Merge branch 'gw_v3_dev'

0bb46c7a · Denia Bouhired-Ferrag · 73525861 · 07f48154 · 0bb46c7a · 0bb46c7a
Commit 0bb46c7a authored Jul 13, 2017 by Denia Bouhired-Ferrag
22 changed files
--- a/doc/cern-title.tex
+++ b/doc/cern-title.tex
@@ -9,7 +9,7 @@
 \noindent \rule{\textwidth}{.1cm}
-\hfill January 26, 2014
+\hfill 17 February 2017
 \vspace*{3cm}
@@ -24,7 +24,9 @@
 %---------------------------------------------------------------
 % name
 %---------------------------------------------------------------
-\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
+\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
+\noindent {Last modified by \textit{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}\\
 \noindent \rule{\textwidth}{.05cm}

--- a/doc/conv-common-gw.bib
+++ b/doc/conv-common-gw.bib
@@ -21,8 +21,14 @@
  note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
 }
+@misc{bib:doulos-counter,
+  title = {{Repository for converter board common gateware}},
+  note = {\url{https://www.doulos.com/knowhow/fpga/fastcounter/}}
+}
 @misc{board-id,
-  title = {{Board IDs for level conversion circuits}},
+  title = {{A counter for fast events, using a Flancter}},
  note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
 }

--- a/doc/conv-common-gw.tex
+++ b/doc/conv-common-gw.tex
@@ -197,15 +197,15 @@ and despite their seemingly dedicated name, they are also general-purpose switch
 time of writing of this document. Therefore, they are considered as \textit{other switches},
 due to the fact they do not appear on the CONV-TTL-BLO.
 The state of the general-purpose switches can be read from the status register
-(SR -- see Appendix~\ref{app:conv-regs-sr}), and the state of the MultiCast
+(SR -- see Appendix~\ref{app:conv-regs-SR}), and the state of the MultiCast
-switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-oswr}).
+switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-OSWR}).
 A total of 32 dedicated switches can be implemented on converter boards and mapped to the OSWR, should
 they be required. This number-of-32 constraint is imposed by the number of bits in the OSWR.
 Table~\ref{tbl:switches} summarizes the switches on converter boards.
-\begin{table}[h]
+\begin{table}[ht]
  \caption{\label{tbl:switches} Switches on converter boards}
  \rowcolors{2}{white}{gray!25}
  \centerline {
@@ -214,10 +214,10 @@ Table~\ref{tbl:switches} summarizes the switches on converter boards.
      \multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Comments}} \\
      \hline
      General-purpose & Eight switches that \textit{should} be implemented on all converter boards.
-                        Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-sr}) \\
+                        Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-SR}) \\
      Other & Dedicated switches for specific converter boards.
-              Read their state from the OSWR register
+        y      Read their state from the OSWR register
-              (see Appendix~\ref{app:conv-regs-oswr}) \\
+              (see Appendix~\ref{app:conv-regs-OSWR}) \\
      \hline
    \end{tabular}
  }
@@ -277,7 +277,7 @@ an external reset is received. The external reset can come from one of two sourc
 \begin{itemize}
  \item the VME system reset pin
  \item a write to the CR.RST bit, after having been previously unlocked by a write to the
-  CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-cr})
+  CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-CR})
 \end{itemize}
 The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
@@ -301,9 +301,9 @@ By default, the reset time is set to 100~ms.
 \label{sec:chan-logic}
 The channel logic is presented in Figure~\ref{fig:chan-logic}. The central part
-thereof is a pulse generator which can be configured for pass-through mode, or
+thereof is a pulse generator followed by a burst mode controller. The former can be configured for pass-through mode, or
 fixed-width pulse generation with subsequent pulse rejection after a pulse has
-been generated. The generator can be triggered in two ways:
+been generated. The latter (the burst controller) allows high frequency bursts to be repeated for a limited period of time, as defined by some internal parameters, see Section~\ref{subsec:burst-ctrl}. The generator itself can be triggered in two ways:
 \begin{itemize}
  \item by the pulse input, which can be fed directly to the generator's input,
@@ -398,10 +398,18 @@ For information on the module's implementation, consult its documentation in the
 Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
 When a pulse arrives on either the TTL or blocking side, it is resynchronized
-in the 20~MHz clock domain and passed through a rising edge detector. When
+in the 20~MHz clock domain and passed to a \textit{fast counter} module. Indeed, at high frequencies it was found that internal counters need to be able to cope with high frequency triggers however short.
-a rising edge occurs on the pulse, the counter is incremented by one and stored
-to the channel pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs})
+A so-callod \textit{Flancter}-based counter is therefore used~\cite{bib:doulos-counter}. When
-register.
+a rising edge occurs on the pulse, the result of the counter is stored
+to the channel pulse counter register. On v4 release of the gateware\footnotemark\footnotetext{On preceding releases, there was a single counter per channel, aggregating both types of pulses.}, there are two counters implemented separately for TTL 
+and BLO outputs of each channel (CHxTTLPCR and CHxBLOPCR -- see Appendix~\ref{app:conv-regs}).
+Figure~\ref{fig:pulse-cnt} presents the implementation for the TTL case only, the same is duplicated for the 
+blocking counter.
+The pulse counter register can be written via the \textit{conv\_regs} component as a
+result of an I$^2$C write access to the register's address. At this point, the fastcounter module needs to be reset by the external load command, otherwise, it will keep its old value.
 \begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
@@ -455,7 +463,7 @@ The two counters implemented are:
 \end{itemize}
 The TAI counter can be loaded with a new value by writing the TVLR and TVHR registers
-(see Appendix~\ref{app:conv-regs-tvlr} and~\ref{app:conv-regs-tvhr}). A load of either
+(see Appendix~\ref{app:conv-regs-TVLR} and~\ref{app:conv-regs-TVHR}). A load of either
 of these registers will reset the internal cycles counter.
 Note that due to the synchronization logic, rising edge detector and the latching of the
@@ -498,9 +506,9 @@ advance on read or write requests from the buffer. While a read can not be perfo
 buffer is empty, a write to a full buffer will start overwriting old timestamps.
 For converter board designs, a caution should be put in place. Because the TBMR
-register (see Appendix~\ref{app:conv-regs-tbmr}) causes the read pointer to advance,
+register (see Appendix~\ref{app:conv-regs-TBMR}) causes the read pointer to advance,
-it should be the last register read in a readout cycle (Table~\ref{tbl:timetag-rd-seq}).
+it should be the last register read in a readout cycle. Otherwise, the values of the
-Otherwise, the values of the other tag buffer registers will return the next sample in the tag buffer.
+other tag buffer registers will return the next sample in the tag buffer.
 \begin{figure}
  \centerline{\includegraphics[width=.97\textwidth]{fig/timetag-buf-mech}}
@@ -576,7 +584,20 @@ The FSM waits in each state indefinitely for a value to be input.
 \end{figure}
 %------------------------------------------------------------------------------
-\subsection{Pulse generator}
+\subsection{Pulse generation and dynamic burst control}
+For hardware v4 of the CONV-TTL-BLO in particular (CONV-TTL-RS485 boards outputs are not sensitive to repetition frequency), release 4 of the gateware includes a \textit{burst mode} capability. Pulses output from the (\textit{conv\_pulse\_gen}) block, Sec~\ref{subsec:pulse-gen}, are fed onto to the \textit{conv\_dyn\_burst\_ctrl}, Sec~\ref{subsec:burst-ctrl}, where frequencies are limited over time and not on a pulse by pulse basis.
+Moreover, v4 boards, give the possibility to select pulse width at the output via a \textit{general-purpose switch}. In addition to that, and for backwards compatibility with v3 boards and earlier, a fixed width, fixed frequency output is also available on the output for legacy boards\footnotemark.\footnotetext{These boards cannot handle high frequencies purely because of their hardware design and in that case \textit{burst mode} is disabled.}
+Figure~\ref{fig:pulse-out-sel} shows how the output is selected depending on whether \textit{burst\_en\_n\_i} is activated or not, and also on which pulse width is selected (options are for \textit{SHORT} and \textit{LONG} pulses).
+\begin{figure}[h]
+  \centerline{\includegraphics[width=\textwidth]{fig/pulse-out-select}}
+  \caption{\label{fig:pulse-out-sel} Pulse repetition output selection}
+\end{figure}
+\subsubsection{Pulse generator}
 \label{subsec:pulse-gen}
 %------------------------------------------------------------------------------
@@ -591,7 +612,7 @@ When an output stage is sensitive to the pulse duty cycle, such as in the TTL to
 blocking converter (CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}), the \textit{g\_pgen\_fixed\_width}
 generic can be set to \textit{true} and this will synthesize a pulse generator
 which outputs a pulse with a fixed width (\textit{g\_pgen\_pwidth}) and fixed
-duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
+period (\textit{g\_pgen\_pperiod}).
 \begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
@@ -600,19 +621,51 @@ duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
 In this latter case, a finite-state machine (FSM) handles pulse generation and rejection.
 Its general operation is shown in Figure~\ref{fig:pulse-gen-operation}.
-The operation of the pulse generator depends on whether the glitch filter is enabled.
+The operation of the pulse generator is agnostic of whether the signal is de-glitched or not\footnotemark\footnotetext{This module has seen a complete redesign in comparison with the one used in release v3.0. This is because it had different signal paths for the asynchronous external trigger and the de-glitched version. This has made for a more complex logic, which the new module tries to simplify by using the same logic whether the signal is glitch-filtered or not} and 
-If this is enabled, then the pulse is synchronized externally to the \textit{conv\_pulse\_gen}
+so is independent of whether it is synchronous (de-glitched) or asynchronous to the system clock. 
-block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the trigger
+After the pulse width has been reached, the FSM 
-input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized and the
+resets the input flip-flop and goes into the rejection state.
-FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM resets
-the input flip-flop and goes into the rejection state. If any pulses arrive either during the generation
-state or the rejection state, the pulse is rejected and the error output is set high for one clock cycle.
-\begin{figure}[h]
+If any pulses arrive either during the generation state, or the rejection state, the error output
+is set high for one clock cycle. This type of error is identified as a \textit{flim\_err\_p}. It is the result of the maximum allowed frequency being reached.
+\begin{figure}
  \centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
  \caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
 \end{figure}
+\subsubsection{Dynamic burst controller}
+\label{subsec:burst-ctrl}
+The dynamic burst control block emulates temperature rise when new pulses arrive, when the 
+temperature counter reaches a pre-set maximum value (corresponding to maximum temperature), the 
+burst controller starts missing 
+pulses. This means that the board needs to \textit{cool off} between pulses and therefore 
+implements rejection only as long as the temperature is above the maximum. As soon as recovery is 
+achieved (temperature is again below maximum) the board starts repeating again. 
+The time at which the rejection starts depends on the frequency of the pulses coming out of the 
+\textit{Pulse Generator} block. For high frequencies, temperature will rise quickly and pulses 
+are rejected earlier. The lower the frequency the longer are repetition times.
+The information relating repetition frequency and repetition times is embedded inside the FPGA and is generated in pre-processing and fed as a generic to the entity. The values used for a given thermal model is an array of constant values input as the \textit{g\_temp\_decre\_step} generic.
+%They differ for the SHORT and LONG pulse implementations. Appendix~\ref{app:} shows how these values can be generated in pre-processing.
+In terms of gateware implementation, see Fig.\ref{fig:burst_ctrl}, the \textit{conv\_dyn\_burst\_ctrl}, module uses a finite 
+state machine (FSM) to handle transitions between pulse repetition and pulse rejection depending 
+on the \textit{temp\_rise} counter value. 
+The FSM is triggered by pulse signals \textit{pulse\_r\_edge\_p\_i} and \textit{pulse\_f\_edge\_p\_i} 
+that had been generated as a result of synchronisation inside the \textit{Pulse Generator} block. The 
+FSM outputs a \textit{burst\_ctrl\_rst} signal as a select signal to a multiplexer. The block's output replicates the input or clears it depending on the status of the \textit{burst\_ctrl\_rst} signal.
+An error pulse is generated every time a pulse is missed. This is the \textit{frequency watchdog error}, \textit{fwdg\_err\_p}, which signifies that the board has started to miss pulses in order to limit temperature rise.
+\begin{figure}[h]
+  \centerline{\includegraphics[width=\textwidth]{fig/burst-ctrl}}
+  \caption{\label{fig:burst_ctrl} Dynamic burst controller block}
+\end{figure}
 %------------------------------------------------------------------------------
 \subsection{Pulse LED control}
 \label{subsec:pulse-led}
@@ -620,7 +673,7 @@ state or the rejection state, the pulse is rejected and the error output is set
 A rising edge on the \textit{pulse\_o} signal from the \textit{conv\_pulse\_gen}
 block generates a 26-ms active-high pulse signal on the \textit{led\_pulse\_o} port of
-\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output.
+\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output. The same logic is used to drive LEDs on the inverting channels.
 %==============================================================================
 % SEC: Memory-mapped peripherals
@@ -742,29 +795,28 @@ The \textit{xwb\_xil\_multiboot} module from the \textit{general-cores} library~
 is used to provide MultiBoot functionality via I$^2$C. To find out more about the
 module and how to use it, consult its documentation under the \textit{general-cores/doc/} folder.
-%==============================================================================
+%%==============================================================================
-\subsection{One-wire master}
+\subsection{One-wire temperature}
 \label{subsec:onewire}
-%==============================================================================
+%%==============================================================================
+The \textit{conv\_common\_gw} used a one-wire interface module (\textit{gc\_ds182x\_interface}) to the one-wire ds182x thermometer chip present on the board.  
-\begin{tabular}{p{.96\textwidth}}
+The module requires the thermometer input \textit{thermometer\_b}, directly from the board plus a pps (pulse-per-second) signal (generated by \textit{wf\_decr\_counter} component). This interface outputs the chip unique ID as a 64-bit value, and the board temperature as a 16-bit value. These 2 values result in 3 memory mapped registers, 2, 32-bit registers for the chip ID, and 1 for the temperature. 
-\hline
+.
-\large \hspace*{22pt} Synthesized when \textit{g\_with\_thermometer $=>$ true}. \\
+%%==============================================================================
-\hline
+%\subsection{One-wire master}
-\end{tabular}
+%\label{subsec:onewire}
+%%==============================================================================
-\vspace*{11pt}
+%
+%Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
-Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
+%which can be used for monitoring the temperature of, and obtaining a unique
-which can be used for monitoring the temperature of, and obtaining a unique
+%identifier for the board.
-identifier for the board.
+%
+%The one-wire master module provides two registers for software control of the module.
-The one-wire master module provides two registers for software control of the module.
+%Note that the FPGA does not control the one-wire thermometer lines in any way.
-Note that the FPGA does not control the one-wire thermometer lines in any way.
+%Accessing the thermometer is done through software only.
-Accessing the thermometer is done through software only.
+%
+%More details about how to access the one-wire master module can be found in its
-More details about how to access the one-wire master module can be found in its
+%documentation~\cite{onewire-core}.
-documentation~\cite{onewire-core}.
 %==============================================================================
 % Appendices
@@ -798,7 +850,7 @@ The following sections list the memory map of each peripheral.
  \hline
  Board registers & 0x000 & 0x0ff & Coverter board registers \\
  MultiBoot       & 0x100 & 0x11f & MultiBoot module \\
-  One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
+  %One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
  SDB descriptor  & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
  \hline
  \end{tabular}
@@ -818,34 +870,34 @@ The following sections list the memory map of each peripheral.
 %------------------------------------------------------------------------------
 % SUBSEC: Thermo
 %------------------------------------------------------------------------------
-\subsection{Thermometer module}
+%\subsection{Thermometer module}
-\label{app:memmap-thermo}
+%\label{app:memmap-thermo}
+%
-\indent Base address: 0x200
+%\indent Base address: 0x200
+%
-\vspace*{11pt}
+%\vspace*{11pt}
+%
-\centerline
+%\centerline
-{
+%{
-  \rowcolors{2}{white}{gray!25}
+  %\rowcolors{2}{white}{gray!25}
-  \begin{tabular}{l l l p{.5\textwidth}}
+  %\begin{tabular}{l l l p{.5\textwidth}}
-  \hline
+  %\hline
-  \textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
+  %\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
-  \hline
+  %\hline
-  0x00            & 0x00000000       & OWCSR         & One-Wire Control and Status Register \\
+  %0x00            & 0x00000000       & OWCSR         & One-Wire Control and Status Register \\
-  0x04            & 0x00000004       & OWCDR         & One-Wire Clock Divider Registers \\
+  %0x04            & 0x00000004       & OWCDR         & One-Wire Clock Divider Registers \\
-  \hline
+  %\hline
-  \end{tabular}
+  %\end{tabular}
-}
+%}
+%
-\vspace*{11pt}
+%\vspace*{11pt}
+%
-For details on the bits of the thermometer module access registers, see the
+%For details on the bits of the thermometer module access registers, see the
-OneWire Master module's documentation~\cite{onewire-core}.
+%OneWire Master module's documentation~\cite{onewire-core}.
+%
-Note that the OWCDR should be set accordingly for proper functioning of the
+%Note that the OWCDR should be set accordingly for proper functioning of the
-one-wire timings. The value for the current version of the gateware is
+%one-wire timings. The value for the current version of the gateware is
-\verb-OWCDR = 0x00130063-.
+%\verb-OWCDR = 0x00130063-.
 %==============================================================================
 % APP: Changing the code for more than six pulse repetition channels

--- a/doc/conv-regs.tex
+++ b/doc/conv-regs.tex
@@ -17,54 +17,69 @@ Base address: 0x000
 \endhead
 \hline
 \endfoot
-0x0 & \textit{g\_board\_id} & BIDR & Board ID Register\\
+0x0& 0x54424c4f & BIDR & Board ID Register\\
-0x4 & (1)        & SR & Status Register\\
+0x4& Note(1)& SR & Status Register\\
-0x8 & 0x00000000 & CR & Control Register\\
+0x8& 0x00000000 & ERR & Error Register\\
-0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
+0xc& 0x00000000 & CR &  Control Register\\
-0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
+0x10& 0x00000000 & CH1TTLPCR & Channel 1 TTL Pulse Counter Register\\
-0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
+0x14& 0x00000000 & CH2TTLPCR & Channel 2 TTL Pulse Counter Register\\
-0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
+0x18& 0x00000000 & CH3TTLPCR & Channel 3 TTL Pulse Counter Register\\
-0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
+0x1c& 0x00000000 & CH4TTLPCR & Channel 4 TTL Pulse Counter Register\\
-0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
+0x20& 0x00000000 & CH5TTLPCR & Channel 5 TTL Pulse Counter Register\\
-0x24 & 0x00000000 & TVLR & Time Value Low Register\\
+0x24& 0x00000000 & CH6TTLPCR & Channel 6 TTL Pulse Counter Register\\
-0x28 & 0x00000000 & TVHR & Time Value High Register\\
+0x28& 0x00000000 & CH1BLOPCR & Channel 1 BLO Pulse Counter Register\\
-0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
+0x2c& 0x00000000 & CH2BLOPCR & Channel 2 BLO Pulse Counter Register\\
-0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
+0x30& 0x00000000 & CH3BLOPCR & Channel 3 BLO Pulse Counter Register\\
-0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
+0x34& 0x00000000 & CH4BLOPCR & Channel 4 BLO Pulse Counter Register\\
-0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
+0x38& 0x00000000 & CH5BLOPCR & Channel 5 BLO Pulse Counter Register\\
-0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
+0x3c& 0x00000000 & CH6BLOPCR & Channel 6 BLO Pulse Counter Register\\
-0x40 & 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
+0x40& 0x00000000 & TVLR & Time Value Low Register\\
-0x44 & 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
+0x44& 0x00000000 & TVHR & Time Value High Register\\
-0x48 & 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
+0x48& 0x00000000 & TBMR & Tag Buffer Meta Register\\
-0x4c & 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
+0x4c& 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
-0x50 & 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
+0x50& 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
-0x54 & 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
+0x54& 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
-0x58 & 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
+0x58& 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
-0x5c & 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
+0x5c& 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
-0x60 & 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
+0x60& 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
-0x64 & 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
+0x64& 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
-0x68 & 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
+0x68& 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
-0x6c & 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
+0x6c& 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
-0x70 & 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
+0x70& 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
-0x74 & 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
+0x74& 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
-0x78 & 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
+0x78& 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
-0x7c & 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
+0x7c& 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
-0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
+0x80& 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
-0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
+0x84& 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
-0x88 & (2) & LSR & Line Status Register\\
+0x88& 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
-0x8c & 0x00000000 & OSWR & Other Switches Register\\
+0x8c& 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
+0x90& 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
+0x94& 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
+0x98& 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
+0x9c& 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
+0xa0& 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
+0xa4& Note(2) & LSR & Line Status Register\\
+0xa8& 0x00000000 & OSWR & Other switch register\\
+0xac& Unique ID & UIDLR & Thermometer ID Low register\\
+0xb0& Unique ID & UIDHR & Thermometer ID High register\\
+0xb4& 0x00000000 & TEMPR & Board Temperature Register\\
+\hline
 \end{longtable}
 }
 \noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
 gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
 \noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
 is plugged into the channel or not.
 \vspace{11pt}
 \subsubsection{BIDR -- Board ID Register}
-\label{app:conv-regs-bidr}
+\label{app:conv-regs-BIDR}
 \vspace{11pt}
 \noindent
@@ -95,27 +110,30 @@ is plugged into the channel or not.
 BIDR
 } [\emph{read-only}]: ID register bits
 \\
-Reset value: \textit{g\_board\_id}
+Reset value: 0x54424c4f
 \end{small}
 \item \begin{small}
 \textbf{Unimplemented bits}: write as '0', read undefined
 \end{small}
 \end{itemize}
 \vspace{11pt}
 \subsubsection{SR -- Status Register}
-\label{app:conv-regs-sr}
+\label{app:conv-regs-SR}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{1}{|c}{-} & \multicolumn{6}{|c|}{\cellcolor{gray!25}PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
+\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{4}{|c|}{\cellcolor{gray!25}HWVERS[5:2]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
+\multicolumn{2}{|c|}{\cellcolor{gray!25}HWVERS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
@@ -141,21 +159,21 @@ Leftmost nibble hex value is major release decimal value \\
 SWITCHES
 } [\emph{read-only}]: Status of on-board general-purpose switches
 \\
-1 -- switch is ON \\		     0 -- switch is OFF
+Eg: SW1.1-- SR.SWITCHES[0] \\                     SW1.2-- SR.SWITCHES[1] \\                     SW2.1-- SR.SWITCHES[4] \\                     SW2.4-- SR.SWITCHES[7] \\                     1 -- switch is ON \\                     0 -- switch is OFF
 \end{small}
 \item \begin{small}
 {\bf 
 RTM
-} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
+} [\emph{read-only}]: RTM detection lines cite{rtm-det}
 \\
-1 -- line active \\                     0 -- line inactive
+1 bit per RTM output channel \\					 1 -- line active \\                     0 -- line inactive
 \end{small}
 \item \begin{small}
 {\bf 
-I2C\_WDTO
+HWVERS
-} [\emph{read/write}]: I2C communication watchdog timeout error
+} [\emph{read-only}]: Hardware version
 \\
-1 -- timeout occured \\                     0 -- no timeout \\                     This bit can be cleared by writing a '1' to it
+PCB version - Hardwired on the board \\					 Only meaningful for HW v4.0 and over \\					 Earlier versions show 0. The register \\					 uses 4 bits for the version number and\\					 2 bits for the execution.\\		     e.g. \\		     0x010001 -- hw v4.1 \\		     0x010111 -- hw v5.3 \\			 0x00-- hw v3 and earlier
 \end{small}
 \item \begin{small}
 {\bf 
@@ -164,6 +182,42 @@ WRPRES
 \\
 1 -- White Rabbit present \\                     0 -- White Rabbit not present
 \end{small}
+\end{itemize}
+\subsubsection{ERR - Error Register}
+\label{app:conv-regs-ERR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FWDG\_PMISSE[5:0]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{gray!25}FLIM\_PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+I2C\_WDTO
+} [\emph{read/write}]: I2C communication watchdog timeout error
+\\
+1 -- timeout occured \\                     0 -- no timeout \\                     This bit can be cleared by writing a '1' to it
+\end{small}
 \item \begin{small}
 {\bf 
 I2C\_ERR
@@ -173,19 +227,21 @@ I2C\_ERR
 \end{small}
 \item \begin{small}
 {\bf 
-PMISSE
+FLIM\_PMISSE
-} [\emph{read/write}]: Pulse missed error
+} [\emph{read/write}]: Frequency error
 \\
-1 -- pulse arrived during pulse rejection phase \\                     0 -- idle \\                     Bit 0 -- channel 1 \\                     Bit 1 -- channel 2 \\                     etc. \\                     Each bit can be cleared by writing a '1' to it
+1 -- Input above maximum supported frequency \\                     0 -- idle \\                     Bit 0 -- channel 1 \\                     Bit 1 -- channel 2 \\                     etc. \\                     Each bit can be cleared by writing a '1' to it
 \end{small}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+FWDG\_PMISSE
+} [\emph{read/write}]: Frequency watchdog error
+\\
+1 -- Pulse over maximum pulse count for given frequency'  \\                     0 -- idle \\                     Bit 0 -- channel 1 \\                     Bit 1 -- channel 2 \\                     etc. \\                     Each bit can be cleared by writing a '1' to it
 \end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CR - Control Register}
-\subsubsection{CR -- Control Register}
+\label{app:conv-regs-CR}
-\label{app:conv-regs-cr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -220,7 +276,7 @@ RST\_UNLOCK
 \item \begin{small}
 {\bf 
 RST
-} [\emph{read/write}]: Reset bit
+} [\emph{read/write}]: Reset bit - active only if RST\_UNLOCK is 1
 \\
 1 -- initiate logic reset \\                     0 -- no reset
 \end{small}
@@ -235,29 +291,28 @@ Write the following sequence to trigger a pulse: \\                     0xde --
 \textbf{Unimplemented bits}: write as '0', read undefined
 \end{small}
 \end{itemize}
-\vspace{11pt}
-\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
-\label{app:conv-regs-ch1pcr}
+\subsubsection{CH1TTLPCR - Channel 1 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH1TTLPCR}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -265,16 +320,14 @@ Write the following sequence to trigger a pulse: \\                     0xde --
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH1PCR
+CH1TTLPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: TTL pulse counter value
-\end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
 \end{small}
 \end{itemize}
-\vspace{11pt}
-\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
-\label{app:conv-regs-ch2pcr}
+\subsubsection{CH2TTLPCR - Channel 2 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH2TTLPCR}
 \vspace{11pt}
 \noindent
@@ -282,19 +335,19 @@ CH1PCR
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -302,16 +355,46 @@ CH1PCR
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH2PCR
+CH2TTLPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: TTL pulse counter value
 \end{small}
+\end{itemize}
+\subsubsection{CH3TTLPCR - Channel 3 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH3TTLPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+CH3TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
 \end{small}
 \end{itemize}
-\vspace{11pt}
-\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
-\label{app:conv-regs-ch3pcr}
+\subsubsection{CH4TTLPCR - Channel 4 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH4TTLPCR}
 \vspace{11pt}
 \noindent
@@ -319,19 +402,19 @@ CH2PCR
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -339,16 +422,46 @@ CH2PCR
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH3PCR
+CH4TTLPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: TTL pulse counter value
 \end{small}
+\end{itemize}
+\subsubsection{CH5TTLPCR - Channel 5 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH5TTLPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+CH5TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
 \end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH6TTLPCR - Channel 6 Pulse Counter Register for TTL pulses}
-\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
+\label{app:conv-regs-CH6TTLPCR}
-\label{app:conv-regs-ch4pcr}
 \vspace{11pt}
 \noindent
@@ -356,19 +469,19 @@ CH3PCR
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -376,16 +489,45 @@ CH3PCR
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH4PCR
+CH6TTLPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: TTL pulse counter value
 \end{small}
+\end{itemize}
+\subsubsection{CH1BLOPCR - Channel 1 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH1BLOPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+CH1BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
 \end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH2BLOPCR - Channel 2 Pulse Counter Register for BLO pulses}
-\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
+\label{app:conv-regs-CH2BLOPCR}
-\label{app:conv-regs-ch5pcr}
 \vspace{11pt}
 \noindent
@@ -393,19 +535,19 @@ CH4PCR
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -413,16 +555,46 @@ CH4PCR
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH5PCR
+CH2BLOPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: BLO pulse counter value
 \end{small}
+\end{itemize}
+\subsubsection{CH3BLOPCR - Channel 3 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH3BLOPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+CH3BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
 \end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH4BLOPCR - Channel 4 Pulse Counter Register for BLO pulses}
-\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
+\label{app:conv-regs-CH4BLOPCR}
-\label{app:conv-regs-ch6pcr}
 \vspace{11pt}
 \noindent
@@ -430,19 +602,19 @@ CH5PCR
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -450,16 +622,80 @@ CH5PCR
 \begin{itemize}
 \item \begin{small}
 {\bf 
-CH6PCR
+CH4BLOPCR
-} [\emph{read/write}]: Pulse counter value
+} [\emph{read/write}]: BLO pulse counter value
 \end{small}
+\end{itemize}
+\subsubsection{CH5BLOPCR - Channel 5 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH5BLOPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+CH5BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
 \end{small}
 \end{itemize}
+\subsubsection{CH6BLOPCR - Channel 6 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH6BLOPCR}
 \vspace{11pt}
-\subsubsection{TVLR -- Time Value Low Register}
+\noindent
-\label{app:conv-regs-tvlr}
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH6BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{TVLR - Time Value Low Register}
+\label{app:conv-regs-TVLR}
 \vspace{11pt}
 \noindent
@@ -492,13 +728,11 @@ TVLR
 \\
 Writing this field resets the internal cycles counter.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{TVHR - Time Value High Register}
-\subsubsection{TVHR -- Time Value High Register}
+\label{app:conv-regs-TVHR}
-\label{app:conv-regs-tvhr}
 \vspace{11pt}
 \noindent
@@ -531,14 +765,9 @@ TVHR
 \\
 Writing this field resets the internal cycles counter.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{TBMR - Tag Buffer Meta Register}
-\subsubsection{TBMR -- Tag Buffer Meta Register}
+\label{app:conv-regs-TBMR}
-\label{app:conv-regs-tbmr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -577,16 +806,9 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
-\item \begin{small}
-\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{TBCYR - Tag Buffer Cycles Register}
-\subsubsection{TBCYR -- Tag Buffer Cycles Register}
+\label{app:conv-regs-TBCYR}
-\label{app:conv-regs-tbcyr}
 \vspace{11pt}
 \noindent
@@ -619,13 +841,11 @@ TBCYR
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{TBTLR - Tag Buffer TAI Low Register}
-\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
+\label{app:conv-regs-TBTLR}
-\label{app:conv-regs-tbtlr}
 \vspace{11pt}
 \noindent
@@ -658,14 +878,10 @@ TBTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\pagebreak
+\subsubsection{TBTHR - Tag Buffer TAI High Register}
-\vspace{11pt}
+\label{app:conv-regs-TBTHR}
-\subsubsection{TBTHR -- Tag Buffer TAI High Register}
-\label{app:conv-regs-tbthr}
 \vspace{11pt}
 \noindent
@@ -698,14 +914,9 @@ TBTHR
 \\
 Value of the TAI seconds counter bits 39..32 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{TBCSR - Tag Buffer Control and Status Register}
-\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
+\label{app:conv-regs-TBCSR}
-\label{app:conv-regs-tbcsr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -758,14 +969,9 @@ CLR
 \\
 1 -- clear\\      0 -- no effect
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH1LTSCYR - Channel 1 Latest Timestamp Cycles Register}
-\subsubsection{CH1LTSCYR -- Channel 1 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH1LTSCYR}
-\label{app:conv-regs-ch1ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -793,17 +999,14 @@ CLR
 \item \begin{small}
 {\bf 
 CH1LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH1LTSTLR - Channel 1 Latest Timestamp TAI Low Register}
-\subsubsection{CH1LTSTLR -- Channel 1 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH1LTSTLR}
-\label{app:conv-regs-ch1ltstlr}
 \vspace{11pt}
 \noindent
@@ -836,15 +1039,10 @@ CH1LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH1LTSTHR - Channel 1 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH1LTSTHR}
-\pagebreak
-\subsubsection{CH1LTSTHR -- Channel 1 Latest Timestamp TAI High Register}
-\label{app:conv-regs-ch1ltsthr}
 \vspace{11pt}
 \noindent
@@ -884,14 +1082,9 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH2LTSCYR - Channel 2 Latest Timestamp Cycles Register}
-\subsubsection{CH2LTSCYR -- Channel 2 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH2LTSCYR}
-\label{app:conv-regs-ch2ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -919,18 +1112,13 @@ WRTAG
 \item \begin{small}
 {\bf 
 CH2LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH2LTSTLR - Channel 2 Latest Timestamp TAI Low Register}
-\subsubsection{CH2LTSTLR -- Channel 2 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH2LTSTLR}
-\label{app:conv-regs-ch2ltstlr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -962,14 +1150,9 @@ CH2LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH2LTSTHR - Channel 2 Latest Timestamp TAI High Register}
-\subsubsection{CH2LTSTHR -- Channel 2 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH2LTSTHR}
-\label{app:conv-regs-ch2ltsthr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1008,14 +1191,9 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH3LTSCYR - Channel 3 Latest Timestamp Cycles Register}
-\subsubsection{CH3LTSCYR -- Channel 3 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH3LTSCYR}
-\label{app:conv-regs-ch3ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1043,18 +1221,13 @@ WRTAG
 \item \begin{small}
 {\bf 
 CH3LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH3LTSTLR - Channel 3 Latest Timestamp TAI Low Register}
-\subsubsection{CH3LTSTLR -- Channel 3 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH3LTSTLR}
-\label{app:conv-regs-ch3ltstlr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1086,15 +1259,9 @@ CH3LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH3LTSTHR - Channel 3 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH3LTSTHR}
-\pagebreak
-\subsubsection{CH3LTSTHR -- Channel 3 Latest Timestamp TAI High Register}
-\label{app:conv-regs-ch3ltsthr}
 \vspace{11pt}
 \noindent
@@ -1134,33 +1301,28 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH4LTSCYR - Channel 4 Latest Timestamp Cycles Register}
-\subsubsection{CH4LTSCYR -- Channel 4 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH4LTSCYR}
-\label{app:conv-regs-ch4ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TAI[27:24]}\\
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH4LTSCYR[27:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -1168,19 +1330,14 @@ WRTAG
 \begin{itemize}
 \item \begin{small}
 {\bf 
-TAI
+CH4LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH4LTSTLR - Channel 4 Latest Timestamp TAI Low Register}
-\subsubsection{CH4LTSTLR -- Channel 4 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH4LTSTLR}
-\label{app:conv-regs-ch4ltstlr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1212,14 +1369,9 @@ CH4LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH4LTSTHR - Channel 4 Latest Timestamp TAI High Register}
-\subsubsection{CH4LTSTHR -- Channel 4 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH4LTSTHR}
-\label{app:conv-regs-ch4ltsthr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1258,14 +1410,9 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH5LTSCYR - Channel 5 Latest Timestamp Cycles Register}
-\subsubsection{CH5LTSCYR -- Channel 5 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH5LTSCYR}
-\label{app:conv-regs-ch5ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1293,18 +1440,13 @@ WRTAG
 \item \begin{small}
 {\bf 
 CH5LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH5LTSTLR - Channel 5 Latest Timestamp TAI Low Register}
-\subsubsection{CH5LTSTLR -- Channel 5 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH5LTSTLR}
-\label{app:conv-regs-ch5ltstlr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1336,15 +1478,9 @@ CH5LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH5LTSTHR - Channel 5 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH5LTSTHR}
-\pagebreak
-\subsubsection{CH5LTSTHR -- Channel 5 Latest Timestamp TAI High Register}
-\label{app:conv-regs-ch5ltsthr}
 \vspace{11pt}
 \noindent
@@ -1384,14 +1520,9 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH6LTSCYR - Channel 6 Latest Timestamp Cycles Register}
-\subsubsection{CH6LTSCYR -- Channel 6 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH6LTSCYR}
-\label{app:conv-regs-ch6ltscyr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1419,17 +1550,13 @@ WRTAG
 \item \begin{small}
 {\bf 
 CH6LTSCYR
-} [\emph{write-only}]: Cycles counter
+} [\emph{read-only}]: Cycles counter
 \\
 Value of the 8-ns cycles counter when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH6LTSTLR - Channel 6 Latest Timestamp TAI Low Register}
-\subsubsection{CH6LTSTLR -- Channel 6 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH6LTSTLR}
-\label{app:conv-regs-ch6ltstlr}
 \vspace{11pt}
 \noindent
@@ -1462,14 +1589,9 @@ CH6LTSTLR
 \\
 Value of the TAI seconds counter bits 31..0 when time tag was taken.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{CH6LTSTHR - Channel 6 Latest Timestamp TAI High Register}
-\subsubsection{CH6LTSTHR -- Channel 6 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH6LTSTHR}
-\label{app:conv-regs-ch6ltsthr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1508,12 +1630,8 @@ WRTAG
 \\
 1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{LSR - Line Status Register}
-\subsubsection{LSR -- Line Status Register}
 \label{app:conv-regs-lsr}
 \vspace{11pt}
@@ -1582,15 +1700,9 @@ REARFS
 \\
 High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\subsubsection{OSWR - Other Switch Register}
+\label{app:conv-regs-OSWR}
-\subsubsection{OSWR -- Other Switches Register}
-\label{app:conv-regs-oswr}
 \vspace{11pt}
 \noindent
 \resizebox{\textwidth}{!}{
@@ -1622,7 +1734,107 @@ SWITCHES
 \\
 1 -- switch is ON \\      0 -- switch is OFF
 \end{small}
+\end{itemize}
+\subsubsection{UIDLR - 32 LS bits of 1-wire thermometer ID}
+\label{app:conv-regs-UIDLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
 \item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
+{\bf 
+UIDLR
+} [\emph{read-only}]: LS bits of 1-wire DS18B20U thermometer ID
+\end{small}
+\end{itemize}
+\subsubsection{UIDHR - 32 MS bits of 1-wire thermometer ID}
+\label{app:conv-regs-UIDHR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+UIDHR
+} [\emph{read-only}]: MS bits of 1-wire DS18B20U thermometer ID
 \end{small}
 \end{itemize}
+\subsubsection{TEMPR - Temperature Resgister }
+\label{app:conv-regs-TEMPR}
+Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to ${}^{o}C$ as follows: Temp = register value / 16.0
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TEMPR
+} [\emph{read-only}]: TEMP
+\\
+Current on-board temperature
+\end{small}
+\end{itemize}
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--- a/general-cores @ 9a40120b
+++ b/general-cores @ 9a40120b
-Subproject commit 382b46c19757e0c7c8574ebe56f32169c5a84b20
+Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
--- a/modules/conv_dyn_burst_ctrl.vhd
+++ b/modules/conv_dyn_burst_ctrl.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Burst mode control module
+-- Copyright CERN 2017
+--==============================================================================
+--
+-- author: Denia Bouhired (denia.bouhired@cern.ch)
+--
+-- Date of creation: 19-09-2016 
+--
+-- version: 1.0
+--
+-- Description:
+-- This module serves as a burst mode controller. When pulses of  
+-- pre-defined length (250 ns or 1.2us) arrive, depending on the frequency, the 
+-- module will allow the pulse to go through for a pre-defined amount of
+-- time, before going into pulse rejection mode. The rejection lasts for
+-- the time it takes for the "temperature" to reach the upper limit
+-- g_max_temp. For each frequency, the time of failure selected
+-- corresponds to the time it takes to reach g_max_temp for pulses of a given 
+-- frequency. 
+-- The array of values representing the thermal properties at the pulse level 
+-- is given as the array of integers temp_decre_step. This array of values is 
+-- generated in pre-processing via python script (*link to be added*). These 
+-- values correspond to the thermal model of the board components. They are 	
+-- different for short 250ns pulses and long 1.2us pulses.
+-- Any modification to the board specification which would change the 
+-- high frequency operation behaviour, would require changing the 3
+-- parameters g_1_pulse_temp_rise, g_max_temp and t_temp_decre_step. These 
+-- are generated using the Python file (*link to be added*). 
+-- dependencies:
+--    
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.conv_common_gw_pkg.all;
+----------------------------------------------------------------------------
+-- ENTITY DECLARATION
+----------------------------------------------------------------------------
+entity conv_dyn_burst_ctrl is
+	generic
+	(
+		-- Fixed pulse width
+		g_pwidth 			: natural range 2 to 40 	:= 5;
+		-- Array of decrement values derived from the choses thermal model
+		-- The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s, 
+		-- 36.66s and continuous" for pulsing for frequencies 
+		-- 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively.
+		g_temp_decre_step 	: t_temp_decre_step 		:=
+						(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
+		--Scaled temperature rise resulting from a single pulse.
+		g_1_pulse_temp_rise	:in unsigned (19 downto 0)	:= x"01388"; --5000
+		-- Scaled maximum temperature ceiling for pulse inhibition 
+		g_max_temp			:in unsigned (39 downto 0) 	:= x"02540BE400" --10^10
+	);
+	port
+	(
+    -- Clock and active-low reset inputs
+		clk_i        		: in  std_logic;
+		rst_n_i      		: in  std_logic;
+	-- Enable input, high frequency repetition is enabled when '1'
+		en_i         	 	: in  std_logic;
+	-- Asynchronous input pulse with rising and falling edges
+		pulse_burst_i 		: in std_logic;
+		pulse_r_edge_p_i	: in std_logic;
+		pulse_f_edge_p_i	: in std_logic;
+	-- Temp_rise is output for external probing
+		temp_rise_o			: out unsigned (39 downto 0) ;
+	-- Dynamic temperature-controlled ouput pulse train.
+		pulse_burst_o		: out std_logic;
+	-- Burst error output, pulses high for one clock cycle when a pulse arrives
+	-- within a burst rejection phase
+		burst_err_p_o : out std_logic	
+	);
+	end entity conv_dyn_burst_ctrl;
+----------------------------------------------------------------------------
+-- ARCHITECTURE
+----------------------------------------------------------------------------
+	architecture behav of conv_dyn_burst_ctrl is
+	type t_state is (
+		IDLE,			
+		PULSE_REPEAT,	
+		PULSE_REJECT	
+	);
+	signal burst_ctrl_rst			: std_logic;
+	signal temp_rise				: unsigned (39 downto 0) ;
+	signal single_cycle_cnt			: integer;
+	signal n_cycle_cnt				: integer range 1 to g_temp_decre_step'LENGTH;
+	signal thermal_array_lgth :natural := 7;
+	signal thermal_res : natural; -- thermal resolution in clock cycles
+	signal state                     : t_state;
+	signal nxt_state			     : t_state;
+	signal s_pulse_reject, s_pulse_repeat : std_logic;
+	begin
+		thermal_array_lgth <= 7 when g_pwidth = 5 else 16;
+		thermal_res <= g_pwidth; --Resolution depends on i/p pulse width
+	-- Output from module depends on burst_ctrl_rst and en_i
+	---------------------------------------------------------
+		pulse_burst_o <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
+		temp_rise_o <= temp_rise;
+-----------------------------------------------------------------------------
+-- Finite State Machine FSM
+-----------------------------------------------------------------------------
+-- Finite State Machine to control pulse repetition as a function of rising 
+-- board temperature. The FSM relies on temp_rise counter for state transitions
+-----------------------------------------------------------------------------
+-- Process to trigger state transitions
+----------------------------------------
+  p_fsm_transitions: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        state 						<= IDLE;
+      elsif (en_i = '1') then
+		state	 					<= nxt_state;
+      end if;
+    end if;
+  end process;
+-- Process to define FSM states
+--------------------------------
+  p_thermal_fsm_states : process (state, pulse_r_edge_p_i, pulse_f_edge_p_i, 
+												n_cycle_cnt, temp_rise, en_i )
+  begin
+	case state is 
+	-------------------------------------------------------------------------
+	-- The FSM is IDLE, when the board is reset
+	-------------------------------------------------------------------------
+		when IDLE =>
+			if en_i = '1' and pulse_r_edge_p_i = '1' then
+					nxt_state 	<= PULSE_REPEAT;
+			else
+					nxt_state 	<= IDLE; 
+			end if;
+	-------------------------------------------------------------------------
+	-- PULSE_REPEAT pulses are repeated as long as the temperature is below 
+	-- maximum g_max_temp.
+	-- While the temperature counter temp_rise is above 0, the time between 
+	-- 2 pulses is used to decrement it, i.e. to cool down.
+	-------------------------------------------------------------------------
+		when PULSE_REPEAT =>
+			if temp_rise <= g_max_temp then
+					nxt_state <= PULSE_REPEAT;
+			else
+					nxt_state <= PULSE_REJECT;
+			end if;
+	-----------------------------------------------oo-----------------------
+	-- PULSE_REJECT applies when a new pulse causes temperature to exceed 
+	-- maximum value
+	-- i.e. temp_rise >= g_max_temp.
+	------------------------------------------------------------------------
+		when PULSE_REJECT =>
+			if pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp then
+				nxt_state <= PULSE_REPEAT;
+			elsif temp_rise = 0 then
+				nxt_state <= IDLE;
+			else
+				nxt_state <= PULSE_REJECT;
+			end if;
+		when others =>
+            nxt_state <= IDLE;
+	end case;
+	end process p_thermal_fsm_states;
+-- Process to define FSM outputs
+--------------------------------
+	p_thermal_fsm_outputs : process (state, pulse_r_edge_p_i)
+  begin	 
+	-------------------------------------------------------------------------
+	-- In the idle state all outputs are reset
+	-------------------------------------------------------------------------
+	case state is 
+			when IDLE =>
+				burst_ctrl_rst <= '0';
+				burst_err_p_o  <= '0';
+				s_pulse_reject <= '0';
+				s_pulse_repeat <= '0';
+	--------------------------------------------------------------------------
+	-- In PULSE_REPEAT pulses the input pulse is copied to the output and 
+	-- the state flag s_pulse_repeat is set
+	--------------------------------------------------------------------------
+			when PULSE_REPEAT =>
+				burst_err_p_o  <= '0';
+				burst_ctrl_rst <= '0';
+				s_pulse_repeat <= '1';
+				s_pulse_reject <= '0';
+	---------------------------------------------------------------------------
+	-- PULSE_REJECT sets burst_ctrl_rst to 1 to cutoff the output and sets the 
+	-- error pulse
+	---------------------------------------------------------------------------
+			when PULSE_REJECT =>
+				burst_err_p_o  <= pulse_r_edge_p_i;
+				burst_ctrl_rst <= '1';
+				s_pulse_reject <= '1';
+				s_pulse_repeat <= '0';
+			when others =>
+				burst_ctrl_rst <= '0';
+				burst_err_p_o  <= '0';
+				s_pulse_reject <= '0';
+				s_pulse_repeat <= '0';
+	end case;
+	end process p_thermal_fsm_outputs;
+	-- Process to count in n clk cycles steps
+	-- single_cycle_cnt counts clock cycles. When it reaches the thermal resolution
+	-- (pulse width dependent) it increments  n_cycle_cnt by 1 and single_cycle_cnt
+	-- is reset to 1 again. n_cycle_cnt is reset to 1 only when a new pulse arrives
+	-- and pulse output inhibition is not active.
+	---------------------------------------------------------------------------
+	p_n_cycle_cnt : process(clk_i)
+	begin
+	if rising_edge(clk_i) then
+		if rst_n_i = '0' then
+				single_cycle_cnt <= 1;
+				n_cycle_cnt   <= 1;
+		else
+			-- Reset counters in the event of a new pulse only 
+			-- when pulse rejection is not active
+			if (pulse_r_edge_p_i = '1' and burst_ctrl_rst = '0') then --OR
+			 --(pulse_f_edge_p_i = '1' and n_cycle_cnt /= 1) then
+				single_cycle_cnt <= 1;
+				n_cycle_cnt   <= 1;
+			else
+				--count clk cycles 
+				single_cycle_cnt <= single_cycle_cnt + 1;
+				if single_cycle_cnt = thermal_res then
+					if n_cycle_cnt < thermal_array_lgth then
+					-- increment every n=thermal_res clk cycles
+						n_cycle_cnt <= n_cycle_cnt + 1;
+					end if;
+						single_cycle_cnt <= 1;
+				end if;
+			end if;
+		end if;
+	end if;
+  end process p_n_cycle_cnt;
+	-- Process to output temperature rise. When a new pulse arrives, 
+	-- temp_rise rises at the falling edge. Between pulses, temp_rise is 
+	-- decremented according to the thermal model. 
+	------------------------------------------------------------------------------
+	p_temp_rise : process(clk_i)
+	begin
+	if rising_edge(clk_i) then
+		if rst_n_i = '0' then
+				temp_rise <=  (others => '0');
+		else
+			if s_pulse_repeat = '1' then
+				if pulse_f_edge_p_i ='1' then
+					temp_rise <= temp_rise + g_1_pulse_temp_rise;
+				else
+					if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
+						temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
+					else
+						temp_rise <= (others => '0');
+					end if;
+				end if;
+			elsif s_pulse_reject = '1' and temp_rise > 0 then
+				if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
+					temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
+				else
+					temp_rise <= (others => '0');
+				end if;
+			end if;
+		end if;
+	end if;
+  end process p_temp_rise;
+	end architecture behav;
\ No newline at end of file
--- a/modules/conv_pulse_gen.vhd
+++ b/modules/conv_pulse_gen.vhd
@@ -3,7 +3,7 @@
 -- Pulse generator with trigger
 --==============================================================================
 --
+-- author: 
 --
 -- date of creation: 2013-03-01
 --
@@ -11,8 +11,9 @@
 --
 -- description:
 --    This module generates a constant-width pulse. The width is set using the
--    g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
+--    g_pwidth generic, given in number of clk_i cycles. The module in principle
--    50 ns, the output pulse width is by default 50*24=1.2 us.
+--    should generate either 250ns pulses or 1.2us. With a clk_i period of
+--    50 ns, the output pulse width is by default 5 or 24clock cycles long respectively.
 --
 --    The module is designed to work with an external glitch filter. Enabling
 --    this glitch filter will result in jitter on the leading edge of the
@@ -24,7 +25,9 @@
 --    g_pwidth. At the end of the pulse, a rejection phase is implemented in order
 --    to avoid too many pulses arriving on the input. This is to safeguard the
 --    blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
--    the input pulse to 1/500 duty cycle.
+--    the input pulse to 1/2 cycles for 250 ns pulses and 1/8 for 1.2 us pulses.
+--    The burst cntrol module placed immediately after this module, will integrate 
+--    pulse repetition frequency over time according to a pre-defined "thermal" model.
 --
 -- dependencies:
 --    none
@@ -44,13 +47,8 @@
 --==============================================================================
 -- last changes:
 --    01-03-2013   Theodor Stana     File created.
--    02-08-2013   Theodor Stana     Implemented rejection phase.
+--    02-03-2017   Denia Bouhired    Almost total re-write of the code to make for a more general FSM
--    17-02-2014   Theodor Stana     Moved the glitch filter to outside the
--                                   module.
--    04-03-2014   Theodor Stana     Added first pulse inhibit on glitch-filtered
--                                   side.
--    24-07-2014   Theodor Stana     Added g_with_fixed_pwidth generic and
--                                   subsequent logic.
 --==============================================================================
 -- TODO: -
 --==============================================================================
@@ -58,6 +56,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.gencores_pkg.all;
 entity conv_pulse_gen is
  generic
@@ -67,12 +66,12 @@ entity conv_pulse_gen is
    -- Pulse width, in number of clk_i cycles
    -- Default pulse width (20 MHz clock): 1.2 us
-    -- Minimum allowable pulse width (20 MHz clock): 1 us
+    -- Minimum allowable pulse width (20 MHz clock): 100 ns
    -- Maximum allowable pulse width (20 MHz clock): 2 us
-    g_pwidth : natural range 20 to 40 := 24;
+    g_pwidth                        : natural range 2 to 40 := 24;
-    -- Duty cycle divider: D = 1/g_duty_cycle_div
+    -- Pulse period in unit of clock cycles
-    g_duty_cycle_div : natural := 5
+    g_pperiod                       : natural := 9
  );
  port
  (
@@ -91,6 +90,9 @@ entity conv_pulse_gen is
    -- Trigger input, has to be '1' to assure pulse output with delay no greater
    -- than internal gate delays.
    trig_a_i                        : in  std_logic;
+    -- Rising and falling edges of the input trigger. Externally synchronised to the clock
+    trig_r_edge_p_i                 : in std_logic; --synced 1 cycle-long r edge output
+    trig_f_edge_p_i                 : in std_logic; --synced 1 cycle-long f edge output
    -- Pulse error output, pulses high for one clock cycle when a pulse arrives
    -- within a pulse period
@@ -100,7 +102,11 @@ entity conv_pulse_gen is
    -- latency:
    --    glitch filter disabled: none
    --    glitch filter enabled: glitch filter length + 5 clk_i cycles
-    pulse_o       : out std_logic
+    pulse_o                         : out std_logic;
+    -- Rising and falling edges of the output pulse, synchronised to the clock
+    pulse_r_edge_p_o                : out std_logic; --synced 1 cycle-long r edge output
+    pulse_f_edge_p_o                : out std_logic
  );
 end entity conv_pulse_gen;
@@ -112,36 +118,32 @@ architecture behav of conv_pulse_gen is
  --============================================================================ 
  type t_state is (
    IDLE,       -- idle state, wait for pulse
-    GEN_GF_OFF, -- pulse generation, glitch filter off
+    CATCH_ERR,       -- idle state, wait for pulse
-    REJ_GF_OFF, -- pulse rejection, glitch filter off
+    GEN_PULSE_OUTPUT, -- pulse generation
-    GEN_GF_ON,  -- pulse generation, glitch filter on
+    REJ_PULSE_INPUT -- pulse rejection
-    REJ_GF_ON   -- pulse rejection, glitch filter on
  );
  --============================================================================
  -- Constant declarations
  --============================================================================
    -- Max value of pulse counter for pulse width and pulse rejection width.
-  -- glitch filter OFF:
+  --   Generate time:
-  --   generate:
+  --        * Maximum pulse width = g_pwidth
-  --     * g_pwidth-1: counter starts from 0
+  --        * Count starts from 0 c_max_gen = pwidth - 1 
-  --     * g_pwidth-4: three-cycle delay through synchronizer
+  --        * Allow three cycle for synchrnised rising edge pwidth-4
-  --     * g_pwidth-5: reset signal applied in REJ_GF_OFF state
+  --        
-  --   reject:
+  constant c_max_gen : natural := g_pwidth-1;
-  --     * g_duty_cycle_div*g_pwidth: D duty cycle
-  --     * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-  -- glitch filter ON:
+  --   Rejection time:
-  --   generate:
+  --        * Maximum pulse period = g_pperiod*g_pwidth
-  --     * g_pwidth-1: counter starts from 0
+  --        * Allow one cycle to change state from REJ_PULSE_INPUT to CATCH_ERR
-  --   reject:
+  constant c_max_rej : natural := g_pperiod-1;
-  --     * g_duty_cycle_div*g_pwidth: D duty cycle
-  --     * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
+  -- Rising edges result from leading edge of trigger going through a 3 stage synchrnoiser.
-  --     duty cycle,
+  -- An extra 1 clock cycle delay is needed before state can be changed.
-  --     since the FSM needs to go through IDLE to accept a pulse
+  constant c_r_edge_sync_delay : natural := 4;
-  constant c_max_gen_gf_off : natural := g_pwidth-5;
-  constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
-  constant c_max_gen_gf_on  : natural := g_pwidth-1;
-  constant c_max_rej_gf_on  : natural := g_duty_cycle_div*g_pwidth - 2;
  --============================================================================
  -- Function and procedure declarations
@@ -159,26 +161,23 @@ architecture behav of conv_pulse_gen is
  --============================================================================
  -- Signal declarations
  --============================================================================
-  -- Trigger signals
+  -- Reset signal combining reset and en signals
-  signal pulse_gf_off_d0       : std_logic;
+  signal gen_edge_n     : std_logic;
-  signal pulse_gf_off_d1       : std_logic;
-  signal pulse_gf_off_d2       : std_logic;
-  signal trig_gf_on            : std_logic;
-  signal trig_gf_on_d0         : std_logic;
-  signal trig_gf_on_r_edge_p   : std_logic;
  -- Pulse output signals
-  signal pulse_gf_on           : std_logic;
+  signal pulse_out_rst_n          : std_logic; -- From FSM
-  signal pulse_gf_off          : std_logic;
+  signal pulse_gf_on           : std_logic; -- Generated from synchronous input 
-  signal pulse_gf_off_rst      : std_logic;
+  signal pulse_gf_off          : std_logic; -- Generated from asynchronous input
-  signal pulse_gf_off_r_edge_p : std_logic;
+  signal pulse_out             : std_logic; -- Selects between pulse_gf_on and pulse_gf_off
  -- Pulse length counter
-  signal pulse_cnt             : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
+  signal pulse_cnt_reset       : std_logic; -- From FSM
+  signal pulse_cnt_clr       : std_logic; -- From FSM
+  signal pulse_cnt             : unsigned(f_log2_size(g_pperiod)-1 downto 0);
-  -- FSM signal
+  -- FSM states
  signal state                 : t_state;
+  signal nxt_state             : t_state;
 --==============================================================================
 --  architecture begin
@@ -191,77 +190,88 @@ gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
 end generate gen_without_fixed_pwidth;
 gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
-  --============================================================================
+  -- ============================================================================
  -- Output logic
-  --============================================================================
+  -- ============================================================================
-  pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
-             pulse_gf_on;
+  -- pulse_out <= pulse_gf_off when (gf_en_n_i = '1') else
+             -- pulse_gf_on;
+  pulse_o <= pulse_out;
+  -- Synchronise output to get correct rising edges and falling edges output pulses
+    gen_edge_n <= rst_n_i and en_i;
+    cmp_sync_ffs : gc_sync_ffs
+    port map
+    (
+      clk_i    => clk_i,
+      rst_n_i  => gen_edge_n,
+      data_i   => pulse_out,
+      ppulse_o => pulse_r_edge_p_o,
+      npulse_o => pulse_f_edge_p_o
+    ); 
  --============================================================================
  -- Pulse generation logic
  --============================================================================
  -- Generate the pulse on rising edge of trig_a_i
-  p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
+  p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i)
  begin
-    if (pulse_gf_off_rst = '1') then
+    if pulse_out_rst_n = '0' then
-      pulse_gf_off <= '0';
+      pulse_out <= '0';
    elsif rising_edge(trig_a_i) then
-      if (en_i = '1') and (gf_en_n_i = '1') then
+      if  (en_i = '1') then 
-        pulse_gf_off <= '1';
+        pulse_out <= '1';
      end if;
    end if;
  end process p_pulse_gf_off;
-  -- and synchronize the trigger in clk_i domain
-  p_sync_pulse_gf_off: process (clk_i) is
+  --============================================================================
+  -- Pulse width adjustment logic
+  --============================================================================
+   p_count_cycles: process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if (rst_n_i = '0') then
+      if rst_n_i = '0' or pulse_cnt_reset = '1' then
-        pulse_gf_off_d0       <= '0';
+        pulse_cnt <= to_unsigned(c_r_edge_sync_delay, f_log2_size(g_pperiod));
-        pulse_gf_off_d1       <= '0';
+      elsif pulse_cnt_clr = '1' then
-        pulse_gf_off_d2       <= '0';
+        pulse_cnt <= (others => '0');
-        pulse_gf_off_r_edge_p <= '0';
+      else
-      elsif (en_i = '1') and (gf_en_n_i = '1') then
+        pulse_cnt <= pulse_cnt+1;
-        pulse_gf_off_d0       <= pulse_gf_off;
-        pulse_gf_off_d1       <= pulse_gf_off_d0;
-        pulse_gf_off_d2       <= pulse_gf_off_d1;
-        pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
      end if;   
    end if;
-  end process p_sync_pulse_gf_off;
+  end process p_count_cycles; 
-  -- Trigger signal with glitch filter ON is input signal
+-----------------------------------------------------------------------------
-  trig_gf_on <= trig_a_i;
+-- Finite State Machine FSM
+-----------------------------------------------------------------------------
-  -- Rising edge detector for the trigger signal when glitch filter is ON
-  p_trig_gf_on : process (clk_i) is
+-- Process to trigger state transitions
+----------------------------------------
+  p_fsm_transitions: process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if (rst_n_i = '0') then
+      if rst_n_i = '0' then
-        trig_gf_on_d0       <= '0';
+        state                   <= IDLE;
-        trig_gf_on_r_edge_p <= '0';
+      elsif (en_i = '1') then
-      else
+        state                   <= nxt_state;
-        trig_gf_on_d0       <= trig_gf_on;
-        trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
      end if;   
    end if;
-  end process p_trig_gf_on;
+  end process;
-  --============================================================================
-  -- Pulse width adjustment logic
+ -- ======================================================================================   
-  --============================================================================
  -- Generate the FSM logic
-  p_pulse_width: process(clk_i)
+  p_fsm_states : process(state, trig_r_edge_p_i, pulse_cnt)
  begin
-    if rising_edge(clk_i) then
-      if (rst_n_i = '0') then
-        state            <= IDLE;
-        pulse_gf_off_rst <= '1';
-        pulse_gf_on      <= '0';
-        pulse_cnt        <= (others => '0');
-        pulse_err_p_o    <= '0';
-      elsif (en_i = '1') then
-        -- State machine logic
        case state is
          ---------------------------------------------------------------------
          -- IDLE
@@ -270,101 +280,122 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
          -- appropriate input arrives
          ---------------------------------------------------------------------
          when IDLE =>
-            pulse_cnt        <= (others => '0');
-            pulse_gf_off_rst <= '0';
+            if trig_r_edge_p_i = '1' then 
-            pulse_err_p_o    <= '0';
+                nxt_state <= GEN_PULSE_OUTPUT;
-            if (gf_en_n_i = '1') then
+            else
-              if (pulse_gf_off_r_edge_p = '1') then
+                nxt_state <= IDLE;
-                state <= GEN_GF_OFF;
            end if;               
+          when CATCH_ERR =>
+            if pulse_cnt >= c_r_edge_sync_delay-1 then
+                if trig_r_edge_p_i = '1' then
+                    nxt_state <= GEN_PULSE_OUTPUT;
                else
-              if (trig_gf_on_r_edge_p = '1') then
+                    nxt_state <= IDLE;
-                state <= GEN_GF_ON;
                end if;
+            else
+                nxt_state     <= CATCH_ERR;
            end if;
          ---------------------------------------------------------------------
-          -- GEN_GF_OFF
+          -- GEN_PULSE_OUTPUT
-          ---------------------------------------------------------------------
+          --------------------------c-------------------------------------------
          -- Extend the generated pulse to the required pulse width.
          ---------------------------------------------------------------------
-          when GEN_GF_OFF =>
+          when GEN_PULSE_OUTPUT =>
-          -- Pulse logic and state change
+            if pulse_cnt = c_max_gen then
-            pulse_cnt <= pulse_cnt + 1;
+                nxt_state   <= REJ_PULSE_INPUT;
-            if (pulse_cnt = c_max_gen_gf_off) then
+            else 
-              state <= REJ_GF_OFF;
+                nxt_state   <= GEN_PULSE_OUTPUT;
-            end if;
-          -- Pulse error assignment
-            pulse_err_p_o <= '0';
-            if (trig_gf_on_r_edge_p = '1') then
-              pulse_err_p_o <= '1';
            end if;
          ---------------------------------------------------------------------
-          -- REJ_GF_OFF
+          -- REJ_PULSE_INPUT
          ---------------------------------------------------------------------
          -- Cut and reject input pulses, to safeguard the output transformers.
          ---------------------------------------------------------------------
-          when REJ_GF_OFF =>
+          when REJ_PULSE_INPUT =>
-          -- Pulse logic and state change
+            if pulse_cnt = c_max_rej then
-            pulse_gf_off_rst <= '1';
+                nxt_state   <= CATCH_ERR;
-            pulse_cnt        <= pulse_cnt + 1;
+            else 
-            if (pulse_cnt = c_max_rej_gf_off) then
+                nxt_state   <= REJ_PULSE_INPUT;
-              state <= IDLE;
            end if;
-          -- Pulse error assignment
+          when others =>
-            pulse_err_p_o <= '0';
+            nxt_state       <= IDLE;
-            if (trig_gf_on_r_edge_p = '1') then
-              pulse_err_p_o <= '1';
+        end case;
-            end if;
+  end process p_fsm_states;
+    -- Generate the FSM logic
+  p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt, rst_n_i)
+  begin
+        case state is
          ---------------------------------------------------------------------
-          -- GEN_GF_ON
+          -- IDLE
          ---------------------------------------------------------------------
-          -- Start generating the output pulse with the required width.
+          -- Clear all values and go to pulse generation state when the
+          -- appropriate input arrives
          ---------------------------------------------------------------------
-          when GEN_GF_ON =>
+          when IDLE =>
-          -- Pulse logic and state change
+            pulse_out_rst_n <= rst_n_i;
-            pulse_cnt   <= pulse_cnt + 1;
+            pulse_err_p_o   <= '0';
-            pulse_gf_on <= '1';
+            pulse_cnt_reset <= '1';
-            if (pulse_cnt = c_max_gen_gf_on) then
+            pulse_cnt_clr   <= '0';
-              state <= REJ_GF_ON;
-            end if;
-          -- Pulse error assignment
+          when CATCH_ERR =>
+            pulse_out_rst_n <= rst_n_i;
+            if pulse_cnt < c_r_edge_sync_delay-1 then
+                    pulse_err_p_o   <= trig_r_edge_p_i;
+            else
                    pulse_err_p_o   <= '0';
-            if (trig_gf_on_r_edge_p = '1') then
-              pulse_err_p_o <= '1';
            end if;
+            pulse_cnt_reset <= '0';
+            pulse_cnt_clr   <= '0';
          ---------------------------------------------------------------------
-          -- REJ_GF_ON
+          -- GEN_PULSE_OUTPUT
+          --------------------------c-------------------------------------------
+          -- Extend the generated pulse to the required pulse width.
          ---------------------------------------------------------------------
-          -- Stop generating the output pulse and reject incoming pulses.
+          when GEN_PULSE_OUTPUT =>
+            pulse_out_rst_n <= rst_n_i;
+            pulse_err_p_o   <= trig_r_edge_p_i;
+            pulse_cnt_reset <= '0';
+            pulse_cnt_clr   <= '0';
          ---------------------------------------------------------------------
-          when REJ_GF_ON =>
+          -- REJ_PULSE_INPUT
-          -- Pulse logic and state change
+          ---------------------------------------------------------------------
-            pulse_gf_on <= '0';
+          -- Cut and reject input pulses, to safeguard the output transformers.
-            pulse_cnt   <= pulse_cnt + 1;
+          ---------------------------------------------------------------------
-            if (pulse_cnt = c_max_rej_gf_on) then
+          when REJ_PULSE_INPUT =>
-              state <= IDLE;
+                pulse_err_p_o   <= trig_r_edge_p_i;
+                pulse_out_rst_n <= '0';
+                pulse_cnt_reset <= '0';
+            if pulse_cnt = c_max_rej then
+                pulse_cnt_clr   <= '1';
+            else 
+                pulse_cnt_clr   <= '0';
            end if;
-          -- Pulse error assignment
-            pulse_err_p_o <= '0';
-            if (trig_gf_on_r_edge_p = '1') then
-              pulse_err_p_o <= '1';
-            end if;
          when others =>
-            state <= IDLE;
+            pulse_out_rst_n     <= '0';
+            pulse_err_p_o       <= '0';
+            pulse_cnt_reset     <= '1';
        end case;
-      end if;
-    end if;
+  end process p_fsm_outputs;
-  end process p_pulse_width;
 end generate gen_with_fixed_pwidth;

--- a/modules/conv_regs.h
+++ b/modules/conv_regs.h
+/*
+  Register definitions for slave core: Converter board registers
+  * File           : conv_regs.h
+  * Author         : auto-generated by wbgen2 from conv_regs.wb
+  * Created        : 02/06/17 15:05:15
+  * Standard       : ANSI C
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+*/
+#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
+#define __WBGEN2_REGDEFS_CONV_REGS_WB
+#include <inttypes.h>
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+/* definitions for register: BIDR */
+/* definitions for register: SR */
+/* definitions for field: Gateware version in reg: SR */
+#define REG_SR_GWVERS_MASK                    WBGEN2_GEN_MASK(0, 8)
+#define REG_SR_GWVERS_SHIFT                   0
+#define REG_SR_GWVERS_W(value)                WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_SR_GWVERS_R(reg)                  WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: Status of on-board general-purpose switches in reg: SR */
+#define REG_SR_SWITCHES_MASK                  WBGEN2_GEN_MASK(8, 8)
+#define REG_SR_SWITCHES_SHIFT                 8
+#define REG_SR_SWITCHES_W(value)              WBGEN2_GEN_WRITE(value, 8, 8)
+#define REG_SR_SWITCHES_R(reg)                WBGEN2_GEN_READ(reg, 8, 8)
+/* definitions for field: RTM detection lines cite{rtm-det} in reg: SR */
+#define REG_SR_RTM_MASK                       WBGEN2_GEN_MASK(16, 6)
+#define REG_SR_RTM_SHIFT                      16
+#define REG_SR_RTM_W(value)                   WBGEN2_GEN_WRITE(value, 16, 6)
+#define REG_SR_RTM_R(reg)                     WBGEN2_GEN_READ(reg, 16, 6)
+/* definitions for field: Hardware version in reg: SR */
+#define REG_SR_HWVERS_MASK                    WBGEN2_GEN_MASK(22, 6)
+#define REG_SR_HWVERS_SHIFT                   22
+#define REG_SR_HWVERS_W(value)                WBGEN2_GEN_WRITE(value, 22, 6)
+#define REG_SR_HWVERS_R(reg)                  WBGEN2_GEN_READ(reg, 22, 6)
+/* definitions for field: White Rabbit present in reg: SR */
+#define REG_SR_WRPRES                         WBGEN2_GEN_MASK(28, 1)
+/* definitions for register: ERR */
+/* definitions for field: I2C communication watchdog timeout error in reg: ERR */
+#define REG_ERR_I2C_WDTO                      WBGEN2_GEN_MASK(0, 1)
+/* definitions for field: I2C communication error in reg: ERR */
+#define REG_ERR_I2C_ERR                       WBGEN2_GEN_MASK(1, 1)
+/* definitions for field: Frequency error in reg: ERR */
+#define REG_ERR_FLIM_PMISSE_MASK              WBGEN2_GEN_MASK(2, 6)
+#define REG_ERR_FLIM_PMISSE_SHIFT             2
+#define REG_ERR_FLIM_PMISSE_W(value)          WBGEN2_GEN_WRITE(value, 2, 6)
+#define REG_ERR_FLIM_PMISSE_R(reg)            WBGEN2_GEN_READ(reg, 2, 6)
+/* definitions for field: Frequency watchdog error in reg: ERR */
+#define REG_ERR_FWDG_PMISSE_MASK              WBGEN2_GEN_MASK(8, 6)
+#define REG_ERR_FWDG_PMISSE_SHIFT             8
+#define REG_ERR_FWDG_PMISSE_W(value)          WBGEN2_GEN_WRITE(value, 8, 6)
+#define REG_ERR_FWDG_PMISSE_R(reg)            WBGEN2_GEN_READ(reg, 8, 6)
+/* definitions for register: CR */
+/* definitions for field: Reset unlock bit in reg: CR */
+#define REG_CR_RST_UNLOCK                     WBGEN2_GEN_MASK(0, 1)
+/* definitions for field: Reset bit - active only if RST_UNLOCK is 1 in reg: CR */
+#define REG_CR_RST                            WBGEN2_GEN_MASK(1, 1)
+/* definitions for field: Manual Pulse Trigger in reg: CR */
+#define REG_CR_MPT_MASK                       WBGEN2_GEN_MASK(2, 8)
+#define REG_CR_MPT_SHIFT                      2
+#define REG_CR_MPT_W(value)                   WBGEN2_GEN_WRITE(value, 2, 8)
+#define REG_CR_MPT_R(reg)                     WBGEN2_GEN_READ(reg, 2, 8)
+/* definitions for register: CH1TTLPCR */
+/* definitions for register: CH2TTLPCR */
+/* definitions for register: CH3TTLPCR */
+/* definitions for register: CH4TTLPCR */
+/* definitions for register: CH5TTLPCR */
+/* definitions for register: CH6TTLPCR */
+/* definitions for register: CH1BLOPCR */
+/* definitions for register: CH2BLOPCR */
+/* definitions for register: CH3BLOPCR */
+/* definitions for register: CH4BLOPCR */
+/* definitions for register: CH5BLOPCR */
+/* definitions for register: CH6BLOPCR */
+/* definitions for register: TVLR */
+/* definitions for register: TVHR */
+/* definitions for register: TBMR */
+/* definitions for field: Channel mask in reg: TBMR */
+#define REG_TBMR_CHAN_MASK                    WBGEN2_GEN_MASK(0, 6)
+#define REG_TBMR_CHAN_SHIFT                   0
+#define REG_TBMR_CHAN_W(value)                WBGEN2_GEN_WRITE(value, 0, 6)
+#define REG_TBMR_CHAN_R(reg)                  WBGEN2_GEN_READ(reg, 0, 6)
+/* definitions for field: White Rabbit present in reg: TBMR */
+#define REG_TBMR_WRTAG                        WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: TBCYR */
+/* definitions for register: TBTLR */
+/* definitions for register: TBTHR */
+/* definitions for register: TBCSR */
+/* definitions for field: Buffer counter in reg: TBCSR */
+#define REG_TBCSR_USEDW_MASK                  WBGEN2_GEN_MASK(0, 7)
+#define REG_TBCSR_USEDW_SHIFT                 0
+#define REG_TBCSR_USEDW_W(value)              WBGEN2_GEN_WRITE(value, 0, 7)
+#define REG_TBCSR_USEDW_R(reg)                WBGEN2_GEN_READ(reg, 0, 7)
+/* definitions for field: Buffer full in reg: TBCSR */
+#define REG_TBCSR_FULL                        WBGEN2_GEN_MASK(16, 1)
+/* definitions for field: Buffer empty in reg: TBCSR */
+#define REG_TBCSR_EMPTY                       WBGEN2_GEN_MASK(17, 1)
+/* definitions for field: Clear tag buffer in reg: TBCSR */
+#define REG_TBCSR_CLR                         WBGEN2_GEN_MASK(18, 1)
+/* definitions for register: CH1LTSCYR */
+/* definitions for register: CH1LTSTLR */
+/* definitions for register: CH1LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH1LTSTHR */
+#define REG_CH1LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH1LTSTHR_TAI_SHIFT               0
+#define REG_CH1LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH1LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH1LTSTHR */
+#define REG_CH1LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: CH2LTSCYR */
+/* definitions for register: CH2LTSTLR */
+/* definitions for register: CH2LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH2LTSTHR */
+#define REG_CH2LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH2LTSTHR_TAI_SHIFT               0
+#define REG_CH2LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH2LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH2LTSTHR */
+#define REG_CH2LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: CH3LTSCYR */
+/* definitions for register: CH3LTSTLR */
+/* definitions for register: CH3LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH3LTSTHR */
+#define REG_CH3LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH3LTSTHR_TAI_SHIFT               0
+#define REG_CH3LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH3LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH3LTSTHR */
+#define REG_CH3LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: CH4LTSCYR */
+/* definitions for register: CH4LTSTLR */
+/* definitions for register: CH4LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH4LTSTHR */
+#define REG_CH4LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH4LTSTHR_TAI_SHIFT               0
+#define REG_CH4LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH4LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH4LTSTHR */
+#define REG_CH4LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: CH5LTSCYR */
+/* definitions for register: CH5LTSTLR */
+/* definitions for register: CH5LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH5LTSTHR */
+#define REG_CH5LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH5LTSTHR_TAI_SHIFT               0
+#define REG_CH5LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH5LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH5LTSTHR */
+#define REG_CH5LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: CH6LTSCYR */
+/* definitions for register: CH6LTSTLR */
+/* definitions for register: CH6LTSTHR */
+/* definitions for field: Upper part of TAI seconds counter in reg: CH6LTSTHR */
+#define REG_CH6LTSTHR_TAI_MASK                WBGEN2_GEN_MASK(0, 8)
+#define REG_CH6LTSTHR_TAI_SHIFT               0
+#define REG_CH6LTSTHR_TAI_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define REG_CH6LTSTHR_TAI_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* definitions for field: White Rabbit present in reg: CH6LTSTHR */
+#define REG_CH6LTSTHR_WRTAG                   WBGEN2_GEN_MASK(31, 1)
+/* definitions for register: LSR */
+/* definitions for field: Front panel channel input state in reg: LSR */
+#define REG_LSR_FRONT_MASK                    WBGEN2_GEN_MASK(0, 6)
+#define REG_LSR_FRONT_SHIFT                   0
+#define REG_LSR_FRONT_W(value)                WBGEN2_GEN_WRITE(value, 0, 6)
+#define REG_LSR_FRONT_R(reg)                  WBGEN2_GEN_READ(reg, 0, 6)
+/* definitions for field: Front panel INV-TTL input state in reg: LSR */
+#define REG_LSR_FRONTINV_MASK                 WBGEN2_GEN_MASK(6, 4)
+#define REG_LSR_FRONTINV_SHIFT                6
+#define REG_LSR_FRONTINV_W(value)             WBGEN2_GEN_WRITE(value, 6, 4)
+#define REG_LSR_FRONTINV_R(reg)               WBGEN2_GEN_READ(reg, 6, 4)
+/* definitions for field: Rear panel input state in reg: LSR */
+#define REG_LSR_REAR_MASK                     WBGEN2_GEN_MASK(10, 6)
+#define REG_LSR_REAR_SHIFT                    10
+#define REG_LSR_REAR_W(value)                 WBGEN2_GEN_WRITE(value, 10, 6)
+#define REG_LSR_REAR_R(reg)                   WBGEN2_GEN_READ(reg, 10, 6)
+/* definitions for field: Front panel input failsafe state in reg: LSR */
+#define REG_LSR_FRONTFS_MASK                  WBGEN2_GEN_MASK(16, 6)
+#define REG_LSR_FRONTFS_SHIFT                 16
+#define REG_LSR_FRONTFS_W(value)              WBGEN2_GEN_WRITE(value, 16, 6)
+#define REG_LSR_FRONTFS_R(reg)                WBGEN2_GEN_READ(reg, 16, 6)
+/* definitions for field: Front panel inverter input failsafe state in reg: LSR */
+#define REG_LSR_FRONTINVFS_MASK               WBGEN2_GEN_MASK(22, 4)
+#define REG_LSR_FRONTINVFS_SHIFT              22
+#define REG_LSR_FRONTINVFS_W(value)           WBGEN2_GEN_WRITE(value, 22, 4)
+#define REG_LSR_FRONTINVFS_R(reg)             WBGEN2_GEN_READ(reg, 22, 4)
+/* definitions for field: Rear panel input failsafe state in reg: LSR */
+#define REG_LSR_REARFS_MASK                   WBGEN2_GEN_MASK(26, 6)
+#define REG_LSR_REARFS_SHIFT                  26
+#define REG_LSR_REARFS_W(value)               WBGEN2_GEN_WRITE(value, 26, 6)
+#define REG_LSR_REARFS_R(reg)                 WBGEN2_GEN_READ(reg, 26, 6)
+/* definitions for register: OSWR */
+/* definitions for field: Switch state in reg: OSWR */
+#define REG_OSWR_SWITCHES_MASK                WBGEN2_GEN_MASK(0, 32)
+#define REG_OSWR_SWITCHES_SHIFT               0
+#define REG_OSWR_SWITCHES_W(value)            WBGEN2_GEN_WRITE(value, 0, 32)
+#define REG_OSWR_SWITCHES_R(reg)              WBGEN2_GEN_READ(reg, 0, 32)
+/* definitions for register: UIDLR */
+/* definitions for register: UIDHR */
+/* definitions for register: TEMPR */
+/* [0x0]: REG BIDR */
+#define REG_REG_BIDR 0x00000000
+/* [0x4]: REG SR */
+#define REG_REG_SR 0x00000004
+/* [0x8]: REG ERR */
+#define REG_REG_ERR 0x00000008
+/* [0xc]: REG CR */
+#define REG_REG_CR 0x0000000c
+/* [0x10]: REG CH1TTLPCR */
+#define REG_REG_CH1TTLPCR 0x00000010
+/* [0x14]: REG CH2TTLPCR */
+#define REG_REG_CH2TTLPCR 0x00000014
+/* [0x18]: REG CH3TTLPCR */
+#define REG_REG_CH3TTLPCR 0x00000018
+/* [0x1c]: REG CH4TTLPCR */
+#define REG_REG_CH4TTLPCR 0x0000001c
+/* [0x20]: REG CH5TTLPCR */
+#define REG_REG_CH5TTLPCR 0x00000020
+/* [0x24]: REG CH6TTLPCR */
+#define REG_REG_CH6TTLPCR 0x00000024
+/* [0x28]: REG CH1BLOPCR */
+#define REG_REG_CH1BLOPCR 0x00000028
+/* [0x2c]: REG CH2BLOPCR */
+#define REG_REG_CH2BLOPCR 0x0000002c
+/* [0x30]: REG CH3BLOPCR */
+#define REG_REG_CH3BLOPCR 0x00000030
+/* [0x34]: REG CH4BLOPCR */
+#define REG_REG_CH4BLOPCR 0x00000034
+/* [0x38]: REG CH5BLOPCR */
+#define REG_REG_CH5BLOPCR 0x00000038
+/* [0x3c]: REG CH6BLOPCR */
+#define REG_REG_CH6BLOPCR 0x0000003c
+/* [0x40]: REG TVLR */
+#define REG_REG_TVLR 0x00000040
+/* [0x44]: REG TVHR */
+#define REG_REG_TVHR 0x00000044
+/* [0x48]: REG TBMR */
+#define REG_REG_TBMR 0x00000048
+/* [0x4c]: REG TBCYR */
+#define REG_REG_TBCYR 0x0000004c
+/* [0x50]: REG TBTLR */
+#define REG_REG_TBTLR 0x00000050
+/* [0x54]: REG TBTHR */
+#define REG_REG_TBTHR 0x00000054
+/* [0x58]: REG TBCSR */
+#define REG_REG_TBCSR 0x00000058
+/* [0x5c]: REG CH1LTSCYR */
+#define REG_REG_CH1LTSCYR 0x0000005c
+/* [0x60]: REG CH1LTSTLR */
+#define REG_REG_CH1LTSTLR 0x00000060
+/* [0x64]: REG CH1LTSTHR */
+#define REG_REG_CH1LTSTHR 0x00000064
+/* [0x68]: REG CH2LTSCYR */
+#define REG_REG_CH2LTSCYR 0x00000068
+/* [0x6c]: REG CH2LTSTLR */
+#define REG_REG_CH2LTSTLR 0x0000006c
+/* [0x70]: REG CH2LTSTHR */
+#define REG_REG_CH2LTSTHR 0x00000070
+/* [0x74]: REG CH3LTSCYR */
+#define REG_REG_CH3LTSCYR 0x00000074
+/* [0x78]: REG CH3LTSTLR */
+#define REG_REG_CH3LTSTLR 0x00000078
+/* [0x7c]: REG CH3LTSTHR */
+#define REG_REG_CH3LTSTHR 0x0000007c
+/* [0x80]: REG CH4LTSCYR */
+#define REG_REG_CH4LTSCYR 0x00000080
+/* [0x84]: REG CH4LTSTLR */
+#define REG_REG_CH4LTSTLR 0x00000084
+/* [0x88]: REG CH4LTSTHR */
+#define REG_REG_CH4LTSTHR 0x00000088
+/* [0x8c]: REG CH5LTSCYR */
+#define REG_REG_CH5LTSCYR 0x0000008c
+/* [0x90]: REG CH5LTSTLR */
+#define REG_REG_CH5LTSTLR 0x00000090
+/* [0x94]: REG CH5LTSTHR */
+#define REG_REG_CH5LTSTHR 0x00000094
+/* [0x98]: REG CH6LTSCYR */
+#define REG_REG_CH6LTSCYR 0x00000098
+/* [0x9c]: REG CH6LTSTLR */
+#define REG_REG_CH6LTSTLR 0x0000009c
+/* [0xa0]: REG CH6LTSTHR */
+#define REG_REG_CH6LTSTHR 0x000000a0
+/* [0xa4]: REG LSR */
+#define REG_REG_LSR 0x000000a4
+/* [0xa8]: REG OSWR */
+#define REG_REG_OSWR 0x000000a8
+/* [0xac]: REG UIDLR */
+#define REG_REG_UIDLR 0x000000ac
+/* [0xb0]: REG UIDHR */
+#define REG_REG_UIDHR 0x000000b0
+/* [0xb4]: REG TEMPR */
+#define REG_REG_TEMPR 0x000000b4
+#endif
--- a/modules/conv_regs.htm
+++ b/modules/conv_regs.htm
--- a/modules/conv_regs.tex
+++ b/modules/conv_regs.tex
+\subsection{Converter board registers}
+\label{subsec:wbgen:reg}
+\subsubsection{Memory map summary}
+\rowcolors{2}{gray!25}{white}
+\resizebox{\textwidth}{!}{
+\begin{tabular}{|l|l|l|l|l|}
+\rowcolor{RoyalPurple}
+\color{white} SW Offset & \color{white} Type & \color{white} Name &
+\color{white} HW prefix & \color{white} C prefix\\
+0x0& REG & BIDR & reg\_bidr & BIDR\\
+0x4& REG & SR & reg\_sr & SR\\
+0x8& REG & ERR & reg\_err & ERR\\
+0xc& REG & CR & reg\_cr & CR\\
+0x10& REG & CH1TTLPCR & reg\_ch1ttlpcr & CH1TTLPCR\\
+0x14& REG & CH2TTLPCR & reg\_ch2ttlpcr & CH2TTLPCR\\
+0x18& REG & CH3TTLPCR & reg\_ch3ttlpcr & CH3TTLPCR\\
+0x1c& REG & CH4TTLPCR & reg\_ch4ttlpcr & CH4TTLPCR\\
+0x20& REG & CH5TTLPCR & reg\_ch5ttlpcr & CH5TTLPCR\\
+0x24& REG & CH6TTLPCR & reg\_ch6ttlpcr & CH6TTLPCR\\
+0x28& REG & CH1BLOPCR & reg\_ch1blopcr & CH1BLOPCR\\
+0x2c& REG & CH2BLOPCR & reg\_ch2blopcr & CH2BLOPCR\\
+0x30& REG & CH3BLOPCR & reg\_ch3blopcr & CH3BLOPCR\\
+0x34& REG & CH4BLOPCR & reg\_ch4blopcr & CH4BLOPCR\\
+0x38& REG & CH5BLOPCR & reg\_ch5blopcr & CH5BLOPCR\\
+0x3c& REG & CH6BLOPCR & reg\_ch6blopcr & CH6BLOPCR\\
+0x40& REG & TVLR & reg\_tvlr & TVLR\\
+0x44& REG & TVHR & reg\_tvhr & TVHR\\
+0x48& REG & TBMR & reg\_tbmr & TBMR\\
+0x4c& REG & TBCYR & reg\_tbcyr & TBCYR\\
+0x50& REG & TBTLR & reg\_tbtlr & TBTLR\\
+0x54& REG & TBTHR & reg\_tbthr & TBTHR\\
+0x58& REG & TBCSR & reg\_tbcsr & TBCSR\\
+0x5c& REG & CH1LTSCYR & reg\_ch1ltscyr & CH1LTSCYR\\
+0x60& REG & CH1LTSTLR & reg\_ch1ltstlr & CH1LTSTLR\\
+0x64& REG & CH1LTSTHR & reg\_ch1ltsthr & CH1LTSTHR\\
+0x68& REG & CH2LTSCYR & reg\_ch2ltscyr & CH2LTSCYR\\
+0x6c& REG & CH2LTSTLR & reg\_ch2ltstlr & CH2LTSTLR\\
+0x70& REG & CH2LTSTHR & reg\_ch2ltsthr & CH2LTSTHR\\
+0x74& REG & CH3LTSCYR & reg\_ch3ltscyr & CH3LTSCYR\\
+0x78& REG & CH3LTSTLR & reg\_ch3ltstlr & CH3LTSTLR\\
+0x7c& REG & CH3LTSTHR & reg\_ch3ltsthr & CH3LTSTHR\\
+0x80& REG & CH4LTSCYR & reg\_ch4ltscyr & CH4LTSCYR\\
+0x84& REG & CH4LTSTLR & reg\_ch4ltstlr & CH4LTSTLR\\
+0x88& REG & CH4LTSTHR & reg\_ch4ltsthr & CH4LTSTHR\\
+0x8c& REG & CH5LTSCYR & reg\_ch5ltscyr & CH5LTSCYR\\
+0x90& REG & CH5LTSTLR & reg\_ch5ltstlr & CH5LTSTLR\\
+0x94& REG & CH5LTSTHR & reg\_ch5ltsthr & CH5LTSTHR\\
+0x98& REG & CH6LTSCYR & reg\_ch6ltscyr & CH6LTSCYR\\
+0x9c& REG & CH6LTSTLR & reg\_ch6ltstlr & CH6LTSTLR\\
+0xa0& REG & CH6LTSTHR & reg\_ch6ltsthr & CH6LTSTHR\\
+0xa4& REG & LSR & reg\_lsr & LSR\\
+0xa8& REG & OSWR & reg\_oswr & OSWR\\
+0xac& REG & UIDLR & reg\_uidlr & UIDLR\\
+0xb0& REG & UIDHR & reg\_uidhr & UIDHR\\
+0xb4& REG & TEMPR & reg\_tempr & TEMPR\\
+\hline
+\end{tabular}
+}
+\subsubsection{Register description}
+\paragraph*{BIDR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_bidr\\
+{\bf HW address:}  & 0x0\\
+{\bf SW prefix:}  & BIDR\\
+{\bf SW offset:}  & 0x0\\
+\end{tabular}
+\vspace{12pt}
+Board ID Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+BIDR
+} [\emph{read-only}]: ID register bits
+\end{small}
+\end{itemize}
+\paragraph*{SR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_sr\\
+{\bf HW address:}  & 0x1\\
+{\bf SW prefix:}  & SR\\
+{\bf SW offset:}  & 0x4\\
+\end{tabular}
+\vspace{12pt}
+Status Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRPRES} & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:2]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCHES[7:0]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}GWVERS[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+GWVERS
+} [\emph{read-only}]: Gateware version
+\\
+Leftmost nibble hex value is major release decimal value \\                     Rightmost nibble hex value is minor release decimal value \\		     e.g. \\		     0x11 -- v1.1 \\		     0x2e -- v2.14
+\end{small}
+\item \begin{small}
+{\bf 
+SWITCHES
+} [\emph{read-only}]: Status of on-board general-purpose switches
+\\
+Eg: SW1.1-- SR.SWITCHES[0] \\                     SW1.2-- SR.SWITCHES[1] \\                     SW2.1-- SR.SWITCHES[4] \\                     SW2.4-- SR.SWITCHES[7] \\                     1 -- switch is ON \\                     0 -- switch is OFF
+\end{small}
+\item \begin{small}
+{\bf 
+RTM
+} [\emph{read-only}]: RTM detection lines cite{rtm-det}
+\\
+1 bit per RTM output channel \\					 1 -- line active \\                     0 -- line inactive
+\end{small}
+\item \begin{small}
+{\bf 
+HWVERS
+} [\emph{read-only}]: Hardware version
+\\
+PCB version - Hardwired on the board \\					 Only meaningful for HW v4.0 and over \\					 Earlier versions show 0. The register \\					 uses 4 bits for the version number and\\					 2 bits for the execution.\\		     e.g. \\		     0x010001 -- hw v4.1 \\		     0x010111 -- hw v5.3 \\			 0x00-- hw v3 and earlier
+\end{small}
+\item \begin{small}
+{\bf 
+WRPRES
+} [\emph{read-only}]: White Rabbit present
+\\
+1 -- White Rabbit present \\                     0 -- White Rabbit not present
+\end{small}
+\end{itemize}
+\paragraph*{ERR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_err\\
+{\bf HW address:}  & 0x2\\
+{\bf SW prefix:}  & ERR\\
+{\bf SW offset:}  & 0x8\\
+\end{tabular}
+\vspace{12pt}
+Error Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FWDG\_PMISSE[5:0]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FLIM\_PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+I2C\_WDTO
+} [\emph{read/write}]: I2C communication watchdog timeout error
+\\
+1 -- timeout occured \\                     0 -- no timeout \\                     This bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf 
+I2C\_ERR
+} [\emph{read/write}]: I2C communication error
+\\
+1 -- attempted to address non-existing address \\                     0 -- idle \\                     This bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf 
+FLIM\_PMISSE
+} [\emph{read/write}]: Frequency error
+\\
+1 -- Input above maximum supported frequency \\                     0 -- idle \\                     Bit 0 -- channel 1 \\                     Bit 1 -- channel 2 \\                     etc. \\                     Each bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf 
+FWDG\_PMISSE
+} [\emph{read/write}]: Frequency watchdog error
+\\
+1 -- Pulse over maximum pulse count for given frequency'  \\                     0 -- idle \\                     Bit 0 -- channel 1 \\                     Bit 1 -- channel 2 \\                     etc. \\                     Each bit can be cleared by writing a '1' to it
+\end{small}
+\end{itemize}
+\paragraph*{CR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_cr\\
+{\bf HW address:}  & 0x3\\
+{\bf SW prefix:}  & CR\\
+{\bf SW offset:}  & 0xc\\
+\end{tabular}
+\vspace{12pt}
+Control Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}MPT[7:6]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+RST\_UNLOCK
+} [\emph{read/write}]: Reset unlock bit
+\\
+1 -- Reset bit unlocked \\                     0 -- Reset bit locked
+\end{small}
+\item \begin{small}
+{\bf 
+RST
+} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
+\\
+1 -- initiate logic reset \\                     0 -- no reset
+\end{small}
+\item \begin{small}
+{\bf 
+MPT
+} [\emph{write-only}]: Manual Pulse Trigger
+\\
+Write the following sequence to trigger a pulse: \\                     0xde -- Byte 1 of magic sequence \\                     0xad -- Byte 2 of magic sequence \\                     0xbe -- Byte 3 of magic sequence \\                     0xef -- Byte 4 of magic sequence \\		     Number in range 1..6 -- trigger a pulse
+\end{small}
+\end{itemize}
+\paragraph*{CH1TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch1ttlpcr\\
+{\bf HW address:}  & 0x4\\
+{\bf SW prefix:}  & CH1TTLPCR\\
+{\bf SW offset:}  & 0x10\\
+\end{tabular}
+\vspace{12pt}
+Channel 1 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH1TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH2TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch2ttlpcr\\
+{\bf HW address:}  & 0x5\\
+{\bf SW prefix:}  & CH2TTLPCR\\
+{\bf SW offset:}  & 0x14\\
+\end{tabular}
+\vspace{12pt}
+Channel 2 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH2TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH3TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch3ttlpcr\\
+{\bf HW address:}  & 0x6\\
+{\bf SW prefix:}  & CH3TTLPCR\\
+{\bf SW offset:}  & 0x18\\
+\end{tabular}
+\vspace{12pt}
+Channel 3 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH3TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH4TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch4ttlpcr\\
+{\bf HW address:}  & 0x7\\
+{\bf SW prefix:}  & CH4TTLPCR\\
+{\bf SW offset:}  & 0x1c\\
+\end{tabular}
+\vspace{12pt}
+Channel 4 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH4TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH5TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch5ttlpcr\\
+{\bf HW address:}  & 0x8\\
+{\bf SW prefix:}  & CH5TTLPCR\\
+{\bf SW offset:}  & 0x20\\
+\end{tabular}
+\vspace{12pt}
+Channel 5 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH5TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH6TTLPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch6ttlpcr\\
+{\bf HW address:}  & 0x9\\
+{\bf SW prefix:}  & CH6TTLPCR\\
+{\bf SW offset:}  & 0x24\\
+\end{tabular}
+\vspace{12pt}
+Channel 6 Pulse Counter Register for TTL pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH6TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH1BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch1blopcr\\
+{\bf HW address:}  & 0xa\\
+{\bf SW prefix:}  & CH1BLOPCR\\
+{\bf SW offset:}  & 0x28\\
+\end{tabular}
+\vspace{12pt}
+Channel 1 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH1BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH2BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch2blopcr\\
+{\bf HW address:}  & 0xb\\
+{\bf SW prefix:}  & CH2BLOPCR\\
+{\bf SW offset:}  & 0x2c\\
+\end{tabular}
+\vspace{12pt}
+Channel 2 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH2BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH3BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch3blopcr\\
+{\bf HW address:}  & 0xc\\
+{\bf SW prefix:}  & CH3BLOPCR\\
+{\bf SW offset:}  & 0x30\\
+\end{tabular}
+\vspace{12pt}
+Channel 3 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH3BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH4BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch4blopcr\\
+{\bf HW address:}  & 0xd\\
+{\bf SW prefix:}  & CH4BLOPCR\\
+{\bf SW offset:}  & 0x34\\
+\end{tabular}
+\vspace{12pt}
+Channel 4 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH4BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH5BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch5blopcr\\
+{\bf HW address:}  & 0xe\\
+{\bf SW prefix:}  & CH5BLOPCR\\
+{\bf SW offset:}  & 0x38\\
+\end{tabular}
+\vspace{12pt}
+Channel 5 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH5BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{CH6BLOPCR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch6blopcr\\
+{\bf HW address:}  & 0xf\\
+{\bf SW prefix:}  & CH6BLOPCR\\
+{\bf SW offset:}  & 0x3c\\
+\end{tabular}
+\vspace{12pt}
+Channel 6 Pulse Counter Register for BLO pulses
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH6BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\paragraph*{TVLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tvlr\\
+{\bf HW address:}  & 0x10\\
+{\bf SW prefix:}  & TVLR\\
+{\bf SW offset:}  & 0x40\\
+\end{tabular}
+\vspace{12pt}
+Time Value Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TVLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TVLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TVLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TVLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TVLR
+} [\emph{read/write}]: TAI seconds counter bits 31..0
+\\
+Writing this field resets the internal cycles counter.
+\end{small}
+\end{itemize}
+\paragraph*{TVHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tvhr\\
+{\bf HW address:}  & 0x11\\
+{\bf SW prefix:}  & TVHR\\
+{\bf SW offset:}  & 0x44\\
+\end{tabular}
+\vspace{12pt}
+Time Value High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TVHR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TVHR
+} [\emph{read/write}]: TAI seconds counter bits 39..32
+\\
+Writing this field resets the internal cycles counter.
+\end{small}
+\end{itemize}
+\paragraph*{TBMR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tbmr\\
+{\bf HW address:}  & 0x12\\
+{\bf SW prefix:}  & TBMR\\
+{\bf SW offset:}  & 0x48\\
+\end{tabular}
+\vspace{12pt}
+Tag Buffer Meta Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}CHAN[5:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CHAN
+} [\emph{read-only}]: Channel mask
+\\
+Mask for the channel(s) that triggered time-tag storage: \\                     bit 0 -- channel 1 \\		     bit 1 -- channel 2 \\		     ... \\		     bit 5 -- channel 6
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{TBCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tbcyr\\
+{\bf HW address:}  & 0x13\\
+{\bf SW prefix:}  & TBCYR\\
+{\bf SW offset:}  & 0x4c\\
+\end{tabular}
+\vspace{12pt}
+Tag Buffer Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}TBCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TBCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{TBTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tbtlr\\
+{\bf HW address:}  & 0x14\\
+{\bf SW prefix:}  & TBTLR\\
+{\bf SW offset:}  & 0x50\\
+\end{tabular}
+\vspace{12pt}
+Tag Buffer TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TBTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{TBTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tbthr\\
+{\bf HW address:}  & 0x15\\
+{\bf SW prefix:}  & TBTHR\\
+{\bf SW offset:}  & 0x54\\
+\end{tabular}
+\vspace{12pt}
+Tag Buffer TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TBTHR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TBTHR
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{TBCSR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tbcsr\\
+{\bf HW address:}  & 0x16\\
+{\bf SW prefix:}  & TBCSR\\
+{\bf SW offset:}  & 0x58\\
+\end{tabular}
+\vspace{12pt}
+Tag Buffer Control and Status Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}FULL}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{RoyalPurple!25}USEDW[6:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+USEDW
+} [\emph{read-only}]: Buffer counter
+\\
+Number of samples in the ring buffer
+\end{small}
+\item \begin{small}
+{\bf 
+FULL
+} [\emph{read-only}]: Buffer full
+\\
+1 -- buffer full \\      0 -- buffer is not full
+\end{small}
+\item \begin{small}
+{\bf 
+EMPTY
+} [\emph{read-only}]: Buffer empty
+\\
+1 -- buffer empty\\      0 -- buffer is not empty
+\end{small}
+\item \begin{small}
+{\bf 
+CLR
+} [\emph{read/write}]: Clear tag buffer
+\\
+1 -- clear\\      0 -- no effect
+\end{small}
+\end{itemize}
+\paragraph*{CH1LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch1ltscyr\\
+{\bf HW address:}  & 0x17\\
+{\bf SW prefix:}  & CH1LTSCYR\\
+{\bf SW offset:}  & 0x5c\\
+\end{tabular}
+\vspace{12pt}
+Channel 1 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH1LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH1LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch1ltstlr\\
+{\bf HW address:}  & 0x18\\
+{\bf SW prefix:}  & CH1LTSTLR\\
+{\bf SW offset:}  & 0x60\\
+\end{tabular}
+\vspace{12pt}
+Channel 1 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH1LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH1LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch1ltsthr\\
+{\bf HW address:}  & 0x19\\
+{\bf SW prefix:}  & CH1LTSTHR\\
+{\bf SW offset:}  & 0x64\\
+\end{tabular}
+\vspace{12pt}
+Channel 1 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{CH2LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch2ltscyr\\
+{\bf HW address:}  & 0x1a\\
+{\bf SW prefix:}  & CH2LTSCYR\\
+{\bf SW offset:}  & 0x68\\
+\end{tabular}
+\vspace{12pt}
+Channel 2 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH2LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH2LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch2ltstlr\\
+{\bf HW address:}  & 0x1b\\
+{\bf SW prefix:}  & CH2LTSTLR\\
+{\bf SW offset:}  & 0x6c\\
+\end{tabular}
+\vspace{12pt}
+Channel 2 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH2LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH2LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch2ltsthr\\
+{\bf HW address:}  & 0x1c\\
+{\bf SW prefix:}  & CH2LTSTHR\\
+{\bf SW offset:}  & 0x70\\
+\end{tabular}
+\vspace{12pt}
+Channel 2 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{CH3LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch3ltscyr\\
+{\bf HW address:}  & 0x1d\\
+{\bf SW prefix:}  & CH3LTSCYR\\
+{\bf SW offset:}  & 0x74\\
+\end{tabular}
+\vspace{12pt}
+Channel 3 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH3LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH3LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch3ltstlr\\
+{\bf HW address:}  & 0x1e\\
+{\bf SW prefix:}  & CH3LTSTLR\\
+{\bf SW offset:}  & 0x78\\
+\end{tabular}
+\vspace{12pt}
+Channel 3 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH3LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH3LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch3ltsthr\\
+{\bf HW address:}  & 0x1f\\
+{\bf SW prefix:}  & CH3LTSTHR\\
+{\bf SW offset:}  & 0x7c\\
+\end{tabular}
+\vspace{12pt}
+Channel 3 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{CH4LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch4ltscyr\\
+{\bf HW address:}  & 0x20\\
+{\bf SW prefix:}  & CH4LTSCYR\\
+{\bf SW offset:}  & 0x80\\
+\end{tabular}
+\vspace{12pt}
+Channel 4 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH4LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH4LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch4ltstlr\\
+{\bf HW address:}  & 0x21\\
+{\bf SW prefix:}  & CH4LTSTLR\\
+{\bf SW offset:}  & 0x84\\
+\end{tabular}
+\vspace{12pt}
+Channel 4 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH4LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH4LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch4ltsthr\\
+{\bf HW address:}  & 0x22\\
+{\bf SW prefix:}  & CH4LTSTHR\\
+{\bf SW offset:}  & 0x88\\
+\end{tabular}
+\vspace{12pt}
+Channel 4 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{CH5LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch5ltscyr\\
+{\bf HW address:}  & 0x23\\
+{\bf SW prefix:}  & CH5LTSCYR\\
+{\bf SW offset:}  & 0x8c\\
+\end{tabular}
+\vspace{12pt}
+Channel 5 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH5LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH5LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch5ltstlr\\
+{\bf HW address:}  & 0x24\\
+{\bf SW prefix:}  & CH5LTSTLR\\
+{\bf SW offset:}  & 0x90\\
+\end{tabular}
+\vspace{12pt}
+Channel 5 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH5LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH5LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch5ltsthr\\
+{\bf HW address:}  & 0x25\\
+{\bf SW prefix:}  & CH5LTSTHR\\
+{\bf SW offset:}  & 0x94\\
+\end{tabular}
+\vspace{12pt}
+Channel 5 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{CH6LTSCYR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch6ltscyr\\
+{\bf HW address:}  & 0x26\\
+{\bf SW prefix:}  & CH6LTSCYR\\
+{\bf SW offset:}  & 0x98\\
+\end{tabular}
+\vspace{12pt}
+Channel 6 Latest Timestamp Cycles Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH6LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH6LTSTLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch6ltstlr\\
+{\bf HW address:}  & 0x27\\
+{\bf SW prefix:}  & CH6LTSTLR\\
+{\bf SW offset:}  & 0x9c\\
+\end{tabular}
+\vspace{12pt}
+Channel 6 Latest Timestamp TAI Low Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+CH6LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\paragraph*{CH6LTSTHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_ch6ltsthr\\
+{\bf HW address:}  & 0x28\\
+{\bf SW prefix:}  & CH6LTSTHR\\
+{\bf SW offset:}  & 0xa0\\
+\end{tabular}
+\vspace{12pt}
+Channel 6 Latest Timestamp TAI High Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf 
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\                     0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\paragraph*{LSR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_lsr\\
+{\bf HW address:}  & 0x29\\
+{\bf SW prefix:}  & LSR\\
+{\bf SW offset:}  & 0xa4\\
+\end{tabular}
+\vspace{12pt}
+Line Status Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINVFS[3:2]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONTFS[5:0]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+FRONT
+} [\emph{read-only}]: Front panel channel input state
+\\
+Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+FRONTINV
+} [\emph{read-only}]: Front panel INV-TTL input state
+\\
+Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+REAR
+} [\emph{read-only}]: Rear panel input state
+\\
+Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+FRONTFS
+} [\emph{read-only}]: Front panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+FRONTINVFS
+} [\emph{read-only}]: Front panel inverter input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+REARFS
+} [\emph{read-only}]: Rear panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\end{itemize}
+\paragraph*{OSWR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_oswr\\
+{\bf HW address:}  & 0x2a\\
+{\bf SW prefix:}  & OSWR\\
+{\bf SW offset:}  & 0xa8\\
+\end{tabular}
+\vspace{12pt}
+Other Switch Register
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCHES[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCHES[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCHES[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCHES[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+SWITCHES
+} [\emph{read-only}]: Switch state
+\\
+1 -- switch is ON \\      0 -- switch is OFF
+\end{small}
+\end{itemize}
+\paragraph*{UIDLR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_uidlr\\
+{\bf HW address:}  & 0x2b\\
+{\bf SW prefix:}  & UIDLR\\
+{\bf SW offset:}  & 0xac\\
+\end{tabular}
+\vspace{12pt}
+32 LS bits of 1-wire thermometer ID
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDLR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+UIDLR
+} [\emph{read-only}]: LS bits of 1-wire DS18B20U thermometer ID
+\end{small}
+\end{itemize}
+\paragraph*{UIDHR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_uidhr\\
+{\bf HW address:}  & 0x2c\\
+{\bf SW prefix:}  & UIDHR\\
+{\bf SW offset:}  & 0xb0\\
+\end{tabular}
+\vspace{12pt}
+32 MS bits of 1-wire thermometer ID
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDHR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDHR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDHR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}UIDHR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+UIDHR
+} [\emph{read-only}]: MS bits of 1-wire DS18B20U thermometer ID
+\end{small}
+\end{itemize}
+\paragraph*{TEMPR}\vspace{12pt}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & reg\_tempr\\
+{\bf HW address:}  & 0x2d\\
+{\bf SW prefix:}  & TEMPR\\
+{\bf SW offset:}  & 0xb4\\
+\end{tabular}
+\vspace{12pt}
+Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0
+\vspace{12pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TEMPR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TEMPR[7:0]}\\
+\hline
+\end{tabular}
+}
+\begin{itemize}
+\item \begin{small}
+{\bf 
+TEMPR
+} [\emph{read-only}]: TEMP
+\\
+Current on-board temperature
+\end{small}
+\end{itemize}
--- a/modules/conv_regs.vhd
+++ b/modules/conv_regs.vhd
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for Converter board registers
 ---------------------------------------------------------------------------------------
-- File           : conv_regs.vhd
+-- File           : .\conv_regs.vhd
 -- Author         : auto-generated by wbgen2 from conv_regs.wb
-- Created        : Mon Aug 18 15:56:43 2014
+-- Created        : 02/06/17 15:05:15
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
@@ -33,57 +33,87 @@ entity conv_regs is
    reg_sr_gwvers_i                          : in     std_logic_vector(7 downto 0);
 -- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
    reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
+-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
    reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
+-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
-    reg_sr_i2c_wdto_o                        : out    std_logic;
+    reg_sr_hwvers_i                          : in     std_logic_vector(5 downto 0);
-    reg_sr_i2c_wdto_i                        : in     std_logic;
-    reg_sr_i2c_wdto_load_o                   : out    std_logic;
 -- Port for BIT field: 'White Rabbit present' in reg: 'SR'
    reg_sr_wrpres_i                          : in     std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
+-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
-    reg_sr_i2c_err_o                         : out    std_logic;
+    reg_err_i2c_wdto_o                       : out    std_logic;
-    reg_sr_i2c_err_i                         : in     std_logic;
+    reg_err_i2c_wdto_i                       : in     std_logic;
-    reg_sr_i2c_err_load_o                    : out    std_logic;
+    reg_err_i2c_wdto_load_o                  : out    std_logic;
-- Port for std_logic_vector field: 'Pulse missed error' in reg: 'SR'
+-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
-    reg_sr_pmisse_o                          : out    std_logic_vector(5 downto 0);
+    reg_err_i2c_err_o                        : out    std_logic;
-    reg_sr_pmisse_i                          : in     std_logic_vector(5 downto 0);
+    reg_err_i2c_err_i                        : in     std_logic;
-    reg_sr_pmisse_load_o                     : out    std_logic;
+    reg_err_i2c_err_load_o                   : out    std_logic;
+-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
+    reg_err_flim_pmisse_o                    : out    std_logic_vector(5 downto 0);
+    reg_err_flim_pmisse_i                    : in     std_logic_vector(5 downto 0);
+    reg_err_flim_pmisse_load_o               : out    std_logic;
+-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
+    reg_err_fwdg_pmisse_o                    : out    std_logic_vector(5 downto 0);
+    reg_err_fwdg_pmisse_i                    : in     std_logic_vector(5 downto 0);
+    reg_err_fwdg_pmisse_load_o               : out    std_logic;
 -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
    reg_cr_rst_unlock_o                      : out    std_logic;
    reg_cr_rst_unlock_i                      : in     std_logic;
    reg_cr_rst_unlock_load_o                 : out    std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
+-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
    reg_cr_rst_o                             : out    std_logic;
    reg_cr_rst_i                             : in     std_logic;
    reg_cr_rst_load_o                        : out    std_logic;
 -- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
    reg_cr_mpt_o                             : out    std_logic_vector(7 downto 0);
    reg_cr_mpt_wr_o                          : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH1TTLPCR'
-    reg_ch1pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch1ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch1pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch1ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch1pcr_load_o                        : out    std_logic;
+    reg_ch1ttlpcr_load_o                     : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH2TTLPCR'
-    reg_ch2pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch2ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch2pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch2ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch2pcr_load_o                        : out    std_logic;
+    reg_ch2ttlpcr_load_o                     : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH3TTLPCR'
-    reg_ch3pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch3ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch3pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch3ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch3pcr_load_o                        : out    std_logic;
+    reg_ch3ttlpcr_load_o                     : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH4TTLPCR'
-    reg_ch4pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch4ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch4pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch4ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch4pcr_load_o                        : out    std_logic;
+    reg_ch4ttlpcr_load_o                     : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH5TTLPCR'
-    reg_ch5pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch5ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch5pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch5ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch5pcr_load_o                        : out    std_logic;
+    reg_ch5ttlpcr_load_o                     : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR'
-    reg_ch6pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch6ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-    reg_ch6pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch6ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-    reg_ch6pcr_load_o                        : out    std_logic;
+    reg_ch6ttlpcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR'
+    reg_ch1blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch1blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch1blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH2BLOPCR'
+    reg_ch2blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch2blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch2blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH3BLOPCR'
+    reg_ch3blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch3blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch3blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH4BLOPCR'
+    reg_ch4blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch4blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch4blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH5BLOPCR'
+    reg_ch5blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch5blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch5blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH6BLOPCR'
+    reg_ch6blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch6blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch6blopcr_load_o                     : out    std_logic;
 -- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
    reg_tvlr_o                               : out    std_logic_vector(31 downto 0);
    reg_tvlr_i                               : in     std_logic_vector(31 downto 0);
@@ -94,6 +124,7 @@ entity conv_regs is
    reg_tvhr_load_o                          : out    std_logic;
 -- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
    reg_tbmr_chan_i                          : in     std_logic_vector(5 downto 0);
+    reg_tb_rd_req_p_o                        : out    std_logic;
 -- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
    reg_tbmr_wrtag_i                         : in     std_logic;
 -- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
@@ -112,8 +143,6 @@ entity conv_regs is
    reg_tbcsr_clr_o                          : out    std_logic;
    reg_tbcsr_clr_i                          : in     std_logic;
    reg_tbcsr_clr_load_o                     : out    std_logic;
-- Tag buffer read request, asserted when reading from TBMR
-    reg_tb_rd_req_p_o                        : out    std_logic;
 -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
    reg_ch1ltscyr_i                          : in     std_logic_vector(27 downto 0);
 -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
@@ -168,14 +197,20 @@ entity conv_regs is
    reg_lsr_frontinv_i                       : in     std_logic_vector(3 downto 0);
 -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
    reg_lsr_rear_i                           : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
    reg_lsr_frontfs_i                        : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
    reg_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
    reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
+-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
-    reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0)
+    reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
+    reg_uidlr_i                              : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
+    reg_uidhr_i                              : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
+    reg_tempr_i                              : in     std_logic_vector(15 downto 0)
  );
 end conv_regs;
@@ -208,62 +243,82 @@ begin
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
-      reg_sr_i2c_wdto_load_o <= '0';
+      reg_err_i2c_wdto_load_o <= '0';
-      reg_sr_i2c_err_load_o <= '0';
+      reg_err_i2c_err_load_o <= '0';
-      reg_sr_pmisse_load_o <= '0';
+      reg_err_flim_pmisse_load_o <= '0';
+      reg_err_fwdg_pmisse_load_o <= '0';
      reg_cr_rst_unlock_load_o <= '0';
      reg_cr_rst_load_o <= '0';
      reg_cr_mpt_wr_o <= '0';
-      reg_ch1pcr_load_o <= '0';
+      reg_ch1ttlpcr_load_o <= '0';
-      reg_ch2pcr_load_o <= '0';
+      reg_ch2ttlpcr_load_o <= '0';
-      reg_ch3pcr_load_o <= '0';
+      reg_ch3ttlpcr_load_o <= '0';
-      reg_ch4pcr_load_o <= '0';
+      reg_ch4ttlpcr_load_o <= '0';
-      reg_ch5pcr_load_o <= '0';
+      reg_ch5ttlpcr_load_o <= '0';
-      reg_ch6pcr_load_o <= '0';
+      reg_ch6ttlpcr_load_o <= '0';
+      reg_ch1blopcr_load_o <= '0';
+      reg_ch2blopcr_load_o <= '0';
+      reg_ch3blopcr_load_o <= '0';
+      reg_ch4blopcr_load_o <= '0';
+      reg_ch5blopcr_load_o <= '0';
+      reg_ch6blopcr_load_o <= '0';
      reg_tvlr_load_o <= '0';
      reg_tvhr_load_o <= '0';
-      reg_tbcsr_clr_load_o <= '0';
      reg_tb_rd_req_p_o <= '0';
+      reg_tbcsr_clr_load_o <= '0';
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
-          reg_sr_i2c_wdto_load_o <= '0';
+          reg_err_i2c_wdto_load_o <= '0';
-          reg_sr_i2c_err_load_o <= '0';
+          reg_err_i2c_err_load_o <= '0';
-          reg_sr_pmisse_load_o <= '0';
+          reg_err_flim_pmisse_load_o <= '0';
+          reg_err_fwdg_pmisse_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
          reg_cr_mpt_wr_o <= '0';
-          reg_ch1pcr_load_o <= '0';
+          reg_ch1ttlpcr_load_o <= '0';
-          reg_ch2pcr_load_o <= '0';
+          reg_ch2ttlpcr_load_o <= '0';
-          reg_ch3pcr_load_o <= '0';
+          reg_ch3ttlpcr_load_o <= '0';
-          reg_ch4pcr_load_o <= '0';
+          reg_ch4ttlpcr_load_o <= '0';
-          reg_ch5pcr_load_o <= '0';
+          reg_ch5ttlpcr_load_o <= '0';
-          reg_ch6pcr_load_o <= '0';
+          reg_ch6ttlpcr_load_o <= '0';
+          reg_ch1blopcr_load_o <= '0';
+          reg_ch2blopcr_load_o <= '0';
+          reg_ch3blopcr_load_o <= '0';
+          reg_ch4blopcr_load_o <= '0';
+          reg_ch5blopcr_load_o <= '0';
+          reg_ch6blopcr_load_o <= '0';
          reg_tvlr_load_o <= '0';
          reg_tvhr_load_o <= '0';
-          reg_tbcsr_clr_load_o <= '0';
          reg_tb_rd_req_p_o <= '0';
+          reg_tbcsr_clr_load_o <= '0';
          ack_in_progress <= '0';
        else
-          reg_sr_i2c_wdto_load_o <= '0';
+          reg_err_i2c_wdto_load_o <= '0';
-          reg_sr_i2c_err_load_o <= '0';
+          reg_err_i2c_err_load_o <= '0';
-          reg_sr_pmisse_load_o <= '0';
+          reg_err_flim_pmisse_load_o <= '0';
+          reg_err_fwdg_pmisse_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
          reg_cr_mpt_wr_o <= '0';
-          reg_ch1pcr_load_o <= '0';
+          reg_ch1ttlpcr_load_o <= '0';
-          reg_ch2pcr_load_o <= '0';
+          reg_ch2ttlpcr_load_o <= '0';
-          reg_ch3pcr_load_o <= '0';
+          reg_ch3ttlpcr_load_o <= '0';
-          reg_ch4pcr_load_o <= '0';
+          reg_ch4ttlpcr_load_o <= '0';
-          reg_ch5pcr_load_o <= '0';
+          reg_ch5ttlpcr_load_o <= '0';
-          reg_ch6pcr_load_o <= '0';
+          reg_ch6ttlpcr_load_o <= '0';
+          reg_ch1blopcr_load_o <= '0';
+          reg_ch2blopcr_load_o <= '0';
+          reg_ch3blopcr_load_o <= '0';
+          reg_ch4blopcr_load_o <= '0';
+          reg_ch5blopcr_load_o <= '0';
+          reg_ch6blopcr_load_o <= '0';
          reg_tvlr_load_o <= '0';
          reg_tvhr_load_o <= '0';
          reg_tbcsr_clr_load_o <= '0';
-          reg_tb_rd_req_p_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
@@ -276,21 +331,49 @@ begin
            ack_in_progress <= '1';
          when "000001" => 
            if (wb_we_i = '1') then
-              reg_sr_i2c_wdto_load_o <= '1';
-              reg_sr_i2c_err_load_o <= '1';
-              reg_sr_pmisse_load_o <= '1';
            end if;
            rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
            rddata_reg(15 downto 8) <= reg_sr_switches_i;
            rddata_reg(21 downto 16) <= reg_sr_rtm_i;
-            rddata_reg(22) <= reg_sr_i2c_wdto_i;
+            rddata_reg(27 downto 22) <= reg_sr_hwvers_i;
-            rddata_reg(23) <= reg_sr_wrpres_i;
+            rddata_reg(28) <= reg_sr_wrpres_i;
-            rddata_reg(24) <= reg_sr_i2c_err_i;
+            rddata_reg(29) <= 'X';
-            rddata_reg(30 downto 25) <= reg_sr_pmisse_i;
+            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000010" => 
+            if (wb_we_i = '1') then
+              reg_err_i2c_wdto_load_o <= '1';
+              reg_err_i2c_err_load_o <= '1';
+              reg_err_flim_pmisse_load_o <= '1';
+              reg_err_fwdg_pmisse_load_o <= '1';
+            end if;
+            rddata_reg(0) <= reg_err_i2c_wdto_i;
+            rddata_reg(1) <= reg_err_i2c_err_i;
+            rddata_reg(7 downto 2) <= reg_err_flim_pmisse_i;
+            rddata_reg(13 downto 8) <= reg_err_fwdg_pmisse_i;
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "000011" => 
            if (wb_we_i = '1') then
              reg_cr_rst_unlock_load_o <= '1';
              reg_cr_rst_load_o <= '1';
@@ -330,56 +413,98 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "000011" => 
-            if (wb_we_i = '1') then
-              reg_ch1pcr_load_o <= '1';
-            end if;
-            rddata_reg(31 downto 0) <= reg_ch1pcr_i;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
          when "000100" => 
            if (wb_we_i = '1') then
-              reg_ch2pcr_load_o <= '1';
+              reg_ch1ttlpcr_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= reg_ch2pcr_i;
+            rddata_reg(31 downto 0) <= reg_ch1ttlpcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000101" => 
            if (wb_we_i = '1') then
-              reg_ch3pcr_load_o <= '1';
+              reg_ch2ttlpcr_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= reg_ch3pcr_i;
+            rddata_reg(31 downto 0) <= reg_ch2ttlpcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000110" => 
            if (wb_we_i = '1') then
-              reg_ch4pcr_load_o <= '1';
+              reg_ch3ttlpcr_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= reg_ch4pcr_i;
+            rddata_reg(31 downto 0) <= reg_ch3ttlpcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000111" => 
            if (wb_we_i = '1') then
-              reg_ch5pcr_load_o <= '1';
+              reg_ch4ttlpcr_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= reg_ch5pcr_i;
+            rddata_reg(31 downto 0) <= reg_ch4ttlpcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001000" => 
            if (wb_we_i = '1') then
-              reg_ch6pcr_load_o <= '1';
+              reg_ch5ttlpcr_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= reg_ch6pcr_i;
+            rddata_reg(31 downto 0) <= reg_ch5ttlpcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001001" => 
+            if (wb_we_i = '1') then
+              reg_ch6ttlpcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch6ttlpcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001010" => 
+            if (wb_we_i = '1') then
+              reg_ch1blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch1blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001011" => 
+            if (wb_we_i = '1') then
+              reg_ch2blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch2blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001100" => 
+            if (wb_we_i = '1') then
+              reg_ch3blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch3blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001101" => 
+            if (wb_we_i = '1') then
+              reg_ch4blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch4blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001110" => 
+            if (wb_we_i = '1') then
+              reg_ch5blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch5blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "001111" => 
+            if (wb_we_i = '1') then
+              reg_ch6blopcr_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= reg_ch6blopcr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "010000" => 
            if (wb_we_i = '1') then
              reg_tvlr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_tvlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001010" => 
+          when "010001" => 
            if (wb_we_i = '1') then
              reg_tvhr_load_o <= '1';
            end if;
@@ -410,11 +535,11 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001011" => 
+          when "010010" => 
            if (wb_we_i = '1') then
            end if;
-            reg_tb_rd_req_p_o <= '1';
            rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
+            reg_tb_rd_req_p_o <= '1';
            rddata_reg(31) <= reg_tbmr_wrtag_i;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
@@ -443,7 +568,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001100" => 
+          when "010011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_tbcyr_i;
@@ -453,13 +578,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001101" => 
+          when "010100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_tbtlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001110" => 
+          when "010101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_tbthr_i;
@@ -489,7 +614,7 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "001111" => 
+          when "010110" => 
            if (wb_we_i = '1') then
              reg_tbcsr_clr_load_o <= '1';
            end if;
@@ -521,7 +646,7 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010000" => 
+          when "010111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch1ltscyr_i;
@@ -531,13 +656,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010001" => 
+          when "011000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch1ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010010" => 
+          when "011001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch1ltsthr_tai_i;
@@ -567,7 +692,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010011" => 
+          when "011010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch2ltscyr_i;
@@ -577,13 +702,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010100" => 
+          when "011011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch2ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010101" => 
+          when "011100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch2ltsthr_tai_i;
@@ -613,7 +738,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010110" => 
+          when "011101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch3ltscyr_i;
@@ -623,13 +748,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "010111" => 
+          when "011110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch3ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011000" => 
+          when "011111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch3ltsthr_tai_i;
@@ -659,7 +784,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011001" => 
+          when "100000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch4ltscyr_i;
@@ -669,13 +794,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011010" => 
+          when "100001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch4ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011011" => 
+          when "100010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch4ltsthr_tai_i;
@@ -705,7 +830,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011100" => 
+          when "100011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch5ltscyr_i;
@@ -715,13 +840,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011101" => 
+          when "100100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch5ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011110" => 
+          when "100101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch5ltsthr_tai_i;
@@ -751,7 +876,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "011111" => 
+          when "100110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_ch6ltscyr_i;
@@ -761,13 +886,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "100000" => 
+          when "100111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_ch6ltstlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "100001" => 
+          when "101000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_ch6ltsthr_tai_i;
@@ -797,7 +922,7 @@ begin
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "100010" => 
+          when "101001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(5 downto 0) <= reg_lsr_front_i;
@@ -808,12 +933,46 @@ begin
            rddata_reg(31 downto 26) <= reg_lsr_rearfs_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "100011" => 
+          when "101010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_oswr_switches_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
+          when "101011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= reg_uidlr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101100" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= reg_uidhr_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101101" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= reg_tempr_i;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
          when others =>
 -- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
@@ -830,33 +989,48 @@ begin
 -- ID register bits
 -- Gateware version
 -- Status of on-board general-purpose switches
-- RTM detection lines~\cite{rtm-det}
+-- RTM detection lines cite{rtm-det}
-- I2C communication watchdog timeout error
+-- Hardware version
-  reg_sr_i2c_wdto_o <= wrdata_reg(22);
 -- White Rabbit present
+-- I2C communication watchdog timeout error
+  reg_err_i2c_wdto_o <= wrdata_reg(0);
 -- I2C communication error
-  reg_sr_i2c_err_o <= wrdata_reg(24);
+  reg_err_i2c_err_o <= wrdata_reg(1);
-- Pulse missed error
+-- Frequency error
-  reg_sr_pmisse_o <= wrdata_reg(30 downto 25);
+  reg_err_flim_pmisse_o <= wrdata_reg(7 downto 2);
+-- Frequency watchdog error
+  reg_err_fwdg_pmisse_o <= wrdata_reg(13 downto 8);
 -- Reset unlock bit
  reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
+-- Reset bit - active only if RST_UNLOCK is 1
  reg_cr_rst_o <= wrdata_reg(1);
 -- Manual Pulse Trigger
 -- pass-through field: Manual Pulse Trigger in register: CR
  reg_cr_mpt_o <= wrdata_reg(9 downto 2);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch1pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch1ttlpcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch2pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch2ttlpcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch3pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch3ttlpcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch4pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch4ttlpcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch5pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch5ttlpcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
+-- TTL pulse counter value
-  reg_ch6pcr_o <= wrdata_reg(31 downto 0);
+  reg_ch6ttlpcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch1blopcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch2blopcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch3blopcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch4blopcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch5blopcr_o <= wrdata_reg(31 downto 0);
+-- BLO pulse counter value
+  reg_ch6blopcr_o <= wrdata_reg(31 downto 0);
 -- TAI seconds counter bits 31..0
  reg_tvlr_o <= wrdata_reg(31 downto 0);
 -- TAI seconds counter bits 39..32
@@ -898,8 +1072,13 @@ begin
 -- Front panel channel input state
 -- Front panel INV-TTL input state
 -- Rear panel input state
-- Input failsafe state
+-- Front panel input failsafe state
-- Multicast address (from switch)
+-- Front panel inverter input failsafe state
+-- Rear panel input failsafe state
+-- Switch state
+-- LS bits of 1-wire DS18B20U thermometer ID
+-- MS bits of 1-wire DS18B20U thermometer ID
+-- TEMP
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/modules/conv_regs.wb
+++ b/modules/conv_regs.wb
@@ -30,6 +30,11 @@
 -- last changes:
 --    03-05-2014   Theodor Stana     Added GPL header
 --    31-07-2014   Theodor Stana     Added MSWR & LSR registers
+--	  			   Denia Bouhired    Added separate pulse counters for TTL and BLO pulses
+--	  11-10-2016   Denia Bouhired    Added thermometer registers one 16 bit for temperature read out
+-- 									2 for LSBs and MSBs of 64-bit ID
+--	  20-12-2016   Denia Bouhired    Small modification to file in order to match that of wr-n-therm branch from 
+--										Theodor Stana
 --==============================================================================
 -- TODO: -
 --==============================================================================
@@ -77,7 +82,11 @@ peripheral {
    };
    field {
      name = "Status of on-board general-purpose switches";
-      description = "1 -- switch is ON \
+      description = "Eg: SW1.1-- SR.SWITCHES[0] \
+                     SW1.2-- SR.SWITCHES[1] \
+                     SW2.1-- SR.SWITCHES[4] \
+                     SW2.4-- SR.SWITCHES[7] \
+                     1 -- switch is ON \
                     0 -- switch is OFF";
      prefix = "switches";
      type = SLV;
@@ -86,8 +95,9 @@ peripheral {
      access_bus = READ_ONLY;
    };
    field {
-      name = "RTM detection lines~\\cite{rtm-det}";
+      name = "RTM detection lines \cite{rtm-det}";
-      description = "1 -- line active \
+      description = "1 bit per RTM output channel \
+					 1 -- line active \
                     0 -- line inactive";
      prefix = "rtm";
      type = SLV;
@@ -95,6 +105,39 @@ peripheral {
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
+    field {
+      name = "Hardware version";
+      description = "PCB version - Hardwired on the board \
+					 Only meaningful for HW v4.0 and over \
+					 Earlier versions show 0. The register \
+					 uses 4 bits for the version number and\
+					 2 bits for the execution.\
+		     e.g. \
+		     0x010001 -- hw v4.1 \
+		     0x010111 -- hw v5.3 \
+			 0x00-- hw v3 and earlier";
+      prefix = "hwvers";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "White Rabbit present";
+      description = "1 -- White Rabbit present \
+                     0 -- White Rabbit not present";
+      prefix = "wrpres";
+      type = BIT;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+  -- Error register
+  reg {
+    name = "ERR";
+    description = "Error Register";
+    prefix = "err";
    field {
      name = "I2C communication watchdog timeout error";
      description = "1 -- timeout occured \
@@ -107,15 +150,6 @@ peripheral {
      access_bus = READ_WRITE;
      load       = LOAD_EXT;
    };
-    field {
-      name = "White Rabbit present";
-      description = "1 -- White Rabbit present \
-                     0 -- White Rabbit not present";
-      prefix = "wrpres";
-      type = BIT;
-      access_dev = WRITE_ONLY;
-      access_bus = READ_ONLY;
-    };
    field {
      name = "I2C communication error";
      description = "1 -- attempted to address non-existing address \
@@ -128,14 +162,29 @@ peripheral {
      load = LOAD_EXT;
    };
    field {
-      name = "Pulse missed error";
+      name = "Frequency error";
-      description = "1 -- pulse arrived during pulse rejection phase \
+      description = "1 -- Input above maximum supported frequency \
+                     0 -- idle \
+                     Bit 0 -- channel 1 \
+                     Bit 1 -- channel 2 \
+                     etc. \
+                     Each bit can be cleared by writing a '1' to it";
+      prefix = "flim_pmisse";
+      type = SLV;
+      size = 6;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load = LOAD_EXT;
+    };
+    field {
+      name = "Frequency watchdog error";
+      description = "1 -- Pulse over maximum pulse count for given frequency'  \
                     0 -- idle \
                     Bit 0 -- channel 1 \
                     Bit 1 -- channel 2 \
                     etc. \
                     Each bit can be cleared by writing a '1' to it";
-      prefix = "pmisse";
+      prefix = "fwdg_pmisse";
      type = SLV;
      size = 6;
      access_dev = READ_WRITE;
@@ -144,7 +193,6 @@ peripheral {
    };
  };
  -- Control Register
  reg {
    name = "CR";
@@ -186,13 +234,98 @@ peripheral {
    };
  };
-  -- Pulse counter registers, R/W access from SysMon
+  -- Pulse counter registers for TTL pulses, R/W access from SysMon
+  reg {
+    name = "CH1TTLPCR";
+    description = "Channel 1 Pulse Counter Register for TTL pulses";
+    prefix = "ch1ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "CH2TTLPCR";
+    description = "Channel 2 Pulse Counter Register for TTL pulses";
+    prefix = "ch2ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "CH3TTLPCR";
+    description = "Channel 3 Pulse Counter Register for TTL pulses";
+    prefix = "ch3ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "CH4TTLPCR";
+    description = "Channel 4 Pulse Counter Register for TTL pulses";
+    prefix = "ch4ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "CH5TTLPCR";
+    description = "Channel 5 Pulse Counter Register for TTL pulses";
+    prefix = "ch5ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "CH6TTLPCR";
+    description = "Channel 6 Pulse Counter Register for TTL pulses";
+    prefix = "ch6ttlpcr";
+    field {
+      name = "TTL pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+  -- Pulse counter registers for blocking pulses, R/W access from SysMon
  reg {
-    name = "CH1PCR";
+    name = "CH1BLOPCR";
-    description = "Channel 1 Pulse Counter Register";
+    description = "Channel 1 Pulse Counter Register for BLO pulses";
-    prefix = "ch1pcr";
+    prefix = "ch1blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -202,11 +335,11 @@ peripheral {
  };
  reg {
-    name = "CH2PCR";
+    name = "CH2BLOPCR";
-    description = "Channel 2 Pulse Counter Register";
+    description = "Channel 2 Pulse Counter Register for BLO pulses";
-    prefix = "ch2pcr";
+    prefix = "ch2blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -216,11 +349,11 @@ peripheral {
  };
  reg {
-    name = "CH3PCR";
+    name = "CH3BLOPCR";
-    description = "Channel 3 Pulse Counter Register";
+    description = "Channel 3 Pulse Counter Register for BLO pulses";
-    prefix = "ch3pcr";
+    prefix = "ch3blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -230,11 +363,11 @@ peripheral {
  };
  reg {
-    name = "CH4PCR";
+    name = "CH4BLOPCR";
-    description = "Channel 4 Pulse Counter Register";
+    description = "Channel 4 Pulse Counter Register for BLO pulses";
-    prefix = "ch4pcr";
+    prefix = "ch4blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -244,11 +377,11 @@ peripheral {
  };
  reg {
-    name = "CH5PCR";
+    name = "CH5BLOPCR";
-    description = "Channel 5 Pulse Counter Register";
+    description = "Channel 5 Pulse Counter Register for BLO pulses";
-    prefix = "ch5pcr";
+    prefix = "ch5blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -258,11 +391,11 @@ peripheral {
  };
  reg {
-    name = "CH6PCR";
+    name = "CH6BLOPCR";
-    description = "Channel 6 Pulse Counter Register";
+    description = "Channel 6 Pulse Counter Register for BLO pulses";
-    prefix = "ch6pcr";
+    prefix = "ch6blopcr";
    field {
-      name = "Pulse counter value";
+      name = "BLO pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -317,6 +450,7 @@ peripheral {
      size = 6;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
+	  ack_read = "reg_tb_rd_req_p_o";
    };
    field {
      name = "White Rabbit present";
@@ -582,7 +716,7 @@ peripheral {
    field {
      name = "Cycles counter";
      description = "Value of the 8-ns cycles counter when time tag was taken.";
-      prefix = "tai";
      type = SLV;
      size = 28;
      access_dev = WRITE_ONLY;
@@ -816,7 +950,7 @@ peripheral {
  reg {
    name = "OSWR";
    description = "Other Switch Register";
-    prefix = "mswr";
+    prefix = "oswr";
    field {
      name = "Switch state";
      description = "1 -- switch is ON \
@@ -829,4 +963,49 @@ peripheral {
    };
  };
+-- 32 LS Bits of 64 bit ID of 1-Wire thermometer  
+  reg {
+    name = "UIDLR";
+    description = "32 LS bits of 1-wire thermometer ID";
+    prefix = "uidlr";
+    field {
+      name = "LS bits of 1-wire DS18B20U thermometer ID";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+-- 32 MS Bits of 64 bit ID of 1-Wire thermometer  
+  reg {
+    name = "UIDHR";
+    description = "32 MS bits of 1-wire thermometer ID";
+    prefix = "uidhr";
+    field {
+      name = "MS bits of 1-wire DS18B20U thermometer ID";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+     };
+  };
+-- 16 bit temperature  
+  reg {
+    name = "TEMPR";
+    description = "Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0";
+    prefix = "tempr";
+    field {
+      name = "TEMP";
+      description = "Current on-board temperature";
+      type = SLV;
+      size = 16;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
 };
--- a/modules/conv_regs_pkg.vhd
+++ b/modules/conv_regs_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Converter board registers
+---------------------------------------------------------------------------------------
+-- File           : C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs_pkg.vhd
+-- Author         : auto-generated by wbgen2 from C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
+-- Created        : 12/16/16 14:31:04
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+package reg_wbgen2_pkg is
+  -- Input registers (user design -> WB slave)
+  type t_reg_in_registers is record
+    bidr_i                                   : std_logic_vector(31 downto 0);
+    sr_gwvers_i                              : std_logic_vector(7 downto 0);
+    sr_switches_i                            : std_logic_vector(7 downto 0);
+    sr_rtm_i                                 : std_logic_vector(5 downto 0);
+    sr_i2c_wdto_i                            : std_logic;
+    sr_wrpres_i                              : std_logic;
+    sr_i2c_err_i                             : std_logic;
+    sr_pmisse_i                              : std_logic_vector(5 downto 0);
+    cr_rst_unlock_i                          : std_logic;
+    cr_rst_i                                 : std_logic;
+    ch1ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch2ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch3ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch4ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch5ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch6ttlpcr_i                              : std_logic_vector(31 downto 0);
+    ch1blopcr_i                              : std_logic_vector(31 downto 0);
+    ch2blopcr_i                              : std_logic_vector(31 downto 0);
+    ch3blopcr_i                              : std_logic_vector(31 downto 0);
+    ch4blopcr_i                              : std_logic_vector(31 downto 0);
+    ch5blopcr_i                              : std_logic_vector(31 downto 0);
+    ch6blopcr_i                              : std_logic_vector(31 downto 0);
+    tvlr_i                                   : std_logic_vector(31 downto 0);
+    tvhr_i                                   : std_logic_vector(7 downto 0);
+    tbmr_chan_i                              : std_logic_vector(5 downto 0);
+    tbmr_wrtag_i                             : std_logic;
+    tbcyr_i                                  : std_logic_vector(27 downto 0);
+    tbtlr_i                                  : std_logic_vector(31 downto 0);
+    tbthr_i                                  : std_logic_vector(7 downto 0);
+    tbcsr_usedw_i                            : std_logic_vector(6 downto 0);
+    tbcsr_full_i                             : std_logic;
+    tbcsr_empty_i                            : std_logic;
+    tbcsr_clr_i                              : std_logic;
+    ch1ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch1ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch1ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch1ltsthr_wrtag_i                        : std_logic;
+    ch2ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch2ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch2ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch2ltsthr_wrtag_i                        : std_logic;
+    ch3ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch3ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch3ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch3ltsthr_wrtag_i                        : std_logic;
+    ch4ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch4ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch4ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch4ltsthr_wrtag_i                        : std_logic;
+    ch5ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch5ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch5ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch5ltsthr_wrtag_i                        : std_logic;
+    ch6ltscyr_i                              : std_logic_vector(27 downto 0);
+    ch6ltstlr_i                              : std_logic_vector(31 downto 0);
+    ch6ltsthr_tai_i                          : std_logic_vector(7 downto 0);
+    ch6ltsthr_wrtag_i                        : std_logic;
+    lsr_front_i                              : std_logic_vector(5 downto 0);
+    lsr_frontinv_i                           : std_logic_vector(3 downto 0);
+    lsr_rear_i                               : std_logic_vector(5 downto 0);
+    lsr_frontfs_i                            : std_logic_vector(5 downto 0);
+    lsr_frontinvfs_i                         : std_logic_vector(3 downto 0);
+    lsr_rearfs_i                             : std_logic_vector(5 downto 0);
+    mswr_switches_i                          : std_logic_vector(31 downto 0);
+    ds18b20u_id_lsb_i                        : std_logic_vector(31 downto 0);
+    ds18b20u_id_msb_i                        : std_logic_vector(31 downto 0);
+    ds18b20u_temp_i                          : std_logic_vector(15 downto 0);
+    end record;
+  constant c_reg_in_registers_init_value: t_reg_in_registers := (
+    bidr_i => (others => '0'),
+    sr_gwvers_i => (others => '0'),
+    sr_switches_i => (others => '0'),
+    sr_rtm_i => (others => '0'),
+    sr_i2c_wdto_i => '0',
+    sr_wrpres_i => '0',
+    sr_i2c_err_i => '0',
+    sr_pmisse_i => (others => '0'),
+    cr_rst_unlock_i => '0',
+    cr_rst_i => '0',
+    ch1ttlpcr_i => (others => '0'),
+    ch2ttlpcr_i => (others => '0'),
+    ch3ttlpcr_i => (others => '0'),
+    ch4ttlpcr_i => (others => '0'),
+    ch5ttlpcr_i => (others => '0'),
+    ch6ttlpcr_i => (others => '0'),
+    ch1blopcr_i => (others => '0'),
+    ch2blopcr_i => (others => '0'),
+    ch3blopcr_i => (others => '0'),
+    ch4blopcr_i => (others => '0'),
+    ch5blopcr_i => (others => '0'),
+    ch6blopcr_i => (others => '0'),
+    tvlr_i => (others => '0'),
+    tvhr_i => (others => '0'),
+    tbmr_chan_i => (others => '0'),
+    tbmr_wrtag_i => '0',
+    tbcyr_i => (others => '0'),
+    tbtlr_i => (others => '0'),
+    tbthr_i => (others => '0'),
+    tbcsr_usedw_i => (others => '0'),
+    tbcsr_full_i => '0',
+    tbcsr_empty_i => '0',
+    tbcsr_clr_i => '0',
+    ch1ltscyr_i => (others => '0'),
+    ch1ltstlr_i => (others => '0'),
+    ch1ltsthr_tai_i => (others => '0'),
+    ch1ltsthr_wrtag_i => '0',
+    ch2ltscyr_i => (others => '0'),
+    ch2ltstlr_i => (others => '0'),
+    ch2ltsthr_tai_i => (others => '0'),
+    ch2ltsthr_wrtag_i => '0',
+    ch3ltscyr_i => (others => '0'),
+    ch3ltstlr_i => (others => '0'),
+    ch3ltsthr_tai_i => (others => '0'),
+    ch3ltsthr_wrtag_i => '0',
+    ch4ltscyr_i => (others => '0'),
+    ch4ltstlr_i => (others => '0'),
+    ch4ltsthr_tai_i => (others => '0'),
+    ch4ltsthr_wrtag_i => '0',
+    ch5ltscyr_i => (others => '0'),
+    ch5ltstlr_i => (others => '0'),
+    ch5ltsthr_tai_i => (others => '0'),
+    ch5ltsthr_wrtag_i => '0',
+    ch6ltscyr_i => (others => '0'),
+    ch6ltstlr_i => (others => '0'),
+    ch6ltsthr_tai_i => (others => '0'),
+    ch6ltsthr_wrtag_i => '0',
+    lsr_front_i => (others => '0'),
+    lsr_frontinv_i => (others => '0'),
+    lsr_rear_i => (others => '0'),
+    lsr_frontfs_i => (others => '0'),
+    lsr_frontinvfs_i => (others => '0'),
+    lsr_rearfs_i => (others => '0'),
+    mswr_switches_i => (others => '0'),
+    ds18b20u_id_lsb_i => (others => '0'),
+    ds18b20u_id_msb_i => (others => '0'),
+    ds18b20u_temp_i => (others => '0')
+    );
+    -- Output registers (WB slave -> user design)
+    type t_reg_out_registers is record
+      sr_i2c_wdto_o                            : std_logic;
+      sr_i2c_wdto_load_o                       : std_logic;
+      sr_i2c_err_o                             : std_logic;
+      sr_i2c_err_load_o                        : std_logic;
+      sr_pmisse_o                              : std_logic_vector(5 downto 0);
+      sr_pmisse_load_o                         : std_logic;
+      cr_rst_unlock_o                          : std_logic;
+      cr_rst_unlock_load_o                     : std_logic;
+      cr_rst_o                                 : std_logic;
+      cr_rst_load_o                            : std_logic;
+      cr_mpt_o                                 : std_logic_vector(7 downto 0);
+      cr_mpt_wr_o                              : std_logic;
+      ch1ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch1ttlpcr_load_o                         : std_logic;
+      ch2ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch2ttlpcr_load_o                         : std_logic;
+      ch3ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch3ttlpcr_load_o                         : std_logic;
+      ch4ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch4ttlpcr_load_o                         : std_logic;
+      ch5ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch5ttlpcr_load_o                         : std_logic;
+      ch6ttlpcr_o                              : std_logic_vector(31 downto 0);
+      ch6ttlpcr_load_o                         : std_logic;
+      ch1blopcr_o                              : std_logic_vector(31 downto 0);
+      ch1blopcr_load_o                         : std_logic;
+      ch2blopcr_o                              : std_logic_vector(31 downto 0);
+      ch2blopcr_load_o                         : std_logic;
+      ch3blopcr_o                              : std_logic_vector(31 downto 0);
+      ch3blopcr_load_o                         : std_logic;
+      ch4blopcr_o                              : std_logic_vector(31 downto 0);
+      ch4blopcr_load_o                         : std_logic;
+      ch5blopcr_o                              : std_logic_vector(31 downto 0);
+      ch5blopcr_load_o                         : std_logic;
+      ch6blopcr_o                              : std_logic_vector(31 downto 0);
+      ch6blopcr_load_o                         : std_logic;
+      tvlr_o                                   : std_logic_vector(31 downto 0);
+      tvlr_load_o                              : std_logic;
+      tvhr_o                                   : std_logic_vector(7 downto 0);
+      tvhr_load_o                              : std_logic;
+      tbcsr_clr_o                              : std_logic;
+      tbcsr_clr_load_o                         : std_logic;
+      end record;
+    constant c_reg_out_registers_init_value: t_reg_out_registers := (
+      sr_i2c_wdto_o => '0',
+      sr_i2c_wdto_load_o => '0',
+      sr_i2c_err_o => '0',
+      sr_i2c_err_load_o => '0',
+      sr_pmisse_o => (others => '0'),
+      sr_pmisse_load_o => '0',
+      cr_rst_unlock_o => '0',
+      cr_rst_unlock_load_o => '0',
+      cr_rst_o => '0',
+      cr_rst_load_o => '0',
+      cr_mpt_o => (others => '0'),
+      cr_mpt_wr_o => '0',
+      ch1ttlpcr_o => (others => '0'),
+      ch1ttlpcr_load_o => '0',
+      ch2ttlpcr_o => (others => '0'),
+      ch2ttlpcr_load_o => '0',
+      ch3ttlpcr_o => (others => '0'),
+      ch3ttlpcr_load_o => '0',
+      ch4ttlpcr_o => (others => '0'),
+      ch4ttlpcr_load_o => '0',
+      ch5ttlpcr_o => (others => '0'),
+      ch5ttlpcr_load_o => '0',
+      ch6ttlpcr_o => (others => '0'),
+      ch6ttlpcr_load_o => '0',
+      ch1blopcr_o => (others => '0'),
+      ch1blopcr_load_o => '0',
+      ch2blopcr_o => (others => '0'),
+      ch2blopcr_load_o => '0',
+      ch3blopcr_o => (others => '0'),
+      ch3blopcr_load_o => '0',
+      ch4blopcr_o => (others => '0'),
+      ch4blopcr_load_o => '0',
+      ch5blopcr_o => (others => '0'),
+      ch5blopcr_load_o => '0',
+      ch6blopcr_o => (others => '0'),
+      ch6blopcr_load_o => '0',
+      tvlr_o => (others => '0'),
+      tvlr_load_o => '0',
+      tvhr_o => (others => '0'),
+      tvhr_load_o => '0',
+      tbcsr_clr_o => '0',
+      tbcsr_clr_load_o => '0'
+      );
+    function "or" (left, right: t_reg_in_registers) return t_reg_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+package body reg_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_reg_in_registers) return t_reg_in_registers is
+variable tmp: t_reg_in_registers;
+begin
+tmp.bidr_i := f_x_to_zero(left.bidr_i) or f_x_to_zero(right.bidr_i);
+tmp.sr_gwvers_i := f_x_to_zero(left.sr_gwvers_i) or f_x_to_zero(right.sr_gwvers_i);
+tmp.sr_switches_i := f_x_to_zero(left.sr_switches_i) or f_x_to_zero(right.sr_switches_i);
+tmp.sr_rtm_i := f_x_to_zero(left.sr_rtm_i) or f_x_to_zero(right.sr_rtm_i);
+tmp.sr_i2c_wdto_i := f_x_to_zero(left.sr_i2c_wdto_i) or f_x_to_zero(right.sr_i2c_wdto_i);
+tmp.sr_wrpres_i := f_x_to_zero(left.sr_wrpres_i) or f_x_to_zero(right.sr_wrpres_i);
+tmp.sr_i2c_err_i := f_x_to_zero(left.sr_i2c_err_i) or f_x_to_zero(right.sr_i2c_err_i);
+tmp.sr_pmisse_i := f_x_to_zero(left.sr_pmisse_i) or f_x_to_zero(right.sr_pmisse_i);
+tmp.cr_rst_unlock_i := f_x_to_zero(left.cr_rst_unlock_i) or f_x_to_zero(right.cr_rst_unlock_i);
+tmp.cr_rst_i := f_x_to_zero(left.cr_rst_i) or f_x_to_zero(right.cr_rst_i);
+tmp.ch1ttlpcr_i := f_x_to_zero(left.ch1ttlpcr_i) or f_x_to_zero(right.ch1ttlpcr_i);
+tmp.ch2ttlpcr_i := f_x_to_zero(left.ch2ttlpcr_i) or f_x_to_zero(right.ch2ttlpcr_i);
+tmp.ch3ttlpcr_i := f_x_to_zero(left.ch3ttlpcr_i) or f_x_to_zero(right.ch3ttlpcr_i);
+tmp.ch4ttlpcr_i := f_x_to_zero(left.ch4ttlpcr_i) or f_x_to_zero(right.ch4ttlpcr_i);
+tmp.ch5ttlpcr_i := f_x_to_zero(left.ch5ttlpcr_i) or f_x_to_zero(right.ch5ttlpcr_i);
+tmp.ch6ttlpcr_i := f_x_to_zero(left.ch6ttlpcr_i) or f_x_to_zero(right.ch6ttlpcr_i);
+tmp.ch1blopcr_i := f_x_to_zero(left.ch1blopcr_i) or f_x_to_zero(right.ch1blopcr_i);
+tmp.ch2blopcr_i := f_x_to_zero(left.ch2blopcr_i) or f_x_to_zero(right.ch2blopcr_i);
+tmp.ch3blopcr_i := f_x_to_zero(left.ch3blopcr_i) or f_x_to_zero(right.ch3blopcr_i);
+tmp.ch4blopcr_i := f_x_to_zero(left.ch4blopcr_i) or f_x_to_zero(right.ch4blopcr_i);
+tmp.ch5blopcr_i := f_x_to_zero(left.ch5blopcr_i) or f_x_to_zero(right.ch5blopcr_i);
+tmp.ch6blopcr_i := f_x_to_zero(left.ch6blopcr_i) or f_x_to_zero(right.ch6blopcr_i);
+tmp.tvlr_i := f_x_to_zero(left.tvlr_i) or f_x_to_zero(right.tvlr_i);
+tmp.tvhr_i := f_x_to_zero(left.tvhr_i) or f_x_to_zero(right.tvhr_i);
+tmp.tbmr_chan_i := f_x_to_zero(left.tbmr_chan_i) or f_x_to_zero(right.tbmr_chan_i);
+tmp.tbmr_wrtag_i := f_x_to_zero(left.tbmr_wrtag_i) or f_x_to_zero(right.tbmr_wrtag_i);
+tmp.tbcyr_i := f_x_to_zero(left.tbcyr_i) or f_x_to_zero(right.tbcyr_i);
+tmp.tbtlr_i := f_x_to_zero(left.tbtlr_i) or f_x_to_zero(right.tbtlr_i);
+tmp.tbthr_i := f_x_to_zero(left.tbthr_i) or f_x_to_zero(right.tbthr_i);
+tmp.tbcsr_usedw_i := f_x_to_zero(left.tbcsr_usedw_i) or f_x_to_zero(right.tbcsr_usedw_i);
+tmp.tbcsr_full_i := f_x_to_zero(left.tbcsr_full_i) or f_x_to_zero(right.tbcsr_full_i);
+tmp.tbcsr_empty_i := f_x_to_zero(left.tbcsr_empty_i) or f_x_to_zero(right.tbcsr_empty_i);
+tmp.tbcsr_clr_i := f_x_to_zero(left.tbcsr_clr_i) or f_x_to_zero(right.tbcsr_clr_i);
+tmp.ch1ltscyr_i := f_x_to_zero(left.ch1ltscyr_i) or f_x_to_zero(right.ch1ltscyr_i);
+tmp.ch1ltstlr_i := f_x_to_zero(left.ch1ltstlr_i) or f_x_to_zero(right.ch1ltstlr_i);
+tmp.ch1ltsthr_tai_i := f_x_to_zero(left.ch1ltsthr_tai_i) or f_x_to_zero(right.ch1ltsthr_tai_i);
+tmp.ch1ltsthr_wrtag_i := f_x_to_zero(left.ch1ltsthr_wrtag_i) or f_x_to_zero(right.ch1ltsthr_wrtag_i);
+tmp.ch2ltscyr_i := f_x_to_zero(left.ch2ltscyr_i) or f_x_to_zero(right.ch2ltscyr_i);
+tmp.ch2ltstlr_i := f_x_to_zero(left.ch2ltstlr_i) or f_x_to_zero(right.ch2ltstlr_i);
+tmp.ch2ltsthr_tai_i := f_x_to_zero(left.ch2ltsthr_tai_i) or f_x_to_zero(right.ch2ltsthr_tai_i);
+tmp.ch2ltsthr_wrtag_i := f_x_to_zero(left.ch2ltsthr_wrtag_i) or f_x_to_zero(right.ch2ltsthr_wrtag_i);
+tmp.ch3ltscyr_i := f_x_to_zero(left.ch3ltscyr_i) or f_x_to_zero(right.ch3ltscyr_i);
+tmp.ch3ltstlr_i := f_x_to_zero(left.ch3ltstlr_i) or f_x_to_zero(right.ch3ltstlr_i);
+tmp.ch3ltsthr_tai_i := f_x_to_zero(left.ch3ltsthr_tai_i) or f_x_to_zero(right.ch3ltsthr_tai_i);
+tmp.ch3ltsthr_wrtag_i := f_x_to_zero(left.ch3ltsthr_wrtag_i) or f_x_to_zero(right.ch3ltsthr_wrtag_i);
+tmp.ch4ltscyr_i := f_x_to_zero(left.ch4ltscyr_i) or f_x_to_zero(right.ch4ltscyr_i);
+tmp.ch4ltstlr_i := f_x_to_zero(left.ch4ltstlr_i) or f_x_to_zero(right.ch4ltstlr_i);
+tmp.ch4ltsthr_tai_i := f_x_to_zero(left.ch4ltsthr_tai_i) or f_x_to_zero(right.ch4ltsthr_tai_i);
+tmp.ch4ltsthr_wrtag_i := f_x_to_zero(left.ch4ltsthr_wrtag_i) or f_x_to_zero(right.ch4ltsthr_wrtag_i);
+tmp.ch5ltscyr_i := f_x_to_zero(left.ch5ltscyr_i) or f_x_to_zero(right.ch5ltscyr_i);
+tmp.ch5ltstlr_i := f_x_to_zero(left.ch5ltstlr_i) or f_x_to_zero(right.ch5ltstlr_i);
+tmp.ch5ltsthr_tai_i := f_x_to_zero(left.ch5ltsthr_tai_i) or f_x_to_zero(right.ch5ltsthr_tai_i);
+tmp.ch5ltsthr_wrtag_i := f_x_to_zero(left.ch5ltsthr_wrtag_i) or f_x_to_zero(right.ch5ltsthr_wrtag_i);
+tmp.ch6ltscyr_i := f_x_to_zero(left.ch6ltscyr_i) or f_x_to_zero(right.ch6ltscyr_i);
+tmp.ch6ltstlr_i := f_x_to_zero(left.ch6ltstlr_i) or f_x_to_zero(right.ch6ltstlr_i);
+tmp.ch6ltsthr_tai_i := f_x_to_zero(left.ch6ltsthr_tai_i) or f_x_to_zero(right.ch6ltsthr_tai_i);
+tmp.ch6ltsthr_wrtag_i := f_x_to_zero(left.ch6ltsthr_wrtag_i) or f_x_to_zero(right.ch6ltsthr_wrtag_i);
+tmp.lsr_front_i := f_x_to_zero(left.lsr_front_i) or f_x_to_zero(right.lsr_front_i);
+tmp.lsr_frontinv_i := f_x_to_zero(left.lsr_frontinv_i) or f_x_to_zero(right.lsr_frontinv_i);
+tmp.lsr_rear_i := f_x_to_zero(left.lsr_rear_i) or f_x_to_zero(right.lsr_rear_i);
+tmp.lsr_frontfs_i := f_x_to_zero(left.lsr_frontfs_i) or f_x_to_zero(right.lsr_frontfs_i);
+tmp.lsr_frontinvfs_i := f_x_to_zero(left.lsr_frontinvfs_i) or f_x_to_zero(right.lsr_frontinvfs_i);
+tmp.lsr_rearfs_i := f_x_to_zero(left.lsr_rearfs_i) or f_x_to_zero(right.lsr_rearfs_i);
+tmp.mswr_switches_i := f_x_to_zero(left.mswr_switches_i) or f_x_to_zero(right.mswr_switches_i);
+tmp.ds18b20u_id_lsb_i := f_x_to_zero(left.ds18b20u_id_lsb_i) or f_x_to_zero(right.ds18b20u_id_lsb_i);
+tmp.ds18b20u_id_msb_i := f_x_to_zero(left.ds18b20u_id_msb_i) or f_x_to_zero(right.ds18b20u_id_msb_i);
+tmp.ds18b20u_temp_i := f_x_to_zero(left.ds18b20u_temp_i) or f_x_to_zero(right.ds18b20u_temp_i);
+return tmp;
+end function;
+end package body;
--- a/modules/wf_decr_counter.vhd
+++ b/modules/wf_decr_counter.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.conv_common_gw_pkg.all;
+entity wf_decr_counter is
+  generic(g_counter_lgth : natural := 4);                         -- default length
+  port(
+  -- INPUTS
+    -- nanoFIP User Interface general signal
+    uclk_i            : in std_logic;                             -- 40 MHz clock
+    -- Signal from the wf_reset_unit
+    counter_rst_i     : in std_logic;                             -- resets counter to all '1'
+    -- Signals from any unit
+    counter_decr_i    : in std_logic;                             -- decrement enable
+    counter_load_i    : in std_logic;                             -- load enable; loads counter to counter_top_i
+    counter_top_i     : in unsigned (g_counter_lgth-1 downto 0);  -- load value
+  -- OUTPUTS
+    -- Signal to any unit
+    counter_o         : out unsigned (g_counter_lgth-1 downto 0); -- counter
+    counter_is_zero_o : out std_logic);                           -- empty counter indication
+end entity wf_decr_counter;
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+architecture rtl of wf_decr_counter is
+  signal s_counter : unsigned (g_counter_lgth-1 downto 0);
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+---------------------------------------------------------------------------------------------------
+  -- Synchronous process Decr_Counter
+  Decr_Counter: process (uclk_i)
+  begin
+    if rising_edge (uclk_i) then
+      if counter_rst_i = '1' then
+        s_counter   <= (others => '1');
+      else
+        if counter_load_i = '1' then
+          s_counter <= counter_top_i;
+        elsif counter_decr_i = '1' then
+          s_counter <= s_counter - 1;
+        end if;
+      end if;
+    end if;
+  end process;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  counter_o         <= s_counter;
+  counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
+  end architecture ;
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -39,11 +39,7 @@
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
 --==============================================================================
-- last changes:
--    2014-07-24   Theodor Stana     File created
--==============================================================================
-- TODO: -
--==============================================================================
 library ieee;
 use ieee.std_logic_1164.all;
@@ -63,27 +59,51 @@ entity conv_common_gw is
  (
    -- Number of repeater channels
    g_nr_chans             : integer := 6;
+    -- Number of inverter channels
+    g_nr_inv_chans         : integer := 4;
    -- Board ID -- 4-letter ASCII string indicating the board ID
    -- see [1] for example
-    g_board_id             : std_logic_vector(31 downto 0);
+    g_board_id             : std_logic_vector(31 downto 0) := x"54424c4f";
    -- Gateware version
-    g_gwvers               : std_logic_vector(7 downto 0);
+    g_gwvers               : std_logic_vector(7 downto 0) :=x"40";
    -- Generate pulse repetition logic with fixed output pulse width
-    g_pgen_fixed_width     : boolean;
+    g_pgen_fixed_width     : boolean := true ;
    -- Pulse width at pulse generator output (valid with fixed output pulse width)
-    g_pgen_pwidth          : natural := 24;
-    -- Duty cycle divider ratio for pulse generator
+    g_pgen_pwidth_lg       : natural range 2 to 40 := 24; 
-    -- output pulse will be limited to 1/g_pgen_duty_cycle_div
+    g_pgen_pwidth_sh       : natural range 2 to 40 := 5; 
-    g_pgen_duty_cycle_div  : natural := 5;
+    -- Output pulse will be limited to period. They are given as n number of cycles
+    -- For continuous mode operation max freq 4.16kHz
+    g_pgen_pperiod_cont    : natural range 2 to 5000 := 4800; 
+    --for LONG pulses changes maximum frequency to ~104kHz
+    g_pgen_pperiod_lg      : natural range 6 to 300 := 191;
+    --for SHORT pulses changes maximum frequency to ~2MHz
+    g_pgen_pperiod_sh      : natural range 2 to 300 := 9;
    -- Pulse generator glitch filter length in number of clk_20_i cycles
    g_pgen_gf_len          : integer := 4;
+    -- Burst-mode-specific generics:
+    g_temp_decre_step_lg    : t_temp_decre_step :=
+                                    (0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
+    g_temp_decre_step_sh    : t_temp_decre_step :=
+                        (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
+    -- Single pulse temperature rise
+    -- For long 1.2us pulses 
+    g_burstctrl_1_pulse_temp_rise_lg    :in unsigned (19 downto 0) := x"17700";
+    -- For short 250ns pulses 
+    g_burstctrl_1_pulse_temp_rise_sh    :in unsigned (19 downto 0) := x"01388"; 
+    -- Maximum temperature allowed (scaled)
+    g_burstctrl_max_temp_lg_sh          :in unsigned (39 downto 0) 
+                :=x"02540BE400"; --For both long 1.2us pulses and short 250ns
    -- Generate logic with pulse counters
    g_with_pulse_cnt                    : boolean := false;
-    -- Generate logic with pulse counters
+    -- Generate logic with pulse timetag
    g_with_pulse_timetag                : boolean := false;
    -- Generate logic with manual trigger
@@ -110,20 +130,36 @@ entity conv_common_gw is
    -- Glitch filter active-low enable signal
    gf_en_n_i               : in  std_logic;	  
+    -- Burst mode enable signal. Mode disabled for all versions of board
+    burst_en_n_i			: in std_logic;
+    -- Pulse width selection, port low means 250ns, high means 1.2us.		
+    pulse_width_sel_n_i	: in std_logic;
    -- Channel enable
    global_ch_oen_o         : out std_logic;
    pulse_front_oen_o       : out std_logic;
    pulse_rear_oen_o        : out std_logic;
    inv_oen_o               : out std_logic;
-    -- Pulse inputs
+    -- Pulse I/O
    pulse_i                 : in  std_logic_vector(g_nr_chans-1 downto 0);
+    pulse_front_i             : in  std_logic_vector(g_nr_chans-1 downto 0);
+    pulse_rear_i             : in  std_logic_vector(g_nr_chans-1 downto 0);
    pulse_o                 : out std_logic_vector(g_nr_chans-1 downto 0);
-    -- Channel leds
+    -- Inverted pulse I/O
+    inv_pulse_i_n			: in  std_logic_vector(g_nr_inv_chans-1 downto 0);
+    inv_pulse_o				: out  std_logic_vector(g_nr_inv_chans-1 downto 0);
+    -- Channel lEDs
    -- 26 ms active-high pulse on pulse_o rising edge
    led_pulse_o             : out std_logic_vector(g_nr_chans-1 downto 0);
+    -- Inverted channel lEDs
+    -- 26 ms active-high pulse on pulse_o rising edge
+    led_inv_pulse_o         : out std_logic_vector(g_nr_inv_chans-1 downto 0);
    -- I2C interface
    scl_i                   : in  std_logic;
    scl_o                   : out std_logic;
@@ -159,10 +195,10 @@ entity conv_common_gw is
    -- SFP lines
    sfp_los_i               : in    std_logic;
-    sfp_mod_def0_i          : in    std_logic;
+    sfp_present_i           : in    std_logic;
    sfp_rate_select_o       : out   std_logic;
-    sfp_mod_def1_b          : inout std_logic;
+    sfp_sda_b               : inout std_logic;
-    sfp_mod_def2_b          : inout std_logic;
+    sfp_scl_i               : inout std_logic;
    sfp_tx_disable_o        : out   std_logic;
    sfp_tx_fault_i          : in    std_logic;
@@ -170,18 +206,20 @@ entity conv_common_gw is
    sw_gp_i                 : in  std_logic_vector(7 downto 0);
    sw_other_i              : in  std_logic_vector(31 downto 0);
+    -- PCB Version information
+    hwvers_i                : in std_logic_vector (5 downto 0);
    -- RTM lines
    rtmm_i                  : in  std_logic_vector(2 downto 0);
    rtmp_i                  : in  std_logic_vector(2 downto 0);
    -- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
    line_front_i            : in std_logic_vector(g_nr_chans-1 downto 0);
-    line_inv_i              : in std_logic_vector(3 downto 0);
+    line_inv_i              : in std_logic_vector(g_nr_inv_chans-1 downto 0);
    line_rear_i             : in std_logic_vector(g_nr_chans-1 downto 0);
    -- Fail-safe lines, detect invalid or no signal on channel input
    line_front_fs_i         : in std_logic_vector(g_nr_chans-1 downto 0);
-    line_inv_fs_i           : in std_logic_vector(3 downto 0);
+    line_inv_fs_i           : in std_logic_vector(g_nr_inv_chans-1 downto 0);
    line_rear_fs_i          : in std_logic_vector(g_nr_chans-1 downto 0);
    -- Thermometer line
@@ -200,14 +238,21 @@ entity conv_common_gw is
 end entity conv_common_gw;
 architecture arch of conv_common_gw is
  --============================================================================
  -- Constant declarations
  --============================================================================
+  -- Short pulse widths 
+  --constant c_pgen_pwidth_sh   : natural := 5;
+  -- Burst mode maximum duty cycle is 50%, i.e. divider is 2
+  constant c_pgen_duty_cycle_div_sh   : natural := 2;
  -- Number of Wishbone masters and slaves, for wb_crossbar
  constant c_nr_masters       : natural :=  1;
-  constant c_nr_slaves        : natural :=  3;
+  constant c_nr_slaves        : natural :=  2;
  -- slave order definitions
  constant c_slv_conv_regs    : natural := 0;
@@ -217,17 +262,18 @@ architecture arch of conv_common_gw is
  -- base address definitions
  constant c_addr_conv_regs   : t_wishbone_address := x"00000000";
  constant c_addr_multiboot   : t_wishbone_address := x"00000100";
-  constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
+  --constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
  constant c_addr_sdb         : t_wishbone_address := x"00000f00";
  -- SDB interconnect layout
  -- c_conv_regs_sdb defined in conv_common_gw_pkg.vhd
  constant c_sdb_layout : t_sdb_record_array(c_nr_slaves-1 downto 0) := (
      c_slv_conv_regs => f_sdb_embed_device(c_conv_regs_sdb, c_addr_conv_regs),
      c_slv_multiboot => f_sdb_embed_device(c_xwb_xil_multiboot_sdb,
-                              c_addr_multiboot),
+                              c_addr_multiboot)
-      c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
+  --    c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
-                              c_addr_onewire_mst)
+  --                            c_addr_onewire_mst)
    );
  -- Tag bufferdata width:  40 -- TAI
@@ -242,6 +288,12 @@ architecture arch of conv_common_gw is
  -- Max. channel count of c_max_nr_chans enforced here:
  type t_pulse_led_cnt is array(c_max_nr_chans-1 downto 0)
                            of unsigned(18 downto 0);
+  type t_inv_pulse_led_cnt is array(g_nr_inv_chans-1 downto 0) 
+                            of unsigned(18 downto 0); 
+  type t_temp_rise_cnt is array(c_max_nr_chans-1 downto 0)
+                            of unsigned(39 downto 0);
  type t_pulse_cnt is array(c_max_nr_chans-1 downto 0)
                        of unsigned(31 downto 0);
  type t_ch_pcr is array(c_max_nr_chans-1 downto 0)
@@ -260,6 +312,7 @@ architecture arch of conv_common_gw is
  signal clk_125             	: std_logic;
  signal rst_125_n           	: std_logic;
  signal rst_20_n            	: std_logic;
+  signal rst_20            		: std_logic;
  signal rst_ext             	: std_logic;
  -- Pulse logic signals
@@ -268,12 +321,36 @@ architecture arch of conv_common_gw is
  signal trig_degl           	: std_logic_vector(g_nr_chans-1 downto 0);
  signal trig_chan           	: std_logic_vector(g_nr_chans-1 downto 0);
  signal trig_chan_redge_p   	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal trig_chan_fedge_p   	: std_logic_vector(g_nr_chans-1 downto 0);
  signal trig_man            	: std_logic_vector(g_nr_chans-1 downto 0);
  signal trig_pgen           	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal burst_en_n				: std_logic;
+  signal pulse_outp_cont    	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal burst_outp_sh    		: std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_r_edge_lg_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_f_edge_lg_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_r_edge_sh_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_f_edge_sh_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_outp_sh    		: std_logic_vector(g_nr_chans-1 downto 0);
+  signal burst_outp_lg   		: std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_outp_lg    		: std_logic_vector(g_nr_chans-1 downto 0);
  signal pulse_outp	      		: std_logic_vector(g_nr_chans-1 downto 0);
+  signal temp_rise_c_lg			: t_temp_rise_cnt;
+  signal temp_rise_c_sh			: t_temp_rise_cnt;
  signal pulse_outp_d0       	: std_logic_vector(g_nr_chans-1 downto 0);
  signal pulse_outp_redge_p  	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal inv_pulse_outp      	: std_logic_vector(g_nr_inv_chans-1 downto 0);
+  signal inv_pulse_outp_d0     	: std_logic_vector(g_nr_inv_chans-1 downto 0);
+  signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0);
  signal pmisse_p            	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal flim_pmisse_p          : std_logic_vector(g_nr_chans-1 downto 0);
+  signal fwdg_pmisse_p          : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_outp_err_cont	: std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_outp_err_lg_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal pulse_outp_err_sh_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal burst_outp_err_lg_p      : std_logic_vector(g_nr_chans-1 downto 0);
+  signal burst_outp_err_sh_p      : std_logic_vector(g_nr_chans-1 downto 0);
  -- Output enable signals
  signal global_oen          	: std_logic;
@@ -300,12 +377,28 @@ architecture arch of conv_common_gw is
  signal i2c_wdto_bit_rst    : std_logic;
  signal i2c_wdto_bit_rst_ld : std_logic;
  signal pmisse_bit          : std_logic_vector(c_max_nr_chans-1 downto 0);
-  signal pmisse_bit_rst      : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal flim_pmisse_bit          : std_logic_vector(c_max_nr_chans-1 downto 0);
-  signal pmisse_bit_rst_ld   : std_logic;
+  signal flim_pmisse_bit_rst      : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal flim_pmisse_bit_rst_ld   : std_logic;
+  signal fwdg_pmisse_bit          : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal fwdg_pmisse_bit_rst      : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal fwdg_pmisse_bit_rst_ld   : std_logic;
  signal pmisse_bits_or      : std_logic;
+  --signals for pulse counters
+  signal rst_ttl_cnt        : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal rst_blo_cnt        : std_logic_vector(c_max_nr_chans-1 downto 0);
  signal pulse_cnt           : t_pulse_cnt;
-  signal ch_pcr              : t_ch_pcr;
+  signal ttl_pulse_cnt       : t_pulse_cnt;
-  signal ch_pcr_ld           : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal blo_pulse_cnt       : t_pulse_cnt;
+  signal ttl_pulse_cnt_offset    : t_pulse_cnt;
+  signal blo_pulse_cnt_offset    : t_pulse_cnt;
+  signal ttl_pulse_c         : t_pulse_cnt;
+  signal blo_pulse_c         : t_pulse_cnt;
+  signal ch_ttl_pcr          : t_ch_pcr;
+  signal ch_ttl_pcr_ld       : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal ch_blo_pcr          : t_ch_pcr;
+  signal ch_blo_pcr_ld       : std_logic_vector(c_max_nr_chans-1 downto 0);
  signal mpt_ld              : std_logic;
  signal mpt                 : std_logic_vector( 7 downto 0);
  signal tvlr                : std_logic_vector(31 downto 0);
@@ -324,6 +417,8 @@ architecture arch of conv_common_gw is
  -- LED signals
  signal led_pulse           : std_logic_vector(g_nr_chans-1 downto 0);
  signal led_pulse_cnt       : t_pulse_led_cnt;
+  signal led_inv_pulse       : std_logic_vector(g_nr_inv_chans-1 downto 0);
+  signal led_inv_pulse_cnt   : t_pulse_led_cnt;
  signal led_i2c             : std_logic;
  signal led_i2c_clkdiv      : unsigned(18 downto 0);
  signal led_i2c_cnt         : unsigned( 2 downto 0);
@@ -370,11 +465,63 @@ architecture arch of conv_common_gw is
  signal owr_en               : std_logic_vector(0 downto 0);
  signal owr_in               : std_logic_vector(0 downto 0);
+  signal pps_is_zero		: std_logic;
+  signal tmp_id				: std_logic_vector(63 downto 0);
+  signal tmp_temper			: std_logic_vector(15 downto 0);
+  signal onewire_read_p 	: std_logic; 
+  signal pps_load_p			: std_logic;
+  signal id					: std_logic_vector(63 downto 0);
+  signal temper  			: std_logic_vector(15 downto 0); 
+  --Chipscope signals 
+  ---------------------------------------------------------------------------------------------------
+   signal CONTROL : std_logic_vector(35 downto 0);
+   signal CLK     : std_logic;
+   signal TRIG0_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG1_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG2_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG3_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG4_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG5_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG6_in  : std_logic_vector(7 downto 0);
+   -- signal TRIG7_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG8_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG9_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG10_in   : std_logic_vector(7 downto 0);
+   -- signal TRIG11_in   : std_logic_vector(7 downto 0);
 --==============================================================================
 --  architecture begin
 --==============================================================================
 begin
+---------------------------------------------------------------------------------------------------
+--       CHIPSCOPE       --
+---------------------------------------------------------------------------------------------------
+  -- chipscope_ila_1 : chipscope_ila
+  -- port map (
+    -- CONTROL => CONTROL,
+    -- CLK     => clk_20_i,
+    -- TRIG0   => TRIG0_in);
+  -- chipscope_icon_1 : chipscope_icon
+  -- port map ( CONTROL0 => CONTROL);
+  -- TRIG0_in(0)   <= pulse_outp_err_sh_p(5);
+  -- TRIG0_in(1)   <= burst_outp_err_sh_p(5);
+  -- TRIG0_in(2)   <= trig_pgen(5);
+  -- TRIG0_in(3)   <= pulse_outp_sh(5);
+  -- TRIG0_in(4)   <= pulse_outp_err_lg_p(5);
+  -- TRIG0_in(5)   <= burst_outp_err_lg_p(5); 
+  -- TRIG0_in(6)   <= pulse_outp_lg(5);
+  -- TRIG0_in(7)   <= ch_ttl_pcr_ld(5);
  --============================================================================
  -- Differential input buffer for 125 MHz clock
  --============================================================================
@@ -432,6 +579,7 @@ begin
  --============================================================================
  -- Enable outputs only when the FPGA is ready to handle them
  -- One clock cycle delay from global OEN to rest of OENs
  p_delay_oen : process (clk_20_i) is
  begin
    if rising_edge(clk_20_i) then
@@ -440,12 +588,14 @@ begin
        ttl_oen    <= '0';
        invttl_oen <= '0';
        rear_oen   <= '0';
+        burst_en_n <= '0';
      else
        global_oen <= '1';
        if global_oen = '1' then
          ttl_oen    <= '1';
          invttl_oen <= '1';
          rear_oen   <= '1';
+          burst_en_n <= burst_en_n_i;
        end if;
      end if;
    end if;
@@ -463,7 +613,7 @@ begin
  trig_a <= pulse_i;
 --------------------------------------------------------------------------------
-gen_man_trig : if (g_with_man_trig = true) generate
+ gen_man_trig : if (g_with_man_trig = true) generate
  -- Manual trigger logic
  cmp_man_trig : conv_man_trig
    generic map
@@ -487,9 +637,9 @@ gen_no_man_trig : if (g_with_man_trig = false) generate
  trig_man <= (others => '0');
 end generate gen_no_man_trig;
 --------------------------------------------------------------------------------
+-- Glitch filter
--------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
  -- Synchronize the asynchronous trigger input into the 20 MHz clock
@@ -526,60 +676,112 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
  trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
                  trig_degl(i);
+  -- The trigger to the pulse generator is either manual OR from the channel input
+  trig_pgen(i) <= trig_chan(i) or trig_man(i);
  -- Now, sync this channel trigger signal before passing it to the counters
  --
  -- The pulse counter is triggered only by a pulse that actually makes it
  -- to the pulse generator.
  --
  -- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-  -- another sync chain here avoids extra logic complication and shoudl have
+  -- another sync chain here avoids extra logic complication and should have
  -- no influence on the correctness of the pulse counter value
  cmp_sync_ffs : gc_sync_ffs
    port map
    (
      clk_i    => clk_20_i,
      rst_n_i  => rst_20_n,
-      data_i   => trig_chan(i),
+      data_i   => trig_pgen(i),
-      ppulse_o => trig_chan_redge_p(i)
+      ppulse_o => trig_chan_redge_p(i),
+      npulse_o => trig_chan_fedge_p(i)
    );
+--------------------------------------------------------------------------------
+-- Pulse counters:
+--------------------------------------------------------------------------------
+-- Use Flacter based fast counters to count fast pulses
+-- See for more details https://www.doulos.com/knowhow/fpga/fastcounter/
+-- The counter below has additional integer output value of the counter plus a 
+-- reset signal that depends on the system reset in addition to the counter load pulse
 --------------------------------------------------------------------------------
 gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
-  -- First, the pulse counters for the used channes (up to g_nr_chans)
+rst_ttl_cnt(i) <= rst_20 or ch_ttl_pcr_ld(i);
+rst_blo_cnt(i) <= rst_20 or ch_blo_pcr_ld(i);
+cmp_pulse_cnt_ttl:  fastevent_counter
+  port map(
+        sysclk_i    => clk_20_i,
+        rstcount_i  => rst_ttl_cnt(i),
+        en_i        => '1',
+        trig_i      => pulse_front_i(i),
+        count_int_o => ttl_pulse_c(i)
+   );   
+cmp_pulse_cnt_blo:  fastevent_counter
+  port map(
+        sysclk_i    => clk_20_i,
+        rstcount_i  => rst_blo_cnt(i),
+        en_i        => '1',
+        trig_i      => pulse_rear_i(i),
+        count_int_o => blo_pulse_c(i)
+   ); 
+  -- First, the pulse counters for the used channels (up to g_nr_chans)
  p_pulse_cnt : process (clk_20_i)
  begin
    if rising_edge(clk_20_i) then
        if (rst_20_n = '0') then
            pulse_cnt(i) <= (others => '0');
-      elsif (ch_pcr_ld(i) = '1') then
+            ttl_pulse_cnt(i)    <= (others => '0');
-        pulse_cnt(i) <= unsigned(ch_pcr(i));
+            blo_pulse_cnt(i)    <= (others => '0');
-      elsif (trig_chan_redge_p(i) = '1') then
+            ttl_pulse_cnt_offset(i) <= (others => '0');
-        pulse_cnt(i) <= pulse_cnt(i) + 1;
+            blo_pulse_cnt_offset(i) <= (others => '0');
+        elsif (ch_ttl_pcr_ld(i) = '1') then
+                ttl_pulse_cnt_offset(i) <= unsigned(ch_ttl_pcr(i));
+        elsif (ch_blo_pcr_ld(i) = '1') then
+                blo_pulse_cnt_offset(i) <= unsigned(ch_blo_pcr(i));
+        else
+                ttl_pulse_cnt(i) <= ttl_pulse_cnt_offset(i)+ ttl_pulse_c(i);
+                blo_pulse_cnt(i) <= blo_pulse_cnt_offset(i)+ blo_pulse_c(i);
        end if;
    end if;
  end process p_pulse_cnt;
 --------------------------------------------------------------------------------
 -- Connect pulse counter values for unused channels to all zeroes
 gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
  pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
+  ttl_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
+  blo_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
 end generate gen_pulse_cnt_unused_chans;
 --------------------------------------------------------------------------------
 end generate gen_pulse_cnt;
 --------------------------------------------------------------------------------
-  -- The trigger to the pulse generator is either manual OR from the channel input
-  trig_pgen(i) <= trig_chan(i) or trig_man(i);
-  -- Instantiate pulse generator block for the channel
+-------------------------------------------------------------------------------------------------
-  cmp_pulse_gen : conv_pulse_gen
+-- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation
+-------------------------------------------------------------------------------------------------
+-- CONTINUOUS MODE
+-------------------
+  --Instantiate pulse generator block for continuous operation without burst feature
+  cmp_pulse_gen_cont : conv_pulse_gen
    generic map
    (
      g_with_fixed_pwidth => g_pgen_fixed_width,
-      g_pwidth            => g_pgen_pwidth,
+      g_pwidth            => g_pgen_pwidth_lg,
-      g_duty_cycle_div    => g_pgen_duty_cycle_div
+      g_pperiod           => g_pgen_pperiod_cont
    )
    port map
    (
@@ -591,12 +793,153 @@ end generate gen_pulse_cnt;
      en_i          => '1',
      trig_a_i      => trig_pgen(i),
+      trig_r_edge_p_i => trig_chan_redge_p(i),
+      trig_f_edge_p_i => trig_chan_fedge_p(i),
-      pulse_err_p_o => pmisse_p(i),
+      pulse_err_p_o => pulse_outp_err_cont (i),
-      pulse_o       => pulse_outp(i)
+      pulse_o       => pulse_outp_cont(i)
    );
+  ----------------------------------------------------------------------------------------------
+  -- Instantiate pulse generator + burst controller block for the channel for long pulse operation
+  -------------------------------------------------------------------------------------------------
+  -- BURST MODE WITH LONG PULSES
+  ----------------------------------
+  --Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
+    cmp_pulse_gen_lg : conv_pulse_gen
+    generic map
+    (
+      g_with_fixed_pwidth => g_pgen_fixed_width,
+      g_pwidth            => g_pgen_pwidth_lg,
+      g_pperiod           => g_pgen_pperiod_lg
+    )
+    port map
+    (
+      clk_i         => clk_20_i,
+      rst_n_i       => rst_20_n,
+      gf_en_n_i     => gf_en_n_i,
+      en_i          => '1',
+      trig_a_i      => trig_pgen(i),
+      trig_r_edge_p_i => trig_chan_redge_p(i),
+      trig_f_edge_p_i => trig_chan_fedge_p(i),
+      pulse_err_p_o => pulse_outp_err_lg_p (i),
+      pulse_o       => pulse_outp_lg(i),
+      pulse_r_edge_p_o       => pulse_r_edge_lg_p(i),
+      pulse_f_edge_p_o       => pulse_f_edge_lg_p(i)
+    );
+    ----------------------------------------------------------------------------------
+    -- Instantiate burst control block for the channel
+    cmp_burst_ctrl_lg :  conv_dyn_burst_ctrl
+    generic map
+    (
+        g_pwidth 					=> g_pgen_pwidth_lg, 
+        g_temp_decre_step			=> g_temp_decre_step_lg,
+        g_1_pulse_temp_rise 		=> g_burstctrl_1_pulse_temp_rise_lg,   
+        g_max_temp  				=> g_burstctrl_max_temp_lg_sh
+    )
+    port map
+    (
+        clk_i        		=> clk_20_i,
+        rst_n_i      		=> rst_20_n,
+        en_i         	 	=> '1',
+        pulse_burst_i 		=> pulse_outp_lg(i),
+        pulse_r_edge_p_i	=> pulse_r_edge_lg_p(i),
+        pulse_f_edge_p_i	=> pulse_f_edge_lg_p(i),
+        temp_rise_o			=> temp_rise_c_lg(i),
+        pulse_burst_o		=> burst_outp_lg(i),
+        burst_err_p_o 		=> burst_outp_err_lg_p(i)
+    );
+     ----------------------------------------------------------------------------------------------
+  -- Instantiate pulse generator + burst controller block for the channel for SHORT pulse operation
+  -------------------------------------------------------------------------------------------------
+  -- BURST MODE WITH SHORT PULSES
+  ----------------------------------
+  --Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
+ cmp_pulse_gen_sh : conv_pulse_gen
+    generic map
+    (
+      g_with_fixed_pwidth => g_pgen_fixed_width,
+      g_pwidth            => g_pgen_pwidth_sh,
+      g_pperiod           => g_pgen_pperiod_sh
+    )
+    port map
+    (
+      clk_i         => clk_20_i,
+      rst_n_i       => rst_20_n,
+      gf_en_n_i     => gf_en_n_i,
+      en_i          => '1',
+      trig_a_i      => trig_pgen(i),
+      trig_r_edge_p_i => trig_chan_redge_p(i),
+      trig_f_edge_p_i => trig_chan_fedge_p(i),
+      pulse_err_p_o => pulse_outp_err_sh_p (i),
+      pulse_o       => pulse_outp_sh(i),
+      pulse_r_edge_p_o       => pulse_r_edge_sh_p(i) ,
+      pulse_f_edge_p_o       => pulse_f_edge_sh_p(i)
+    );
+    ----------------------------------------------------------------------------------
+    -- Instantiate burst control block for the channel
+    cmp_burst_ctrl_sh :  conv_dyn_burst_ctrl
+    generic map
+    (
+        g_pwidth 					=> g_pgen_pwidth_sh, 
+        g_temp_decre_step			=> g_temp_decre_step_sh,
+        g_1_pulse_temp_rise 		=> g_burstctrl_1_pulse_temp_rise_sh,   
+        g_max_temp  				=> g_burstctrl_max_temp_lg_sh
+    )
+    port map
+    (
+        clk_i        		=> clk_20_i,
+        rst_n_i      		=> rst_20_n,
+        en_i         	 	=> '1',
+        pulse_burst_i 		=> pulse_outp_sh(i),
+        pulse_r_edge_p_i	=> pulse_r_edge_sh_p(i),
+        pulse_f_edge_p_i	=> pulse_f_edge_sh_p(i),
+        temp_rise_o			=> temp_rise_c_sh(i),
+        pulse_burst_o		=> burst_outp_sh(i),
+        burst_err_p_o 		=> burst_outp_err_sh_p(i)	
+    );
+    ----------------------------------------------------------------------
+    --Select output depending on mode of operation.
+    ----------------------------------------------------------------------
+    pulse_outp (i) <= (burst_outp_lg(i) and pulse_width_sel_n_i) or
+                    (burst_outp_sh(i) and not pulse_width_sel_n_i) 
+                    when burst_en_n = '0'
+                    else pulse_outp_cont(i);
+    ----------------------------------------------------------------------
+    --Generate error pulses depending on mode of operation
+    ----------------------------------------------------------------------
+    -- flim_pmisse_p gives out a pulse when a pulse is missed because its
+    -- frequency is above the set maximum frequency
+    flim_pmisse_p (i) <= (pulse_outp_err_lg_p(i) and pulse_width_sel_n_i) or
+                    (pulse_outp_err_sh_p(i) and not pulse_width_sel_n_i) 
+                    when burst_en_n = '0'
+                    else pulse_outp_err_cont(i) ;
+    -- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the 
+    -- frequency watchdog only supports a high frequency for a limited period
+    fwdg_pmisse_p (i) <= (burst_outp_err_lg_p(i) and pulse_width_sel_n_i) or
+                    (burst_outp_err_sh_p(i) and not pulse_width_sel_n_i) 
+                    when burst_en_n = '0'
+                    else '0'  ;
+    pmisse_p (i)	<= flim_pmisse_p (i) or fwdg_pmisse_p (i);
+    -----------------------------------------------------------------------
  -- Process to flash pulse LED when a pulse is output
  -- LED flash length: 26 ms
  p_pulse_led : process (clk_20_i) is
@@ -628,10 +971,47 @@ end generate gen_pulse_cnt;
  end process p_pulse_led;
 end generate gen_pulse_chan_logic;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
+  -- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
+  -- LED flash length: 26 ms
+  gen_inv_ttl_leds : for i in 0 to g_nr_inv_chans-1 generate
+-- INV-TTL outputs
+  inv_pulse_outp(i) <= inv_pulse_i_n(i);
+  inv_pulse_o(i) <= inv_pulse_outp(i);
+  p_inv_pulse_led : process (clk_20_i) is
+  begin
+    if rising_edge(clk_20_i) then
+      if (rst_20_n = '0') then
+        inv_pulse_outp_d0(i)      <= '0';
+        inv_pulse_outp_fedge_p(i) <= '0';
+        led_inv_pulse_cnt(i)   <= (others => '0');
+        led_inv_pulse(i)       <= '0';
+      else
+        inv_pulse_outp_d0(i)      <= inv_pulse_outp(i);
+        inv_pulse_outp_fedge_p(i) <= (not inv_pulse_outp(i)) and inv_pulse_outp_d0(i);
+        case led_inv_pulse(i) is
+          when '0' =>
+            if (inv_pulse_outp_fedge_p(i) = '1') then
+              led_inv_pulse(i) <= '1';
+            end if;
+          when '1' =>
+            led_inv_pulse_cnt(i) <= led_inv_pulse_cnt(i) + 1;
+            if (led_inv_pulse_cnt(i) = (led_inv_pulse_cnt(i)'range => '1')) then
+              led_inv_pulse(i) <= '0';
+            end if;
+          when others =>
+            led_inv_pulse(i) <= '0';
+        end case;
+      end if;
+    end if;
+  end process p_inv_pulse_led;
+end generate gen_inv_ttl_leds;
 --------------------------------------------------------------------------------
 gen_pulse_timetag : if (g_with_pulse_timetag = true) generate
  cmp_pulse_timetag : conv_pulse_timetag
@@ -721,6 +1101,7 @@ end generate gen_pulse_timetag;
  -- Channel output assignments
  pulse_o     <= pulse_outp;
  led_pulse_o <= led_pulse;
+  led_inv_pulse_o <= led_inv_pulse;
  --============================================================================
  -- I2C bridge logic
@@ -934,22 +1315,36 @@ end generate gen_line_unused_chans;
    end if;
  end process p_rst_fr_reg;
-  -- Register for the PMISSE bits in the SR, set when a channel misses a pulse
+  -- Register for the PMISSE bits in the ERR, set when a channel misses a pulse
  -- Each bit is cleared by writing a '1' to it
-  p_sr_pmisse_bit : process (clk_20_i)
+  p_err_pmisse_bit : process (clk_20_i)
  begin
    if rising_edge(clk_20_i) then
      for i in 0 to g_nr_chans-1 loop
        if (rst_20_n = '0') then
+          flim_pmisse_bit(i) <= '0';
+          fwdg_pmisse_bit (i)<= '0';
          pmisse_bit(i) <= '0';
        elsif (pmisse_p(i) = '1') then
-          pmisse_bit(i) <= '1';
+          if flim_pmisse_p (i) = '1' then
-        elsif (pmisse_bit_rst_ld = '1') and (pmisse_bit_rst(i) = '1') then
+            flim_pmisse_bit(i)<= '1';
-          pmisse_bit(i) <= '0';
+          end if;
+          if fwdg_pmisse_p (i) = '1' then
+            fwdg_pmisse_bit(i) <= '1';
+          end if;
+        else 
+            if (flim_pmisse_bit_rst_ld = '1') and (flim_pmisse_bit_rst(i) = '1') then
+                flim_pmisse_bit(i) <= '0';
+            end if;
+            if (fwdg_pmisse_bit_rst_ld = '1') and (fwdg_pmisse_bit_rst(i) = '1') then
+                fwdg_pmisse_bit(i) <= '0';
            end if;
+        end if;
+      pmisse_bit(i) <= flim_pmisse_bit(i) or fwdg_pmisse_bit(i);
      end loop;
    end if;
-  end process p_sr_pmisse_bit;
+  end process p_err_pmisse_bit;
  -- Create an OR of all PMISSE bits
  pmisse_bits_or <= '0' when (pmisse_bit = (pmisse_bit'range => '0')) else
@@ -1088,16 +1483,21 @@ end generate gen_latest_timestamp_unused_chans;
      reg_sr_gwvers_i          => g_gwvers,
      reg_sr_switches_i        => sw_gp_i,
      reg_sr_rtm_i             => rtm_lines,
-      reg_sr_i2c_wdto_o        => i2c_wdto_bit_rst,
+      reg_sr_hwvers_i		   => hwvers_i,
-      reg_sr_i2c_wdto_i        => i2c_wdto_bit,
-      reg_sr_i2c_wdto_load_o   => i2c_wdto_bit_rst_ld,
      reg_sr_wrpres_i          => wrpres,  
-      reg_sr_i2c_err_o         => i2c_err_bit_rst,
-      reg_sr_i2c_err_i         => i2c_err_bit,
+      reg_err_i2c_wdto_o        => i2c_wdto_bit_rst,
-      reg_sr_i2c_err_load_o    => i2c_err_bit_rst_ld,
+      reg_err_i2c_wdto_i        => i2c_wdto_bit,
-      reg_sr_pmisse_o          => pmisse_bit_rst,
+      reg_err_i2c_wdto_load_o   => i2c_wdto_bit_rst_ld,
-      reg_sr_pmisse_i          => pmisse_bit,
+      reg_err_i2c_err_o         => i2c_err_bit_rst,
-      reg_sr_pmisse_load_o     => pmisse_bit_rst_ld,
+      reg_err_i2c_err_i         => i2c_err_bit,
+      reg_err_i2c_err_load_o    => i2c_err_bit_rst_ld,  
+      reg_err_flim_pmisse_o          => flim_pmisse_bit_rst,
+      reg_err_flim_pmisse_i          => flim_pmisse_bit,
+      reg_err_flim_pmisse_load_o     => flim_pmisse_bit_rst_ld, 
+      reg_err_fwdg_pmisse_o          => fwdg_pmisse_bit_rst,
+      reg_err_fwdg_pmisse_i          => fwdg_pmisse_bit,
+      reg_err_fwdg_pmisse_load_o     => fwdg_pmisse_bit_rst_ld,
      reg_cr_rst_unlock_o      => rst_unlock_bit,
      reg_cr_rst_unlock_i      => rst_unlock,
@@ -1108,24 +1508,43 @@ end generate gen_latest_timestamp_unused_chans;
      reg_cr_mpt_o             => mpt,
      reg_cr_mpt_wr_o          => mpt_ld,
-      reg_ch1pcr_o             => ch_pcr(0),
+      reg_ch1ttlpcr_o             => ch_ttl_pcr(0),
-      reg_ch1pcr_i             => std_logic_vector(pulse_cnt(0)),
+      reg_ch1ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(0)),
-      reg_ch1pcr_load_o        => ch_pcr_ld(0),
+      reg_ch1ttlpcr_load_o        => ch_ttl_pcr_ld(0),
-      reg_ch2pcr_o             => ch_pcr(1),
+      reg_ch2ttlpcr_o             => ch_ttl_pcr(1),
-      reg_ch2pcr_i             => std_logic_vector(pulse_cnt(1)),
+      reg_ch2ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(1)),
-      reg_ch2pcr_load_o        => ch_pcr_ld(1),
+      reg_ch2ttlpcr_load_o        => ch_ttl_pcr_ld(1),
-      reg_ch3pcr_o             => ch_pcr(2),
+      reg_ch3ttlpcr_o             => ch_ttl_pcr(2),
-      reg_ch3pcr_i             => std_logic_vector(pulse_cnt(2)),
+      reg_ch3ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(2)),
-      reg_ch3pcr_load_o        => ch_pcr_ld(2),
+      reg_ch3ttlpcr_load_o        => ch_ttl_pcr_ld(2),
-      reg_ch4pcr_o             => ch_pcr(3),
+      reg_ch4ttlpcr_o             => ch_ttl_pcr(3),
-      reg_ch4pcr_i             => std_logic_vector(pulse_cnt(3)),
+      reg_ch4ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(3)),
-      reg_ch4pcr_load_o        => ch_pcr_ld(3),
+      reg_ch4ttlpcr_load_o        => ch_ttl_pcr_ld(3),
-      reg_ch5pcr_o             => ch_pcr(4),
+      reg_ch5ttlpcr_o             => ch_ttl_pcr(4),
-      reg_ch5pcr_i             => std_logic_vector(pulse_cnt(4)),
+      reg_ch5ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(4)),
-      reg_ch5pcr_load_o        => ch_pcr_ld(4),
+      reg_ch5ttlpcr_load_o        => ch_ttl_pcr_ld(4),
-      reg_ch6pcr_o             => ch_pcr(5),
+      reg_ch6ttlpcr_o             => ch_ttl_pcr(5),
-      reg_ch6pcr_i             => std_logic_vector(pulse_cnt(5)),
+      reg_ch6ttlpcr_i             => std_logic_vector(ttl_pulse_cnt(5)),
-      reg_ch6pcr_load_o        => ch_pcr_ld(5),
+      reg_ch6ttlpcr_load_o        => ch_ttl_pcr_ld(5),
+      reg_ch1blopcr_o             => ch_blo_pcr(0),
+      reg_ch1blopcr_i             => std_logic_vector(blo_pulse_cnt(0)),
+      reg_ch1blopcr_load_o        => ch_blo_pcr_ld(0),
+      reg_ch2blopcr_o             => ch_blo_pcr(1),
+      reg_ch2blopcr_i             => std_logic_vector(blo_pulse_cnt(1)),
+      reg_ch2blopcr_load_o        => ch_blo_pcr_ld(1),
+      reg_ch3blopcr_o             => ch_blo_pcr(2),
+      reg_ch3blopcr_i             => std_logic_vector(blo_pulse_cnt(2)),
+      reg_ch3blopcr_load_o        => ch_blo_pcr_ld(2),
+      reg_ch4blopcr_o             => ch_blo_pcr(3),
+      reg_ch4blopcr_i             => std_logic_vector(blo_pulse_cnt(3)),
+      reg_ch4blopcr_load_o        => ch_blo_pcr_ld(3),
+      reg_ch5blopcr_o             => ch_blo_pcr(4),
+      reg_ch5blopcr_i             => std_logic_vector(blo_pulse_cnt(4)),
+      reg_ch5blopcr_load_o        => ch_blo_pcr_ld(4),
+      reg_ch6blopcr_o             => ch_blo_pcr(5),
+      reg_ch6blopcr_i             => std_logic_vector(blo_pulse_cnt(5)),
+      reg_ch6blopcr_load_o        => ch_blo_pcr_ld(5),
      reg_tvlr_o               => tvlr,
      reg_tvlr_i               => tm_tai(31 downto 0),
@@ -1179,7 +1598,12 @@ end generate gen_latest_timestamp_unused_chans;
      reg_lsr_frontinvfs_i     => line_inv_fs_i,
      reg_lsr_rearfs_i         => line_rear_fs,
-      reg_oswr_switches_i      => sw_other_i
+      reg_oswr_switches_i      => sw_other_i,
+      reg_uidlr_i    => id (31 downto 0),
+      reg_uidhr_i    => id (63 downto 32),
+      reg_tempr_i      => temper
    );
  --============================================================================
@@ -1205,50 +1629,49 @@ end generate gen_latest_timestamp_unused_chans;
 gen_thermometer : if (g_with_thermometer = true) generate
  -- The one-wire master component is used to control the on-board DS18B20
  -- thermometer
-  cmp_onewire_master : wb_onewire_master
-    generic map
+  cmp_onewire: gc_ds182x_interface
-    (
+  generic map (freq => 20)
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => WORD,
-      g_num_ports           => 1,
-      g_ow_btp_normal       => "5.0",
-      g_ow_btp_overdrive    => "1.0"
-    )
  port map
-    (
+    (clk_i     => clk_20_i,
-      clk_sys_i   => clk_20_i,
     rst_n_i   => rst_20_n,
+     pps_p_i   => pps_is_zero,
-      wb_cyc_i    => xbar_master_out(c_slv_onewire_mst).cyc,
+     onewire_b => thermometer_b,
-      wb_sel_i    => xbar_master_out(c_slv_onewire_mst).sel,
+     id_o      => tmp_id,
-      wb_stb_i    => xbar_master_out(c_slv_onewire_mst).stb,
+     temper_o  => tmp_temper,
-      wb_we_i     => xbar_master_out(c_slv_onewire_mst).we,
+     id_read_o => onewire_read_p,
-      wb_adr_i    => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
+     id_ok_o   => open
-      wb_dat_i    => xbar_master_out(c_slv_onewire_mst).dat,
-      wb_dat_o    => xbar_master_in(c_slv_onewire_mst).dat,
-      wb_ack_o    => xbar_master_in(c_slv_onewire_mst).ack,
-      wb_int_o    => open,
-      wb_stall_o  => xbar_master_in(c_slv_onewire_mst).stall,
-      owr_pwren_o => open,
-      owr_en_o    => owr_en,
-      owr_i       => owr_in
     );
-  -- Generate tri-state buffer for thermometer
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  thermometer_b <= '0' when (owr_en(0) = '1') else
+  -- pps generator based on the 20 MHz clk
-                   'Z';
+  cmp_pps_gen: wf_decr_counter
-  owr_in(0) <= thermometer_b;
+  generic map(
-end generate gen_thermometer;
+  g_counter_lgth   => 25
--------------------------------------------------------------------------------
+  )
+  port map
--------------------------------------------------------------------------------
+    (uclk_i            => clk_20_i,
-gen_no_thermometer : if (g_with_thermometer = false) generate
+     counter_rst_i     => rst_20,
-  thermometer_b <= 'Z';
+     counter_decr_i    => '1',
-  xbar_master_in(c_slv_onewire_mst).ack <= '1';
+     counter_load_i    => pps_load_p,
-  xbar_master_in(c_slv_onewire_mst).stall <= '0';
+     counter_top_i     => "1001100010010110100000000", -- 20'000'000
-end generate gen_no_thermometer;
+     counter_is_zero_o => pps_is_zero);
--------------------------------------------------------------------------------
+  --  --  --  --  --  --  --  --  --  --  --
+  pps_load_p <= pps_is_zero; -- looping
+  rst_20 <= not rst_20_n;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  -- registering of the read values
+  reg_reading: process(clk_20_i)
+  begin
+    if rising_edge(clk_20_i) then
+      temper   <= (others => '0');
+      id       <= (others => '0');
+      if(onewire_read_p = '1') then
+        temper <= tmp_temper;
+        id     <= tmp_id;
+      end if;
+    end if;
+  end process;
  --============================================================================
  -- Bicolor LED matrix logic
@@ -1289,10 +1712,13 @@ end generate gen_no_thermometer;
  -- SFP lines all open-drain, set to high-impedance
  sfp_rate_select_o <= 'Z';
-  sfp_mod_def1_b    <= 'Z';
+  sfp_sda_b    <= 'Z';
-  sfp_mod_def2_b    <= 'Z';
+  sfp_scl_i    <= 'Z';
  sfp_tx_disable_o  <= 'Z';
 end architecture arch;
 --==============================================================================
 --  architecture end

--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -30,6 +30,9 @@
 --==============================================================================
 -- last changes:
 --    2014-08-01   Theodor Stana     File created
+--	  2016-11      Denia Bouhired	Added component for dynamic burst control module
+--    2016-12-20   Denia Bouhired	Modified port list of conv_regs
+--	  2017-01-23   Denia Bouhired	Modified conv_common_gw, added array type for thermal model
 --==============================================================================
 -- TODO: -
 --==============================================================================
@@ -52,6 +55,12 @@ package conv_common_gw_pkg is
  -- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
  -- _reimplement_ the conv_regs module
  constant c_max_nr_chans : natural := 6;
+  --============================================================================
+  --Type declarations
+   --============================================================================
+    --Array of constants for temperature model implemented for short pulse mode
+  type t_temp_decre_step is array (0 to 15) of integer; 
  --============================================================================
  -- Component declarations
@@ -64,7 +73,7 @@ package conv_common_gw_pkg is
    (
      -- Number of repeater channels
      g_nr_chans            : integer := 6;
+	  g_nr_inv_chans        : integer := 4;
      -- Board ID -- 4-letter ASCII string indicating the board ID
      -- see [1] for example
      g_board_id            : std_logic_vector(31 downto 0);
@@ -74,13 +83,28 @@ package conv_common_gw_pkg is
      -- Generate pulse repetition logic with fixed output pulse width
      g_pgen_fixed_width    : boolean;
      -- Pulse width at pulse generator output (valid with fixed output pulse width)
-      g_pgen_pwidth         : natural := 24;
-      -- Duty cycle divider ratio for pulse generator
+      g_pgen_pwidth_lg        : natural range 2 to 40 := 24; --**DB: was 20 to 40
-      -- output pulse will be limited to 1/g_pgen_duty_cycle_div
+      g_pgen_pwidth_sh         : natural range 2 to 40 := 5; 
-      g_pgen_duty_cycle_div : natural := 5;
+      -- output pulse will be limited to pulse period
+	  g_pgen_pperiod_cont 	: natural range 2 to 5000 := 4800; --For continuous mode operation max freq 4.12kHz
+      g_pgen_pperiod_lg  : natural range 6 to 300 := 191; --for LONG pulses changes maximum 
+      g_pgen_pperiod_sh  : natural range 2 to 300 := 9;	--for SHORT pulses changes maximum 
      -- Pulse generator glitch filter length in number of clk_20_i cycles
      g_pgen_gf_len         : integer := 4;
+	 -- Burst-mode-specific generics:
+	  g_temp_decre_step_lg		: t_temp_decre_step :=(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
+	  g_temp_decre_step_sh		: t_temp_decre_step :=(0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
+	-- Temperature rise resulting from 250ns pulse
+	  g_burstctrl_1_pulse_temp_rise_lg			:in unsigned (19 downto 0) := x"17700";   -- Check every "g_eval_burst_len" pulses
+	  g_burstctrl_1_pulse_temp_rise_sh			:in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses 
+	-- Maximum temperature allowed (scaled)
+	  g_burstctrl_max_temp_lg_sh			:in unsigned (39 downto 0) := x"02540BE400"; 
      -- Generate logic with pulse counters
      g_with_pulse_cnt       : boolean := false;
@@ -111,6 +135,11 @@ package conv_common_gw_pkg is
      -- Glitch filter active-low enable signal
      gf_en_n_i               : in  std_logic;
+	  -- Burst mode enable signal. Mode disabled for all versions of board
+	  burst_en_n_i			: in std_logic;
+	  -- Pulse width selection, port low means 250ns, high means 1.2us.		
+	  pulse_width_sel_n_i	: in std_logic;            
      -- Channel enable
      global_ch_oen_o         : out std_logic;
      pulse_front_oen_o       : out std_logic;
@@ -119,11 +148,17 @@ package conv_common_gw_pkg is
      -- Pulse inputs
      pulse_i                 : in  std_logic_vector(g_nr_chans-1 downto 0);
+      pulse_front_i             : in  std_logic_vector(g_nr_chans-1 downto 0);
+      pulse_rear_i             : in  std_logic_vector(g_nr_chans-1 downto 0);
      pulse_o                 : out std_logic_vector(g_nr_chans-1 downto 0);
      -- Channel leds
      -- 26 ms active-high pulse on pulse_o rising edge
+      inv_pulse_i_n			: in  std_logic_vector(g_nr_inv_chans-1 downto 0);
+      inv_pulse_o				: out  std_logic_vector(g_nr_inv_chans-1 downto 0);
      led_pulse_o             : out std_logic_vector(g_nr_chans-1 downto 0);
+      led_inv_pulse_o         : out std_logic_vector(g_nr_inv_chans-1 downto 0);
      -- I2C interface
      scl_i                   : in  std_logic;
@@ -161,10 +196,10 @@ package conv_common_gw_pkg is
      -- SFP lines
      sfp_los_i               : in    std_logic;
-      sfp_mod_def0_i          : in    std_logic;
+      sfp_present_i           : in    std_logic;
      sfp_rate_select_o       : out   std_logic;
-      sfp_mod_def1_b          : inout std_logic;
+      sfp_sda_b               : inout std_logic;
-      sfp_mod_def2_b          : inout std_logic;
+      sfp_scl_i               : inout std_logic;
      sfp_tx_disable_o        : out   std_logic;
      sfp_tx_fault_i          : in    std_logic;
@@ -172,6 +207,9 @@ package conv_common_gw_pkg is
      sw_gp_i                 : in  std_logic_vector(7 downto 0);
      sw_other_i              : in  std_logic_vector(31 downto 0);
+    -- PCB Version information
+      hwvers_i                : in std_logic_vector (5 downto 0);
      -- RTM lines
      rtmm_i                  : in  std_logic_vector(2 downto 0);
      rtmp_i                  : in  std_logic_vector(2 downto 0);
@@ -218,6 +256,19 @@ package conv_common_gw_pkg is
    );
  end component conv_reset_gen;
+  ------------------------------------------------------------------------------
+  -- Pulse counter - Used for scenarios where clocks are shorter than the time it takes to synchronise them (Normally it taked 3 clk cycles to synchronise trigger edge.)
+  ------------------------------------------------------------------------------  
+  component fastevent_counter is
+  port (sysclk_i   : in std_logic;
+        rstcount_i : in std_logic;
+        en_i       : in std_logic;
+        trig_i     : in std_logic;
+        count_o    : out std_logic_vector(31 downto 0);
+        count_int_o: out unsigned(31 downto 0));
+  end component;
  ------------------------------------------------------------------------------
  -- Pulse generator with optional configurable pulse width
  ------------------------------------------------------------------------------
@@ -231,10 +282,10 @@ package conv_common_gw_pkg is
      -- Default pulse width (20 MHz clock): 1.2 us
      -- Minimum allowable pulse width (20 MHz clock): 1 us
      -- Maximum allowable pulse width (20 MHz clock): 2 us
-      g_pwidth : natural range 20 to 40 := 24;
+      g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40
-      -- Duty cycle divider: D = 1/g_duty_cycle_div
+          -- Pulse period in unit of clock cycles
-      g_duty_cycle_div : natural := 5
+      g_pperiod : natural := 5
    );
    port
    (
@@ -253,6 +304,9 @@ package conv_common_gw_pkg is
      -- Trigger input, has to be '1' to assure pulse output with delay no greater
      -- than internal gate delays.
      trig_a_i      : in  std_logic;
+      trig_r_edge_p_i       : in std_logic; --synced 1 cycle-long r edge output
+      trig_f_edge_p_i       : in std_logic; --synced 1 cycle-long f edge output
      -- Pulse error output, pulses high for one clock cycle when a pulse arrives
      -- within a pulse period
@@ -262,11 +316,55 @@ package conv_common_gw_pkg is
      -- latency:
      --    glitch filter disabled: none
      --    glitch filter enabled: glitch filter length + 5 clk_i cycles
-      pulse_o       : out std_logic
+      pulse_o       : out std_logic;
+      pulse_r_edge_p_o       : out std_logic; --synced 1 cycle-long r edge output
+      pulse_f_edge_p_o       : out std_logic
    );
  end component conv_pulse_gen;
    ------------------------------------------------------------------------------
+  -- Controller for burst mode operation with configurable maximum pulse burst length and timeout
+  ------------------------------------------------------------------------------
+  component conv_dyn_burst_ctrl is
+	generic
+	(
+	-- Short pulse width, in number of clk_i cycles
+    -- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
+		g_pwidth : natural range 2 to 40 	:= 5; 
+	-- Thermal model constants, depend on mode selected short or long.
+		g_temp_decre_step : t_temp_decre_step;
+	-- Temperature rise resulting from with 250ns pulse
+		g_1_pulse_temp_rise			:in unsigned (19 downto 0);   -- Check every "g_eval_burst_len" pulses
+	-- Maximum temperature allowed (scaled)
+		g_max_temp			:in unsigned (39 downto 0) := x"174876E800" 
+	);
+	port
+	(
+    -- Clock and active-low reset inputs
+    clk_i        	: in  std_logic;
+    rst_n_i      	: in  std_logic;
+	-- Enable input, pulse generation is enabled when '1'
+    en_i         	 	: in  std_logic;
+	pulse_burst_i 		: in std_logic;
+	pulse_r_edge_p_i	: in std_logic;
+	pulse_f_edge_p_i	: in std_logic;
+	-- Temp_rise is output for external probing
+	temp_rise_o			: out unsigned (39 downto 0) ;
+	-- Dynamic temperature-controlled ouput pulse train.
+	pulse_burst_o		: out std_logic;
+	-- Burst error output, pulses high for one clock cycle when a pulse arrives
+    -- within a burst rejection phase
+    burst_err_p_o : out std_logic	
+	);
+  end component conv_dyn_burst_ctrl;
+  ------------------------------------------------------------------------------
  -- Converter board control registers
  ------------------------------------------------------------------------------
  component conv_regs is
@@ -282,157 +380,192 @@ package conv_common_gw_pkg is
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-  -- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
+-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
    reg_bidr_i                               : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
+-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
    reg_sr_gwvers_i                          : in     std_logic_vector(7 downto 0);
-  -- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
+-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
    reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-  -- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
+-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
    reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-  -- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
+-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
-      reg_sr_i2c_wdto_o                        : out    std_logic;
+    reg_sr_hwvers_i                          : in     std_logic_vector(5 downto 0);
-      reg_sr_i2c_wdto_i                        : in     std_logic;
+-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
-      reg_sr_i2c_wdto_load_o                   : out    std_logic;
-  -- Port for BIT field: 'White Rabbit present' in reg: 'SR'
    reg_sr_wrpres_i                          : in     std_logic;
-  -- Ports for BIT field: 'I2C communication error' in reg: 'SR'
+-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
-      reg_sr_i2c_err_o                         : out    std_logic;
+    reg_err_i2c_wdto_o                       : out    std_logic;
-      reg_sr_i2c_err_i                         : in     std_logic;
+    reg_err_i2c_wdto_i                       : in     std_logic;
-      reg_sr_i2c_err_load_o                    : out    std_logic;
+    reg_err_i2c_wdto_load_o                  : out    std_logic;
-  -- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
+-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
-      reg_sr_pmisse_o                          : out    std_logic_vector(5 downto 0);
+    reg_err_i2c_err_o                        : out    std_logic;
-      reg_sr_pmisse_i                          : in     std_logic_vector(5 downto 0);
+    reg_err_i2c_err_i                        : in     std_logic;
-      reg_sr_pmisse_load_o                     : out    std_logic;
+    reg_err_i2c_err_load_o                   : out    std_logic;
-  -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
+-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
+    reg_err_flim_pmisse_o                    : out    std_logic_vector(5 downto 0);
+    reg_err_flim_pmisse_i                    : in     std_logic_vector(5 downto 0);
+    reg_err_flim_pmisse_load_o               : out    std_logic;
+-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
+    reg_err_fwdg_pmisse_o                    : out    std_logic_vector(5 downto 0);
+    reg_err_fwdg_pmisse_i                    : in     std_logic_vector(5 downto 0);
+    reg_err_fwdg_pmisse_load_o               : out    std_logic;
+-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
    reg_cr_rst_unlock_o                      : out    std_logic;
    reg_cr_rst_unlock_i                      : in     std_logic;
    reg_cr_rst_unlock_load_o                 : out    std_logic;
-  -- Ports for BIT field: 'Reset bit' in reg: 'CR'
+-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
    reg_cr_rst_o                             : out    std_logic;
    reg_cr_rst_i                             : in     std_logic;
    reg_cr_rst_load_o                        : out    std_logic;
-  -- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
+-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
    reg_cr_mpt_o                             : out    std_logic_vector(7 downto 0);
    reg_cr_mpt_wr_o                          : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH1TTLPCR'
-      reg_ch1pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch1ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch1pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch1ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch1pcr_load_o                        : out    std_logic;
+    reg_ch1ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH2TTLPCR'
-      reg_ch2pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch2ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch2pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch2ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch2pcr_load_o                        : out    std_logic;
+    reg_ch2ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH3TTLPCR'
-      reg_ch3pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch3ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch3pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch3ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch3pcr_load_o                        : out    std_logic;
+    reg_ch3ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH4TTLPCR'
-      reg_ch4pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch4ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch4pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch4ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch4pcr_load_o                        : out    std_logic;
+    reg_ch4ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH5TTLPCR'
-      reg_ch5pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch5ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch5pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch5ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch5pcr_load_o                        : out    std_logic;
+    reg_ch5ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
+-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR'
-      reg_ch6pcr_o                             : out    std_logic_vector(31 downto 0);
+    reg_ch6ttlpcr_o                          : out    std_logic_vector(31 downto 0);
-      reg_ch6pcr_i                             : in     std_logic_vector(31 downto 0);
+    reg_ch6ttlpcr_i                          : in     std_logic_vector(31 downto 0);
-      reg_ch6pcr_load_o                        : out    std_logic;
+    reg_ch6ttlpcr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR'
+    reg_ch1blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch1blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch1blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH2BLOPCR'
+    reg_ch2blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch2blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch2blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH3BLOPCR'
+    reg_ch3blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch3blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch3blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH4BLOPCR'
+    reg_ch4blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch4blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch4blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH5BLOPCR'
+    reg_ch5blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch5blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch5blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH6BLOPCR'
+    reg_ch6blopcr_o                          : out    std_logic_vector(31 downto 0);
+    reg_ch6blopcr_i                          : in     std_logic_vector(31 downto 0);
+    reg_ch6blopcr_load_o                     : out    std_logic;
+-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
    reg_tvlr_o                               : out    std_logic_vector(31 downto 0);
    reg_tvlr_i                               : in     std_logic_vector(31 downto 0);
    reg_tvlr_load_o                          : out    std_logic;
-  -- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
+-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
    reg_tvhr_o                               : out    std_logic_vector(7 downto 0);
    reg_tvhr_i                               : in     std_logic_vector(7 downto 0);
    reg_tvhr_load_o                          : out    std_logic;
-  -- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
+-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
    reg_tbmr_chan_i                          : in     std_logic_vector(5 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
-      reg_tbmr_wrtag_i                         : in     std_logic;
-  -- Tag buffer read request, asserted when reading from TBMR
    reg_tb_rd_req_p_o                        : out    std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
+    reg_tbmr_wrtag_i                         : in     std_logic;
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
    reg_tbcyr_i                              : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
    reg_tbtlr_i                              : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
    reg_tbthr_i                              : in     std_logic_vector(7 downto 0);
-  -- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
+-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
    reg_tbcsr_usedw_i                        : in     std_logic_vector(6 downto 0);
-  -- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
+-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
    reg_tbcsr_full_i                         : in     std_logic;
-  -- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
+-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
    reg_tbcsr_empty_i                        : in     std_logic;
-  -- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
+-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
    reg_tbcsr_clr_o                          : out    std_logic;
    reg_tbcsr_clr_i                          : in     std_logic;
    reg_tbcsr_clr_load_o                     : out    std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
    reg_ch1ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
    reg_ch1ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
    reg_ch1ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
    reg_ch1ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
    reg_ch2ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
    reg_ch2ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
    reg_ch2ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
    reg_ch2ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
    reg_ch3ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
    reg_ch3ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
    reg_ch3ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
    reg_ch3ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
    reg_ch4ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
    reg_ch4ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
    reg_ch4ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
    reg_ch4ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
    reg_ch5ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
    reg_ch5ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
    reg_ch5ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
    reg_ch5ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
+-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
    reg_ch6ltscyr_i                          : in     std_logic_vector(27 downto 0);
-  -- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
+-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
    reg_ch6ltstlr_i                          : in     std_logic_vector(31 downto 0);
-  -- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
+-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
    reg_ch6ltsthr_tai_i                      : in     std_logic_vector(7 downto 0);
-  -- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
+-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
    reg_ch6ltsthr_wrtag_i                    : in     std_logic;
-  -- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
    reg_lsr_front_i                          : in     std_logic_vector(5 downto 0);
-  -- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
    reg_lsr_frontinv_i                       : in     std_logic_vector(3 downto 0);
-  -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
    reg_lsr_rear_i                           : in     std_logic_vector(5 downto 0);
-  -- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
    reg_lsr_frontfs_i                        : in     std_logic_vector(5 downto 0);
-  -- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
    reg_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
-  -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
+-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
    reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
-  -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
+-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
-      reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0)
+    reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
+    reg_uidlr_i                              : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
+    reg_uidhr_i                              : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
+    reg_tempr_i                              : in     std_logic_vector(15 downto 0)
    );
-  end component conv_regs;
+end component conv_regs;
  -- Converter board registers SDB definition
  constant c_conv_regs_sdb : t_sdb_device := (
@@ -552,5 +685,52 @@ package conv_common_gw_pkg is
    );
  end component conv_man_trig;
+  ------------------------------------------------------------------------------
+  -- PPS trigger for one-wire master
+  ------------------------------------------------------------------------------
+component wf_decr_counter is
+  generic(g_counter_lgth : natural := 4);                         -- default length
+  port(
+  -- INPUTS
+    -- nanoFIP User Interface general signal
+    uclk_i            : in std_logic;                             -- 40 MHz clock
+    -- Signal from the wf_reset_unit
+    counter_rst_i     : in std_logic;                             -- resets counter to all '1'
+    -- Signals from any unit
+    counter_decr_i    : in std_logic;                             -- decrement enable
+    counter_load_i    : in std_logic;                             -- load enable; loads counter to counter_top_i
+    counter_top_i     : in unsigned (g_counter_lgth-1 downto 0);  -- load value
+  -- OUTPUTS
+    -- Signal to any unit
+    counter_o         : out unsigned (g_counter_lgth-1 downto 0); -- counter
+    counter_is_zero_o : out std_logic);                           -- empty counter indication
+end component wf_decr_counter;
+  ------------------------------------------------------------------------------
+  -- CHIPSCOPE COMPONENTS
+  ------------------------------------------------------------------------------
+  component chipscope_ila IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0));
+END component chipscope_ila;
+component chipscope_icon IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0));
+END component chipscope_icon;
 end package conv_common_gw_pkg;
+-----------------------------------------------------------------------------------