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Converter Common Gateware
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Converter Common Gateware
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3848a6c9
Commit
3848a6c9
authored
Feb 14, 2017
by
Denia Bouhired-Ferrag
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Fixed bug, where state machine cannot recover from REJECT state if no new pulses arrive
parent
c2306023
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13 additions
and
6 deletions
+13
-6
conv_dyn_burst_ctrl.vhd
modules/conv_dyn_burst_ctrl.vhd
+13
-6
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modules/conv_dyn_burst_ctrl.vhd
View file @
3848a6c9
...
...
@@ -93,6 +93,8 @@ entity conv_dyn_burst_ctrl is
pulse_r_edge_p_i
:
in
std_logic
;
pulse_f_edge_p_i
:
in
std_logic
;
-- Temp_rise is output for external probing
temp_rise_o
:
out
unsigned
(
39
downto
0
)
;
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o
:
out
std_logic
;
...
...
@@ -133,7 +135,7 @@ entity conv_dyn_burst_ctrl is
-- Output from module depends on burst_ctrl_rst and en_i
---------------------------------------------------------
pulse_burst_o
<=
'0'
when
burst_ctrl_rst
=
'1'
else
pulse_burst_i
and
en_i
;
temp_rise_o
<=
temp_rise
;
-----------------------------------------------------------------------------
-- Finite State Machine FSM
-----------------------------------------------------------------------------
...
...
@@ -191,7 +193,8 @@ entity conv_dyn_burst_ctrl is
-- i.e. temp_rise >= g_max_temp.
------------------------------------------------------------------------
when
PULSE_REJECT
=>
if
pulse_f_edge_p_i
=
'1'
and
temp_rise
<=
g_max_temp
then
if
(
pulse_f_edge_p_i
=
'1'
and
temp_rise
<=
g_max_temp
)
OR
temp_rise
=
0
then
nxt_state
<=
PULSE_REPEAT
;
else
nxt_state
<=
PULSE_REJECT
;
...
...
@@ -265,10 +268,10 @@ entity conv_dyn_burst_ctrl is
else
-- Reset counters in the event of a new pulse only
-- when pulse rejection is not active
if
(
pulse_r_edge_p_i
=
'1'
)
and
burst_ctrl_rst
=
'0'
then
if
(
pulse_r_edge_p_i
=
'1'
and
burst_ctrl_rst
=
'0'
)
then
--OR
--(pulse_f_edge_p_i = '1' and n_cycle_cnt /= 1) then
single_cycle_cnt
<=
1
;
n_cycle_cnt
<=
1
;
else
--count clk cycles
single_cycle_cnt
<=
single_cycle_cnt
+
1
;
...
...
@@ -305,7 +308,11 @@ entity conv_dyn_burst_ctrl is
end
if
;
end
if
;
elsif
s_pulse_reject
=
'1'
and
temp_rise
>
0
then
if
temp_rise
>=
g_temp_decre_step
(
n_cycle_cnt
-1
)
then
temp_rise
<=
temp_rise
-
to_unsigned
(
g_temp_decre_step
(
n_cycle_cnt
-1
),
40
);
else
temp_rise
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
if
;
...
...
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