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Converter Common Gateware
Commit 3e990133 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added I2C interface and moved pulse inhibit outside of common g/w

parent a04f0dc8
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modules/conv_pulse_gen.vhd
View file @ 3e990133
......@@ -174,10 +174,6 @@ architecture behav of conv_pulse_gen is
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
-- Inhibit first pulse
signal inhibit : std_logic;
signal inhibit_d0 : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
......@@ -189,33 +185,8 @@ architecture behav of conv_pulse_gen is
--==============================================================================
begin
-- Inhibit first pulse process
--
-- This process is needed since when in TTL-BAR repetition mode and when no
-- signal is present on the channel, the external _no signal detect_ block
-- allows a high level on the input line for 100 us. This high level on the
-- line will create a signal that might perturb the operation outside the
-- pulse repeater module, so the pulse generator has to be inhibited until
-- after reset.
p_inhibit_first_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
inhibit <= '1';
inhibit_d0 <= '1';
else
inhibit_d0 <= inhibit;
if (inhibit = '1') then
inhibit <= '0';
end if;
end if;
end if;
end process p_inhibit_first_pulse;
gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
-- Wait for inhibit delay to go LOW, preventing any signal on the line in
-- TTL-BAR
pulse_o <= trig_a_i and (not inhibit_d0);
pulse_o <= trig_a_i;
pulse_err_p_o <= '0';
end generate gen_without_fixed_pwidth;
......@@ -307,13 +278,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
state <= GEN_GF_OFF;
end if;
else
-- wait for inhibit delay to become LOW; this prevents a pulse
-- getting generated when the glitch filter is ON, since the
-- trigger delay above has a reset state of '0', and the high
-- level on the line until the _no signal detect_ block cuts the
-- signal on an unconnected input channel will generate a pulse
-- on the output
if (trig_gf_on_r_edge_p = '1') and (inhibit_d0 = '0') then
if (trig_gf_on_r_edge_p = '1') then
state <= GEN_GF_ON;
end if;
end if;
......
top/conv_common_gw.vhd
View file @ 3e990133
......@@ -19,9 +19,11 @@
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- [1] Board IDs for level conversion circuits
-- www.ohwr.org/projects/conv-common-gw/wiki/Board-id
-- [2] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
......@@ -60,6 +62,9 @@ entity conv_common_gw is
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id : std_logic_vector(31 downto 0);
-- Gateware version
g_gwvers : std_logic_vector(7 downto 0);
......@@ -103,6 +108,25 @@ entity conv_common_gw is
-- Channel leds
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- I2C LED -- conect to a bicolor LED of choice
led_i2c_o : out std_logic;
-- Switch inputs (for readout from converter status register)
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
......@@ -126,7 +150,7 @@ architecture arch of conv_common_gw is
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
constant c_nr_slaves : natural := 1;
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
......@@ -146,17 +170,17 @@ architecture arch of conv_common_gw is
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot,
c_slv_onewire_mst => c_addr_onewire_mst
c_slv_conv_regs => c_addr_conv_regs
--c_slv_multiboot => c_addr_multiboot,
--c_slv_onewire_mst => c_addr_onewire_mst
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot,
c_slv_onewire_mst => c_mask_onewire_mst
c_slv_conv_regs => c_mask_conv_regs
--c_slv_multiboot => c_mask_multiboot,
--c_slv_onewire_mst => c_mask_onewire_mst
);
......@@ -225,26 +249,179 @@ architecture arch of conv_common_gw is
);
end component conv_pulse_gen;
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic;
reg_sr_pmisse_i : in std_logic;
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic
);
end component conv_regs;
--============================================================================
-- Signal declarations
--============================================================================
-- Per-domain clock and reset signals
signal clk_125 : std_logic;
signal rst_125_n : std_logic;
signal rst_20_n : std_logic;
signal clk_125 : std_logic;
signal rst_125_n : std_logic;
signal rst_20_n : std_logic;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse_cnt : t_pulse_led_cnt;
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
-- I2C bridge signals
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal sw_gp : std_logic_vector(7 downto 0);
signal sw_multicast : std_logic_vector(3 downto 0);
signal rst_unlock : std_logic;
signal rst_unlock_bit : std_logic;
signal rst_unlock_bit_ld : std_logic;
signal rst_bit : std_logic;
signal rst_bit_ld : std_logic;
signal rst_fr_reg : std_logic;
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal pmisse_bit : std_logic;
signal pmisse_bit_rst : std_logic;
signal pmisse_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(5 downto 0);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
signal tvlr_ld : std_logic;
signal tvhr : std_logic_vector( 7 downto 0);
signal tvhr_ld : std_logic;
signal wrpres : std_logic;
signal i2c_err_bit : std_logic;
signal i2c_err_bit_rst : std_logic;
signal i2c_err_bit_rst_ld : std_logic;
-- LED signals
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse_cnt : t_pulse_led_cnt;
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_blink : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
--==============================================================================
-- architecture begin
......@@ -299,7 +476,7 @@ begin
port map
(
clk_i => clk_20_i,
rst_n_i => '1',
rst_n_i => rst_20_n,
data_i => trig_a(i),
synced_o => trig_synced(i)
);
......@@ -316,7 +493,7 @@ begin
port map
(
clk_i => clk_20_i,
rst_n_i => '1',
rst_n_i => rst_20_n,
dat_i => trig_synced(i),
dat_o => trig_degl(i)
);
......@@ -326,8 +503,7 @@ begin
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- The trigger to the pulse generator is multiplexed between manually triggered or
-- channel input
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i);
-- Instantiate pulse generator block for the channel
......@@ -390,6 +566,274 @@ begin
pulse_o <= pulse_outp;
led_pulse_o <= led_pulse;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [2]
i2c_addr <= "10" & vme_ga_i;
-- Instantiate I2C bridge component
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge : wb_i2c_bridge
generic map
(
g_fsm_wdt => 480000
)
port map
(
-- Clock, reset
clk_i => clk_20_i,
rst_n_i => rst_20_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
-- TIP and ERR outputs
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- And set the I2C LED Output
led_i2c_o <= led_i2c;
-- Register for the I2C_WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
i2c_wdto_bit <= '1';
elsif (i2c_wdto_bit_rst_ld = '1') and (i2c_wdto_bit_rst = '1') then
i2c_wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
-- Register for the I2C_ERR bit in the SR
p_i2c_err_led : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_err_bit <= '0';
elsif (i2c_err_p = '1') then
i2c_err_bit <= '1';
elsif (i2c_err_bit_rst_ld = '1') and (i2c_err_bit_rst = '1') then
i2c_err_bit <= '0';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- Make switches readout as '1' for ON, instead of '0'
sw_gp <= not sw_gp_n_i;
sw_multicast <= not sw_multicast_n_i;
-- Then, instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_20_n,
clk_sys_i => clk_20_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_bidr_i => g_board_id,
reg_sr_gwvers_i => g_gwvers,
reg_sr_switches_i => sw_gp,
reg_sr_rtm_i => (others => '0'),
reg_sr_i2c_wdto_o => i2c_wdto_bit_rst,
reg_sr_i2c_wdto_i => i2c_wdto_bit,
reg_sr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
reg_sr_wrpres_i => '0',
reg_sr_i2c_err_o => i2c_err_bit_rst,
reg_sr_i2c_err_i => i2c_err_bit,
reg_sr_i2c_err_load_o => i2c_err_bit_rst_ld,
reg_sr_pmisse_o => open,
reg_sr_pmisse_i => '0',
reg_sr_pmisse_load_o => open,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld,
reg_cr_mpt_o => open,
reg_cr_mpt_wr_o => open,
reg_ch1pcr_o => ch_pcr(0),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(0)),
reg_ch1pcr_load_o => ch_pcr_ld(0),
reg_ch2pcr_o => ch_pcr(1),
reg_ch2pcr_i => std_logic_vector(pulse_cnt(1)),
reg_ch2pcr_load_o => ch_pcr_ld(1),
reg_ch3pcr_o => ch_pcr(2),
reg_ch3pcr_i => std_logic_vector(pulse_cnt(2)),
reg_ch3pcr_load_o => ch_pcr_ld(2),
reg_ch4pcr_o => ch_pcr(3),
reg_ch4pcr_i => std_logic_vector(pulse_cnt(3)),
reg_ch4pcr_load_o => ch_pcr_ld(3),
reg_ch5pcr_o => ch_pcr(4),
reg_ch5pcr_i => std_logic_vector(pulse_cnt(4)),
reg_ch5pcr_load_o => ch_pcr_ld(4),
reg_ch6pcr_o => ch_pcr(5),
reg_ch6pcr_i => std_logic_vector(pulse_cnt(5)),
reg_ch6pcr_load_o => ch_pcr_ld(5),
reg_tvlr_o => open,
reg_tvlr_i => (others => '0'),
reg_tvlr_load_o => open,
reg_tvhr_o => open,
reg_tvhr_i => (others => '0'),
reg_tvhr_load_o => open,
reg_tbmr_chan_i => (others => '0'),
reg_tbmr_wrtag_i => '0',
reg_tb_rd_req_p_o => open,
reg_tbcyr_i => (others => '0'),
reg_tbtlr_i => (others => '0'),
reg_tbthr_i => (others => '0'),
reg_tbcsr_clr_o => open,
reg_tbcsr_clr_i => '0',
reg_tbcsr_clr_load_o => open,
reg_tbcsr_usedw_i => (others => '0'),
reg_tbcsr_full_i => '0',
reg_tbcsr_empty_i => '0'
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
else
rst_fr_reg <= '0';
end if;
end if;
end process p_rst_fr_reg;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
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