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Converter Common Gateware
Commits
89385741
Commit
89385741
authored
Jul 31, 2014
by
Theodor-Adrian Stana
Browse files
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Add xwb_xil_multiboot and registers for reading out line status and multicast switches
parent
3e990133
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4 changed files
with
1160 additions
and
74 deletions
+1160
-74
general-cores
ip_cores/general-cores
+1
-1
conv_regs.vhd
modules/conv_regs.vhd
+581
-21
conv_regs.wb
modules/conv_regs.wb
+376
-0
conv_common_gw.vhd
top/conv_common_gw.vhd
+202
-52
No files found.
general-cores
@
382b46c1
Subproject commit
97bc71975252b32cf8a47ba895f7010734f015e5
Subproject commit
382b46c19757e0c7c8574ebe56f32169c5a84b20
modules/conv_regs.vhd
View file @
89385741
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created :
Mon Apr 7 16:50:5
5 2014
-- Created :
Thu Jul 31 15:16:4
5 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
...
...
@@ -18,7 +18,7 @@ entity conv_regs is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -113,7 +113,53 @@ entity conv_regs is
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel TTL input state' in reg: 'LSR'
reg_lsr_front_ttl_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel TTL-BAR input state' in reg: 'LSR'
reg_lsr_front_invttl_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_fs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'State of MultiCast switches' in reg: 'MSWR'
reg_mswr_bit_i
:
in
std_logic_vector
(
3
downto
0
)
);
end
conv_regs
;
...
...
@@ -123,7 +169,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
5
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
...
...
@@ -205,14 +251,14 @@ begin
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
3
downto
0
)
is
when
"0000"
=>
case
rwaddr_reg
(
5
downto
0
)
is
when
"0000
00
"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_bidr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0001"
=>
when
"000
00
1"
=>
if
(
wb_we_i
=
'1'
)
then
reg_sr_i2c_wdto_load_o
<=
'1'
;
reg_sr_i2c_err_load_o
<=
'1'
;
...
...
@@ -233,7 +279,7 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0010"
=>
when
"00
00
10"
=>
if
(
wb_we_i
=
'1'
)
then
reg_cr_rst_unlock_load_o
<=
'1'
;
reg_cr_rst_load_o
<=
'1'
;
...
...
@@ -273,56 +319,56 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0011"
=>
when
"00
00
11"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch1pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch1pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0100"
=>
when
"0
00
100"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch2pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch2pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0101"
=>
when
"0
00
101"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch3pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch3pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0110"
=>
when
"0
00
110"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch4pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch4pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0111"
=>
when
"0
00
111"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch5pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch5pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
when
"
00
1000"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch6pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch6pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1001"
=>
when
"
00
1001"
=>
if
(
wb_we_i
=
'1'
)
then
reg_tvlr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_tvlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1010"
=>
when
"
00
1010"
=>
if
(
wb_we_i
=
'1'
)
then
reg_tvhr_load_o
<=
'1'
;
end
if
;
...
...
@@ -353,7 +399,7 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1011"
=>
when
"
00
1011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
reg_tb_rd_req_p_o
<=
'1'
;
...
...
@@ -386,7 +432,7 @@ begin
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1100"
=>
when
"
00
1100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
27
downto
0
)
<=
reg_tbcyr_i
;
...
...
@@ -396,13 +442,13 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1101"
=>
when
"
00
1101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_tbtlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1110"
=>
when
"
00
1110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_tbthr_i
;
...
...
@@ -432,7 +478,7 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1111"
=>
when
"
00
1111"
=>
if
(
wb_we_i
=
'1'
)
then
reg_tbcsr_clr_load_o
<=
'1'
;
end
if
;
...
...
@@ -464,6 +510,497 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch1ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch1ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch1ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch2ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch2ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch2ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch3ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch3ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch3ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch4ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch4ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch4ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch5ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch5ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch5ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch6ltstlr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
reg_ch6ltsthr_tai_i
;
rddata_reg
(
31
)
<=
reg_ch6ltsthr_wrtag_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
5
downto
0
)
<=
reg_lsr_front_ttl_i
;
rddata_reg
(
9
downto
6
)
<=
reg_lsr_front_invttl_i
;
rddata_reg
(
15
downto
10
)
<=
reg_lsr_rear_i
;
rddata_reg
(
21
downto
16
)
<=
reg_lsr_fs_i
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
3
downto
0
)
<=
reg_mswr_bit_i
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -521,6 +1058,29 @@ begin
-- Buffer empty
-- Clear tag buffer
reg_tbcsr_clr_o
<=
wrdata_reg
(
18
);
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Front panel TTL input state
-- Front panel TTL-BAR input state
-- Rear panel input state
-- Input failsafe state
-- State of MultiCast switches
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/conv_regs.wb
View file @
89385741
...
...
@@ -29,6 +29,7 @@
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
-- 31-07-2014 Theodor Stana Added MSWR & LSR registers
--==============================================================================
-- TODO: -
--==============================================================================
...
...
@@ -411,4 +412,379 @@ peripheral {
};
};
reg {
name = "CH1LTSCYR";
description = "Channel 1 Latest Timestamp Cycles Register";
prefix = "ch1ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH1LTSTLR";
description = "Channel 1 Latest Timestamp TAI Low Register";
prefix = "ch1ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH1LTSTHR";
description = "Channel 1 Latest Timestamp TAI High Register";
prefix = "ch1ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH2LTSCYR";
description = "Channel 2 Latest Timestamp Cycles Register";
prefix = "ch2ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH2LTSTLR";
description = "Channel 2 Latest Timestamp TAI Low Register";
prefix = "ch2ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH2LTSTHR";
description = "Channel 2 Latest Timestamp TAI High Register";
prefix = "ch2ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH3LTSCYR";
description = "Channel 3 Latest Timestamp Cycles Register";
prefix = "ch3ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH3LTSTLR";
description = "Channel 3 Latest Timestamp TAI Low Register";
prefix = "ch3ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH3LTSTHR";
description = "Channel 3 Latest Timestamp TAI High Register";
prefix = "ch3ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH4LTSCYR";
description = "Channel 4 Latest Timestamp Cycles Register";
prefix = "ch4ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
prefix = "tai";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH4LTSTLR";
description = "Channel 4 Latest Timestamp TAI Low Register";
prefix = "ch4ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH4LTSTHR";
description = "Channel 4 Latest Timestamp TAI High Register";
prefix = "ch4ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH5LTSCYR";
description = "Channel 5 Latest Timestamp Cycles Register";
prefix = "ch5ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH5LTSTLR";
description = "Channel 5 Latest Timestamp TAI Low Register";
prefix = "ch5ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH5LTSTHR";
description = "Channel 5 Latest Timestamp TAI High Register";
prefix = "ch5ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH6LTSCYR";
description = "Channel 6 Latest Timestamp Cycles Register";
prefix = "ch6ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "CH6LTSTLR";
description = "Channel 6 Latest Timestamp TAI Low Register";
prefix = "ch6ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH6LTSTHR";
description = "Channel 6 Latest Timestamp TAI High Register";
prefix = "ch6ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "LSR";
description = "Line Status Register";
prefix = "lsr";
field {
name = "Front panel TTL input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "front_ttl";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel INV-TTL input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "front_invttl";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Rear panel input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "rear";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Input failsafe state";
description = "High if line is in failsafe mode (no cable plugged in)\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "fs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "MSWR";
description = "Multicast Switch Register";
prefix = "mswr";
field {
name = "State of MultiCast switches";
prefix = "bit";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
top/conv_common_gw.vhd
View file @
89385741
...
...
@@ -120,13 +120,28 @@ entity conv_common_gw is
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
-- I2C LED -- conect to a bicolor LED of choice
-- SPI interface to on-board flash chip
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_err_o reflects the state of SR.I2C_ERR bit in conv_regs
led_i2c_o
:
out
std_logic
;
led_i2c_err_o
:
out
std_logic
;
-- Switch inputs (for readout from converter status register)
sw_gp_n_i
:
in
std_logic_vector
(
7
downto
0
);
sw_multicast_n_i
:
in
std_logic_vector
(
3
downto
0
);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_ttl_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_invttl_i
:
in
std_logic_vector
(
3
downto
0
);
line_rear_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_rear_fs_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
-- Bicolor LED signals
bicolor_led_state_i
:
in
std_logic_vector
(
2
*
g_bicolor_led_columns
*
g_bicolor_led_lines
-1
downto
0
);
bicolor_led_col_o
:
out
std_logic_vector
(
g_bicolor_led_columns
-1
downto
0
);
...
...
@@ -150,39 +165,63 @@ architecture arch of conv_common_gw is
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
2
;
-- slave order definitions
constant
c_slv_conv_regs
:
natural
:
=
0
;
constant
c_slv_multiboot
:
natural
:
=
1
;
constant
c_slv_onewire_mst
:
natural
:
=
2
;
-- Converter board registers SDB definition
constant
c_conv_regs_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"00"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"3ab464e8"
,
-- echo "conv_regs " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20140731"
,
name
=>
"conv_regs "
)));
-- base address definitions
constant
c_addr_conv_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_multiboot
:
t_wishbone_address
:
=
x"00000040"
;
constant
c_addr_onewire_mst
:
t_wishbone_address
:
=
x"00000080"
;
-- address mask definitions
constant
c_mask_conv_regs
:
t_wishbone_address
:
=
x"00000fc0"
;
constant
c_mask_multiboot
:
t_wishbone_address
:
=
x"00000fc0"
;
constant
c_mask_onewire_mst
:
t_wishbone_address
:
=
x"00000fe0"
;
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
c_addr_conv_regs
--c_slv_multiboot => c_addr_multiboot,
--c_slv_onewire_mst => c_addr_onewire_mst
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
c_mask_conv_regs
--c_slv_multiboot => c_mask_multiboot,
--c_slv_onewire_mst => c_mask_onewire_mst
);
constant
c_addr_multiboot
:
t_wishbone_address
:
=
x"00000100"
;
constant
c_addr_onewire_mst
:
t_wishbone_address
:
=
x"000000c0"
;
constant
c_addr_sdb
:
t_wishbone_address
:
=
x"00000200"
;
-- -- address mask definitions
-- constant c_mask_conv_regs : t_wishbone_address := x"00000fc0";
-- constant c_mask_multiboot : t_wishbone_address := x"00000fc0";
-- constant c_mask_onewire_mst : t_wishbone_address := x"00000fe0";
--
-- -- addresses constant for Wishbone crossbar
-- constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
-- := (
-- c_slv_conv_regs => c_addr_conv_regs
-- -- c_slv_multiboot => c_addr_multiboot,
-- -- c_slv_onewire_mst => c_addr_onewire_mst
-- );
--
-- -- masks constant for Wishbone crossbar
-- constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
-- := (
-- c_slv_conv_regs => c_mask_conv_regs
-- -- c_slv_multiboot => c_mask_multiboot,
-- -- c_slv_onewire_mst => c_mask_onewire_mst
-- );
-- SDB interconnect layout
constant
c_sdb_layout
:
t_sdb_record_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
f_sdb_embed_device
(
c_conv_regs_sdb
,
c_addr_conv_regs
),
c_slv_multiboot
=>
f_sdb_embed_device
(
c_xwb_xil_multiboot_sdb
,
c_addr_multiboot
)
);
--============================================================================
-- Component declarations
...
...
@@ -256,7 +295,7 @@ architecture arch of conv_common_gw is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -351,7 +390,53 @@ architecture arch of conv_common_gw is
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel TTL input state' in reg: 'LSR'
reg_lsr_front_ttl_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel TTL-BAR input state' in reg: 'LSR'
reg_lsr_front_invttl_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_fs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'State of MultiCast switches' in reg: 'MSWR'
reg_mswr_bit_i
:
in
std_logic_vector
(
3
downto
0
)
);
end
component
conv_regs
;
...
...
@@ -418,10 +503,10 @@ architecture arch of conv_common_gw is
signal
led_i2c_blink
:
std_logic
;
-- Wishbone crossbar signals
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-
1
downto
0
);
--==============================================================================
-- architecture begin
...
...
@@ -693,27 +778,50 @@ begin
end
if
;
end
process
p_i2c_err_led
;
-- Set the I2C err signal for the LED
led_i2c_err_o
<=
i2c_err_bit
;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar
:
xwb_crossbar
generic
map
(
g_num_masters
=>
c_nr_masters
,
g_num_slaves
=>
c_nr_slaves
,
g_registered
=>
false
,
g_address
=>
c_addresses
,
g_mask
=>
c_masks
)
port
map
(
clk_sys_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
slave_i
=>
xbar_slave_in
,
slave_o
=>
xbar_slave_out
,
master_i
=>
xbar_master_in
,
master_o
=>
xbar_master_out
);
cmp_wb_crossbar
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_nr_masters
,
g_num_slaves
=>
c_nr_slaves
,
g_registered
=>
false
,
g_wraparound
=>
true
,
g_layout
=>
c_sdb_layout
,
g_sdb_addr
=>
c_addr_sdb
)
port
map
(
clk_sys_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
slave_i
=>
xbar_slave_in
,
slave_o
=>
xbar_slave_out
,
master_i
=>
xbar_master_in
,
master_o
=>
xbar_master_out
);
-- cmp_wb_crossbar : xwb_crossbar
-- generic map
-- (
-- g_num_masters => c_nr_masters,
-- g_num_slaves => c_nr_slaves,
-- g_registered => false,
-- g_address => c_addresses,
-- g_mask => c_masks
-- )
-- port map
-- (
-- clk_sys_i => clk_20_i,
-- rst_n_i => rst_20_n,
-- slave_i => xbar_slave_in,
-- slave_o => xbar_slave_out,
-- master_i => xbar_master_in,
-- master_o => xbar_master_out
-- );
--============================================================================
-- Converter board registers
...
...
@@ -728,7 +836,7 @@ begin
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
5
downto
2
),
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
7
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
...
...
@@ -800,7 +908,33 @@ begin
reg_tbcsr_clr_load_o
=>
open
,
reg_tbcsr_usedw_i
=>
(
others
=>
'0'
),
reg_tbcsr_full_i
=>
'0'
,
reg_tbcsr_empty_i
=>
'0'
reg_tbcsr_empty_i
=>
'0'
,
reg_ch1ltstlr_i
=>
(
others
=>
'0'
),
reg_ch1ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch1ltsthr_wrtag_i
=>
'0'
,
reg_ch2ltstlr_i
=>
(
others
=>
'0'
),
reg_ch2ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch2ltsthr_wrtag_i
=>
'0'
,
reg_ch3ltstlr_i
=>
(
others
=>
'0'
),
reg_ch3ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch3ltsthr_wrtag_i
=>
'0'
,
reg_ch4ltstlr_i
=>
(
others
=>
'0'
),
reg_ch4ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch4ltsthr_wrtag_i
=>
'0'
,
reg_ch5ltstlr_i
=>
(
others
=>
'0'
),
reg_ch5ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch5ltsthr_wrtag_i
=>
'0'
,
reg_ch6ltstlr_i
=>
(
others
=>
'0'
),
reg_ch6ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch6ltsthr_wrtag_i
=>
'0'
,
reg_lsr_front_ttl_i
=>
line_ttl_i
,
reg_lsr_front_invttl_i
=>
line_invttl_i
,
reg_lsr_rear_i
=>
line_rear_i
,
reg_lsr_fs_i
=>
line_rear_fs_i
,
reg_mswr_bit_i
=>
sw_multicast
);
-- Implement the RST_UNLOCK bit
...
...
@@ -834,6 +968,22 @@ begin
end
if
;
end
process
p_rst_fr_reg
;
--============================================================================
-- Instantiate Xilinx MultiBoot module
--============================================================================
cmp_multiboot
:
xwb_xil_multiboot
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
wbs_i
=>
xbar_master_out
(
c_slv_multiboot
),
wbs_o
=>
xbar_master_in
(
c_slv_multiboot
),
spi_cs_n_o
=>
flash_cs_n_o
,
spi_sclk_o
=>
flash_sclk_o
,
spi_mosi_o
=>
flash_mosi_o
,
spi_miso_i
=>
flash_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
...
...
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