Commit 9b832b6a authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

wbgen2 generated files with new register names (no change to memory map

parent 0f499dc4
......@@ -2,17 +2,17 @@
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 02/06/17 15:05:15
* Author : auto-generated by wbgen2 from .\conv_regs.wb
* Created : 09/26/17 10:50:26
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS__\CONV_REGS_WB
#define __WBGEN2_REGDEFS__\CONV_REGS_WB
#include <inttypes.h>
......@@ -96,29 +96,29 @@
#define REG_CR_MPT_W(value) WBGEN2_GEN_WRITE(value, 2, 8)
#define REG_CR_MPT_R(reg) WBGEN2_GEN_READ(reg, 2, 8)
/* definitions for register: CH1TTLPCR */
/* definitions for register: CH1FPPCR */
/* definitions for register: CH2TTLPCR */
/* definitions for register: CH2FPPCR */
/* definitions for register: CH3TTLPCR */
/* definitions for register: CH3FPPCR */
/* definitions for register: CH4TTLPCR */
/* definitions for register: CH4FPPCR */
/* definitions for register: CH5TTLPCR */
/* definitions for register: CH5FPPCR */
/* definitions for register: CH6TTLPCR */
/* definitions for register: CH6FPPCR */
/* definitions for register: CH1BLOPCR */
/* definitions for register: CH1RPPCR */
/* definitions for register: CH2BLOPCR */
/* definitions for register: CH2RPPCR */
/* definitions for register: CH3BLOPCR */
/* definitions for register: CH3RPPCR */
/* definitions for register: CH4BLOPCR */
/* definitions for register: CH4RPPCR */
/* definitions for register: CH5BLOPCR */
/* definitions for register: CH5RPPCR */
/* definitions for register: CH6BLOPCR */
/* definitions for register: CH6RPPCR */
/* definitions for register: TVLR */
......@@ -299,96 +299,100 @@
/* definitions for register: UIDHR */
/* definitions for register: TEMPR */
/* [0x0]: REG BIDR */
#define REG_REG_BIDR 0x00000000
/* [0x4]: REG SR */
#define REG_REG_SR 0x00000004
/* [0x8]: REG ERR */
#define REG_REG_ERR 0x00000008
/* [0xc]: REG CR */
#define REG_REG_CR 0x0000000c
/* [0x10]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x00000010
/* [0x14]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000014
/* [0x18]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000018
/* [0x1c]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x0000001c
/* [0x20]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x00000020
/* [0x24]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000024
/* [0x28]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000028
/* [0x2c]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x0000002c
/* [0x30]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x00000030
/* [0x34]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000034
/* [0x38]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000038
/* [0x3c]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x0000003c
/* [0x40]: REG TVLR */
#define REG_REG_TVLR 0x00000040
/* [0x44]: REG TVHR */
#define REG_REG_TVHR 0x00000044
/* [0x48]: REG TBMR */
#define REG_REG_TBMR 0x00000048
/* [0x4c]: REG TBCYR */
#define REG_REG_TBCYR 0x0000004c
/* [0x50]: REG TBTLR */
#define REG_REG_TBTLR 0x00000050
/* [0x54]: REG TBTHR */
#define REG_REG_TBTHR 0x00000054
/* [0x58]: REG TBCSR */
#define REG_REG_TBCSR 0x00000058
/* [0x5c]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x0000005c
/* [0x60]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x00000060
/* [0x64]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000064
/* [0x68]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000068
/* [0x6c]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x0000006c
/* [0x70]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x00000070
/* [0x74]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000074
/* [0x78]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000078
/* [0x7c]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x0000007c
/* [0x80]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x00000080
/* [0x84]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000084
/* [0x88]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000088
/* [0x8c]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x0000008c
/* [0x90]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x00000090
/* [0x94]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000094
/* [0x98]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000098
/* [0x9c]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x0000009c
/* [0xa0]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x000000a0
/* [0xa4]: REG LSR */
#define REG_REG_LSR 0x000000a4
/* [0xa8]: REG OSWR */
#define REG_REG_OSWR 0x000000a8
/* [0xac]: REG UIDLR */
#define REG_REG_UIDLR 0x000000ac
/* [0xb0]: REG UIDHR */
#define REG_REG_UIDHR 0x000000b0
/* [0xb4]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b4
PACKED struct REG_WB {
/* [0x0]: REG BIDR */
uint32_t BIDR;
/* [0x4]: REG SR */
uint32_t SR;
/* [0x8]: REG ERR */
uint32_t ERR;
/* [0xc]: REG CR */
uint32_t CR;
/* [0x10]: REG CH1FPPCR */
uint32_t CH1FPPCR;
/* [0x14]: REG CH2FPPCR */
uint32_t CH2FPPCR;
/* [0x18]: REG CH3FPPCR */
uint32_t CH3FPPCR;
/* [0x1c]: REG CH4FPPCR */
uint32_t CH4FPPCR;
/* [0x20]: REG CH5FPPCR */
uint32_t CH5FPPCR;
/* [0x24]: REG CH6FPPCR */
uint32_t CH6FPPCR;
/* [0x28]: REG CH1RPPCR */
uint32_t CH1RPPCR;
/* [0x2c]: REG CH2RPPCR */
uint32_t CH2RPPCR;
/* [0x30]: REG CH3RPPCR */
uint32_t CH3RPPCR;
/* [0x34]: REG CH4RPPCR */
uint32_t CH4RPPCR;
/* [0x38]: REG CH5RPPCR */
uint32_t CH5RPPCR;
/* [0x3c]: REG CH6RPPCR */
uint32_t CH6RPPCR;
/* [0x40]: REG TVLR */
uint32_t TVLR;
/* [0x44]: REG TVHR */
uint32_t TVHR;
/* [0x48]: REG TBMR */
uint32_t TBMR;
/* [0x4c]: REG TBCYR */
uint32_t TBCYR;
/* [0x50]: REG TBTLR */
uint32_t TBTLR;
/* [0x54]: REG TBTHR */
uint32_t TBTHR;
/* [0x58]: REG TBCSR */
uint32_t TBCSR;
/* [0x5c]: REG CH1LTSCYR */
uint32_t CH1LTSCYR;
/* [0x60]: REG CH1LTSTLR */
uint32_t CH1LTSTLR;
/* [0x64]: REG CH1LTSTHR */
uint32_t CH1LTSTHR;
/* [0x68]: REG CH2LTSCYR */
uint32_t CH2LTSCYR;
/* [0x6c]: REG CH2LTSTLR */
uint32_t CH2LTSTLR;
/* [0x70]: REG CH2LTSTHR */
uint32_t CH2LTSTHR;
/* [0x74]: REG CH3LTSCYR */
uint32_t CH3LTSCYR;
/* [0x78]: REG CH3LTSTLR */
uint32_t CH3LTSTLR;
/* [0x7c]: REG CH3LTSTHR */
uint32_t CH3LTSTHR;
/* [0x80]: REG CH4LTSCYR */
uint32_t CH4LTSCYR;
/* [0x84]: REG CH4LTSTLR */
uint32_t CH4LTSTLR;
/* [0x88]: REG CH4LTSTHR */
uint32_t CH4LTSTHR;
/* [0x8c]: REG CH5LTSCYR */
uint32_t CH5LTSCYR;
/* [0x90]: REG CH5LTSTLR */
uint32_t CH5LTSTLR;
/* [0x94]: REG CH5LTSTHR */
uint32_t CH5LTSTHR;
/* [0x98]: REG CH6LTSCYR */
uint32_t CH6LTSCYR;
/* [0x9c]: REG CH6LTSTLR */
uint32_t CH6LTSTLR;
/* [0xa0]: REG CH6LTSTHR */
uint32_t CH6LTSTHR;
/* [0xa4]: REG LSR */
uint32_t LSR;
/* [0xa8]: REG OSWR */
uint32_t OSWR;
/* [0xac]: REG UIDLR */
uint32_t UIDLR;
/* [0xb0]: REG UIDHR */
uint32_t UIDHR;
/* [0xb4]: REG TEMPR */
uint32_t TEMPR;
};
#endif
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