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a381f447
Commit
a381f447
authored
Sep 27, 2018
by
Denia Bouhired-Ferrag
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Merge branch 'proposed-master'
parents
f866939a
0226eb67
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5 changed files
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1354 additions
and
1482 deletions
+1354
-1482
cern-title.tex
doc/cern-title.tex
+2
-3
conv-regs.tex
doc/conv-regs.tex
+108
-108
general-cores
ip_cores/general-cores
+1
-1
conv_common_gw.vhd
top/conv_common_gw.vhd
+813
-903
conv_common_gw_pkg.vhd
top/conv_common_gw_pkg.vhd
+430
-467
No files found.
doc/cern-title.tex
View file @
a381f447
...
...
@@ -9,7 +9,7 @@
\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
17 February 2017
\hfill
27 September 2018
\vspace*
{
3cm
}
...
...
@@ -24,9 +24,8 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent
{
\Large
\textbf
{
Theodor-Adrian Stana
(CERN/BE-CO-HT)
}}
\\
\noindent
{
\Large
\textbf
{
(CERN/BE-CO-HT)
}}
\\
\noindent
{
Last modified by
\textit
{
Denia Bouhired-Ferrag (CERN/BE-CO-HT)
}}
\\
\noindent
\rule
{
\textwidth
}{
.05cm
}
...
...
doc/conv-regs.tex
View file @
a381f447
...
...
@@ -21,18 +21,18 @@ Base address: 0x000
0x4
&
Note(1)
&
SR
&
Status Register
\\
0x8
&
0x00000000
&
ERR
&
Error Register
\\
0xc
&
0x00000000
&
CR
&
Control Register
\\
0x10
&
0x00000000
&
CH1
TTLPCR
&
Channel 1 TTL
Pulse Counter Register
\\
0x14
&
0x00000000
&
CH2
TTLPCR
&
Channel 2 TTL
Pulse Counter Register
\\
0x18
&
0x00000000
&
CH3
TTLPCR
&
Channel 3 TTL
Pulse Counter Register
\\
0x1c
&
0x00000000
&
CH4
TTLPCR
&
Channel 4 TTL
Pulse Counter Register
\\
0x20
&
0x00000000
&
CH5
TTLPCR
&
Channel 5 TTL
Pulse Counter Register
\\
0x24
&
0x00000000
&
CH6
TTLPCR
&
Channel 6 TTL
Pulse Counter Register
\\
0x28
&
0x00000000
&
CH1
BLOPCR
&
Channel 1 BLO
Pulse Counter Register
\\
0x2c
&
0x00000000
&
CH2
BLOPCR
&
Channel 2 BLO
Pulse Counter Register
\\
0x30
&
0x00000000
&
CH3
BLOPCR
&
Channel 3 BLO
Pulse Counter Register
\\
0x34
&
0x00000000
&
CH4
BLOPCR
&
Channel 4 BLO
Pulse Counter Register
\\
0x38
&
0x00000000
&
CH5
BLOPCR
&
Channel 5 BLO
Pulse Counter Register
\\
0x3c
&
0x00000000
&
CH6
BLOPCR
&
Channel 6 BLO
Pulse Counter Register
\\
0x10
&
0x00000000
&
CH1
FPPCR
&
Channel 1 Front
Pulse Counter Register
\\
0x14
&
0x00000000
&
CH2
FPPCR
&
Channel 2 Front
Pulse Counter Register
\\
0x18
&
0x00000000
&
CH3
FPPCR
&
Channel 3 Front
Pulse Counter Register
\\
0x1c
&
0x00000000
&
CH4
FPPCR
&
Channel 4 Front
Pulse Counter Register
\\
0x20
&
0x00000000
&
CH5
FPPCR
&
Channel 5 Front
Pulse Counter Register
\\
0x24
&
0x00000000
&
CH6
FPPCR
&
Channel 6 Front
Pulse Counter Register
\\
0x28
&
0x00000000
&
CH1
RPPCR
&
Channel 1 Rear
Pulse Counter Register
\\
0x2c
&
0x00000000
&
CH2
RPPCR
&
Channel 2 Rear
Pulse Counter Register
\\
0x30
&
0x00000000
&
CH3
RPPCR
&
Channel 3 Rear
Pulse Counter Register
\\
0x34
&
0x00000000
&
CH4
RPPCR
&
Channel 4 Rear
Pulse Counter Register
\\
0x38
&
0x00000000
&
CH5
RPPCR
&
Channel 5 Rear
Pulse Counter Register
\\
0x3c
&
0x00000000
&
CH6
RPPCR
&
Channel 6 Rear
Pulse Counter Register
\\
0x40
&
0x00000000
&
TVLR
&
Time Value Low Register
\\
0x44
&
0x00000000
&
TVHR
&
Time Value High Register
\\
0x48
&
0x00000000
&
TBMR
&
Tag Buffer Meta Register
\\
...
...
@@ -292,27 +292,27 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\end{small}
\end{itemize}
\subsubsection
{
CH1
TTLPCR - Channel 1 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH1
TTL
PCR
}
\subsubsection
{
CH1
FPPCR - Channel 1 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH1
FP
PCR
}
\vspace
{
11pt
}
\noindent
\resizebox
{
\textwidth
}{
!
}{
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -320,14 +320,14 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\begin{itemize}
\item
\begin{small}
{
\bf
CH1
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH1
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH2
TTLPCR - Channel 2 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH2
TTL
PCR
}
\subsubsection
{
CH2
FPPCR - Channel 2 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH2
FP
PCR
}
\vspace
{
11pt
}
\noindent
...
...
@@ -335,19 +335,19 @@ CH1TTLPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -355,31 +355,31 @@ CH1TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH2
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH2
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH3
TTLPCR - Channel 3 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH3
TTL
PCR
}
\subsubsection
{
CH3
FPPCR - Channel 3 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH3
FP
PCR
}
\vspace
{
11pt
}
\noindent
\resizebox
{
\textwidth
}{
!
}{
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -387,14 +387,14 @@ CH2TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH3
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH3
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH4
TTLPCR - Channel 4 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH4
TTL
PCR
}
\subsubsection
{
CH4
FPPCR - Channel 4 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH4
FP
PCR
}
\vspace
{
11pt
}
\noindent
...
...
@@ -402,19 +402,19 @@ CH3TTLPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -422,12 +422,12 @@ CH3TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH4
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH4
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH5
TTLPCR - Channel 5 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH5
TTL
PCR
}
\subsubsection
{
CH5
FPPCR - Channel 5 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH5
FP
PCR
}
\vspace
{
11pt
}
\noindent
...
...
@@ -435,19 +435,19 @@ CH4TTLPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -455,12 +455,12 @@ CH4TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH5
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH5
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH6
TTLPCR - Channel 6 Pulse Counter Register for TTL
pulses
}
\label
{
app:conv-regs-CH6
TTL
PCR
}
\subsubsection
{
CH6
FPPCR - Channel 6 Pulse Counter Register for Front panel
pulses
}
\label
{
app:conv-regs-CH6
FP
PCR
}
\vspace
{
11pt
}
...
...
@@ -469,19 +469,19 @@ CH5TTLPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
TTL
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
FP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
TTL
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
FP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
TTL
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
FP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
TTL
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
FP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -489,31 +489,31 @@ CH5TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH6
TTL
PCR
}
[
\emph
{
read/write
}
]:
TTL
pulse counter value
CH6
FP
PCR
}
[
\emph
{
read/write
}
]:
Front panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH1
BLOPCR - Channel 1 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH1
BLO
PCR
}
\subsubsection
{
CH1
RPPCR - Channel 1 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH1
RP
PCR
}
\vspace
{
11pt
}
\noindent
\resizebox
{
\textwidth
}{
!
}{
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH1
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -521,12 +521,12 @@ CH6TTLPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH1
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH1
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH2
BLOPCR - Channel 2 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH2
BLO
PCR
}
\subsubsection
{
CH2
RPPCR - Channel 2 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH2
RP
PCR
}
\vspace
{
11pt
}
...
...
@@ -535,19 +535,19 @@ CH1BLOPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH2
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -555,12 +555,12 @@ CH1BLOPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH2
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH2
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH3
BLOPCR - Channel 3 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH3
BLO
PCR
}
\subsubsection
{
CH3
RPPCR - Channel 3 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH3
RP
PCR
}
\vspace
{
11pt
}
...
...
@@ -569,19 +569,19 @@ CH2BLOPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH3
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -589,12 +589,12 @@ CH2BLOPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH3
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH3
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH4
BLOPCR - Channel 4 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH4
BLO
PCR
}
\subsubsection
{
CH4
RPPCR - Channel 4 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH4
RP
PCR
}
\vspace
{
11pt
}
\noindent
...
...
@@ -602,19 +602,19 @@ CH3BLOPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH4
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -622,12 +622,12 @@ CH3BLOPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH4
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH4
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH5
BLOPCR - Channel 5 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH5
BLO
PCR
}
\subsubsection
{
CH5
RPPCR - Channel 5 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH5
RP
PCR
}
\vspace
{
11pt
}
\noindent
...
...
@@ -635,19 +635,19 @@ CH4BLOPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH5
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -655,12 +655,12 @@ CH4BLOPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH5
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH5
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
CH6
BLOPCR - Channel 6 Pulse Counter Register for BLO
pulses
}
\label
{
app:conv-regs-CH6
BLO
PCR
}
\subsubsection
{
CH6
RPPCR - Channel 6 Pulse Counter Register for Rear panel
pulses
}
\label
{
app:conv-regs-CH6
RP
PCR
}
\vspace
{
11pt
}
...
...
@@ -669,19 +669,19 @@ CH5BLOPCR
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
BLO
PCR[31:24]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
RP
PCR[31:24]
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
BLO
PCR[23:16]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
RP
PCR[23:16]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
BLO
PCR[15:8]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
RP
PCR[15:8]
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
BLO
PCR[7:0]
}
\\
\multicolumn
{
8
}{
|c|
}{
\cellcolor
{
gray!25
}
CH6
RP
PCR[7:0]
}
\\
\hline
\end{tabular}
}
...
...
@@ -689,8 +689,8 @@ CH5BLOPCR
\begin{itemize}
\item
\begin{small}
{
\bf
CH6
BLO
PCR
}
[
\emph
{
read/write
}
]:
BLO
pulse counter value
CH6
RP
PCR
}
[
\emph
{
read/write
}
]:
Rear panel
pulse counter value
\end{small}
\end{itemize}
\subsubsection
{
TVLR - Time Value Low Register
}
...
...
general-cores
@
1c2dd12b
Subproject commit
2782bc8c76e9c6397ff836d208e814718269a975
Subproject commit
1c2dd12b1bceeab3b32b41c3522931c658ad15a7
top/conv_common_gw.vhd
View file @
a381f447
--
==============================================================================
--
------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Converter board common gateware top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-07-24
-- Converter board common gateware
-- URL https://www.ohwr.org/projects/conv-common-gw/wiki/wiki
--------------------------------------------------------------------------------
--
--
version: 1.0
--
Converter board common gateware top-level file
--
--
d
escription:
--
D
escription:
-- This module is to be instantiated in all pulse converter board designs,
-- for example the CONV-TTL-BLO or CONV-TTL-RS485. It contains a set of
-- modules common to all these boards, that are configurable via generics to
-- accommodate for the application of each board.
--
--
d
ependencies:
--
D
ependencies:
-- general-cores repository [1]
--
--
r
eferences:
--
R
eferences:
-- [1] Board IDs for level conversion circuits
-- www.ohwr.org/projects/conv-common-gw/wiki/Board-id
-- [2] Platform-independent core collection webpage on OHWR,
...
...
@@ -26,9 +23,11 @@
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
==============================================================================
--
------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
...
...
@@ -38,7 +37,7 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--
==============================================================================
--
------------------------------------------------------------------------------
library
ieee
;
...
...
@@ -55,186 +54,155 @@ use work.genram_pkg.all;
use
work
.
conv_common_gw_pkg
.
all
;
entity
conv_common_gw
is
generic
(
generic
(
-- Reduces some timeouts to speed up simulations
g_SIMUL
:
boolean
:
=
false
;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_RST_TIME
:
positive
:
=
2
*
(
10
**
6
);
-- Number of repeater channels
g_
nr_chans
:
integer
:
=
6
;
g_
NR_CHANS
:
integer
:
=
6
;
-- Number of inverter channels
g_nr_inv_chans
:
integer
:
=
4
;
g_NR_INV_CHANS
:
integer
:
=
4
;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_
board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
g_
BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
-- Gateware version
g_gwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"40"
;
g_GWVERS
:
std_logic_vector
(
7
downto
0
)
:
=
x"40"
;
-- Generate pulse repetition logic with fixed output pulse width
g_
pgen_fixed_width
:
boolean
:
=
true
;
g_
PGEN_FIXED_WIDTH
:
boolean
:
=
true
;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg
:
natural
range
2
to
40
:
=
24
;
g_pgen_pwidth_sh
:
natural
range
2
to
40
:
=
5
;
g_PGEN_PWIDTH_LG
:
natural
range
2
to
40
:
=
24
;
g_PGEN_PWIDTH_SH
:
natural
range
2
to
40
:
=
5
;
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_
pgen_pperiod_cont
:
natural
range
2
to
5000
:
=
4800
;
--for LONG pulses changes maximum frequency to ~104kHz
g_
pgen_pperiod_lg
:
natural
range
6
to
300
:
=
191
;
--for SHORT pulses changes maximum frequency to ~2MHz
g_
pgen_pperiod_sh
:
natural
range
2
to
300
:
=
9
;
g_
PGEN_PPERIOD_CONT
:
natural
range
2
to
5000
:
=
4800
;
--
for LONG pulses changes maximum frequency to ~104kHz
g_
PGEN_PPERIOD_LG
:
natural
range
6
to
300
:
=
191
;
--
for SHORT pulses changes maximum frequency to ~2MHz
g_
PGEN_PPERIOD_SH
:
natural
range
2
to
300
:
=
9
;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len
:
integer
:
=
4
;
g_PGEN_GF_LEN
:
integer
:
=
4
;
-- Burst-mode-specific generics:
g_
temp_decre_step_lg
:
t_temp_decre_step
:
=
g_
TEMP_DECRE_STEP_LG
:
t_temp_decre_step
:
=
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
5750
,
100
,
79
,
13
,
12
,
4
,
5
,
13
);
g_temp_decre_step_sh
:
t_temp_decre_step
:
=
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
-- Single pulse temperature rise
-- For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_lg
:
in
unsigned
(
19
downto
0
)
:
=
x"17700"
;
-- For short 250ns pulses
g_burstctrl_1_pulse_temp_rise_sh
:
in
unsigned
(
19
downto
0
)
:
=
x"01388"
;
g_TEMP_DECRE_STEP_SH
:
t_temp_decre_step
:
=
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
-- Single pulse temperature rise for long 1.2us pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_LG
:
unsigned
(
19
downto
0
)
:
=
x"17700"
;
-- Single pulse temperature rise for short 250ns pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_SH
:
unsigned
(
19
downto
0
)
:
=
x"01388"
;
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh
:
in
unsigned
(
39
downto
0
)
:
=
x"02540BE400"
;
--For both long 1.2us pulses and short 250ns
-- For both long 1.2us pulses and short 250ns
g_BURSTCTRL_MAX_TEMP_LG_SH
:
unsigned
(
39
downto
0
)
:
=
x"02540BE400"
;
-- Generate logic with pulse counters
g_with_pulse_cnt
:
boolean
:
=
false
;
g_WITH_PULSE_CNT
:
boolean
:
=
false
;
-- Generate logic with pulse timetag
g_with_pulse_timetag
:
boolean
:
=
false
;
g_WITH_PULSE_TIMETAG
:
boolean
:
=
false
;
-- Generate logic with manual trigger
g_with_man_trig
:
boolean
:
=
false
;
g_man_trig_pwidth
:
integer
:
=
24
;
g_WITH_MAN_TRIG
:
boolean
:
=
false
;
g_MAN_TRIG_PWIDTH
:
integer
:
=
24
;
-- Generate one-wire master for thermometer
g_with_thermometer
:
boolean
:
=
false
;
g_WITH_THERMOMETER
:
boolean
:
=
false
;
-- Bicolor LED controller signals
g_bicolor_led_columns
:
integer
:
=
6
;
g_bicolor_led_lines
:
integer
:
=
2
);
port
(
g_BICOLOR_LED_COLUMNS
:
integer
:
=
6
;
g_BICOLOR_LED_LINES
:
integer
:
=
2
);
port
(
-- Clocks
clk_20_i
:
in
std_logic
;
clk_125_p_i
:
in
std_logic
;
clk_125_n_i
:
in
std_logic
;
clk_20_i
:
in
std_logic
;
clk_125_p_i
:
in
std_logic
;
clk_125_n_i
:
in
std_logic
;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o
:
out
std_logic
;
rst_n_o
:
out
std_logic
;
-- Glitch filter active-low enable signal
gf_en_n_i
:
in
std_logic
;
gf_en_n_i
:
in
std_logic
;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
:
in
std_logic
;
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i
:
in
std_logic
;
burst_en_n_i
:
in
std_logic
;
-- Pulse width selection, port low means 250ns, high means 1.2us
pulse_width_sel_n_i
:
in
std_logic
;
-- Channel enable
global_ch_oen_o
:
out
std_logic
;
pulse_front_oen_o
:
out
std_logic
;
pulse_rear_oen_o
:
out
std_logic
;
inv_oen_o
:
out
std_logic
;
global_ch_oen_o
:
out
std_logic
;
pulse_front_oen_o
:
out
std_logic
;
pulse_rear_oen_o
:
out
std_logic
;
inv_oen_o
:
out
std_logic
;
-- Pulse I/O
pulse_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_front_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_rear_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_front_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_rear_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_o
:
out
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Inverted pulse I/O
inv_pulse_i_n
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
inv_pulse_n_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
-- Channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
led_pulse_o
:
out
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Inverted channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
led_inv_pulse_o
:
out
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
-- I2C interface
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o
:
out
std_logic
;
led_i2c_o
:
out
std_logic
;
-- VME interface
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
-- SPI interface to on-board flash chip
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o
:
out
std_logic
;
dac20_sclk_o
:
out
std_logic
;
dac20_sync_n_o
:
out
std_logic
;
dac20_din_o
:
out
std_logic
;
dac20_sclk_o
:
out
std_logic
;
dac20_sync_n_o
:
out
std_logic
;
-- 125 MHz clock generator control
dac125_din_o
:
out
std_logic
;
dac125_sclk_o
:
out
std_logic
;
dac125_sync_n_o
:
out
std_logic
;
dac125_din_o
:
out
std_logic
;
dac125_sclk_o
:
out
std_logic
;
dac125_sync_n_o
:
out
std_logic
;
-- SFP lines
sfp_los_i
:
in
std_logic
;
sfp_present_i
:
in
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_sda_b
:
inout
std_logic
;
sfp_scl_
i
:
inout
std_logic
;
sfp_scl_
b
:
inout
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
;
-- Switch inputs (for readout from converter status register)
sw_gp_i
:
in
std_logic_vector
(
7
downto
0
);
sw_other_i
:
in
std_logic_vector
(
31
downto
0
);
sw_gp_i
:
in
std_logic_vector
(
7
downto
0
);
sw_other_i
:
in
std_logic_vector
(
31
downto
0
);
-- PCB Version information
hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
-- RTM lines
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_inv_i
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
line_rear_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_front_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
line_inv_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
line_rear_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_inv_fs_i
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
line_rear_fs_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_front_fs_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
line_inv_fs_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
line_rear_fs_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Thermometer line
thermometer_b
:
inout
std_logic
;
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o
:
out
std_logic
;
led_syserr_o
:
out
std_logic
;
-- Bicolor LED signals
bicolor_led_state_i
:
in
std_logic_vector
(
2
*
g_bicolor_led_columns
*
g_bicolor_led_lines
-1
downto
0
);
bicolor_led_col_o
:
out
std_logic_vector
(
g_bicolor_led_columns
-1
downto
0
);
bicolor_led_line_o
:
out
std_logic_vector
(
g_bicolor_led_lines
-1
downto
0
);
bicolor_led_line_oen_o
:
out
std_logic_vector
(
g_bicolor_led_lines
-1
downto
0
)
);
bicolor_led_state_i
:
in
std_logic_vector
(
2
*
g_BICOLOR_LED_COLUMNS
*
g_BICOLOR_LED_LINES
-1
downto
0
);
bicolor_led_col_o
:
out
std_logic_vector
(
g_BICOLOR_LED_COLUMNS
-1
downto
0
);
bicolor_led_line_o
:
out
std_logic_vector
(
g_BICOLOR_LED_LINES
-1
downto
0
);
bicolor_led_line_oen_o
:
out
std_logic_vector
(
g_BICOLOR_LED_LINES
-1
downto
0
));
end
entity
conv_common_gw
;
...
...
@@ -244,61 +212,57 @@ architecture arch of conv_common_gw is
--============================================================================
-- Constant declarations
--============================================================================
-- Short pulse widths
--constant c_pgen_pwidth_sh : natural := 5;
-- Short pulse widths
--
constant c_pgen_pwidth_sh : natural := 5;
-- Burst mode maximum duty cycle is 50%, i.e. divider is 2
constant
c_
pgen_duty_cycle_div_sh
:
natural
:
=
2
;
constant
c_
PGEN_DUTY_CYCLE_DIV_SH
:
natural
:
=
2
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_
nr_masters
:
natural
:
=
1
;
constant
c_
nr_slaves
:
natural
:
=
2
;
constant
c_
NR_MASTERS
:
natural
:
=
1
;
constant
c_
NR_SLAVES
:
natural
:
=
2
;
-- slave order definitions
constant
c_slv_conv_regs
:
natural
:
=
0
;
constant
c_slv_multiboot
:
natural
:
=
1
;
constant
c_slv_onewire_mst
:
natural
:
=
2
;
constant
c_SLV_CONV_REGS
:
natural
:
=
0
;
constant
c_SLV_MULTIBOOT
:
natural
:
=
1
;
-- base address definitions
constant
c_
addr_conv_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_
addr_multiboot
:
t_wishbone_address
:
=
x"00000100"
;
--constant c_addr_onewire_mst : t_wishbone_address := x"000002
00";
constant
c_addr_sdb
:
t_wishbone_address
:
=
x"00000f00"
;
constant
c_
ADDR_CONV_REGS
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_
ADDR_MULTIBOOT
:
t_wishbone_address
:
=
x"00000100"
;
constant
c_ADDR_SDB
:
t_wishbone_address
:
=
x"00000f
00"
;
-- SDB interconnect layout
-- c_conv_regs_sdb defined in conv_common_gw_pkg.vhd
constant
c_sdb_layout
:
t_sdb_record_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
f_sdb_embed_device
(
c_conv_regs_sdb
,
c_addr_conv_regs
),
c_slv_multiboot
=>
f_sdb_embed_device
(
c_xwb_xil_multiboot_sdb
,
c_addr_multiboot
)
-- c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
-- c_addr_onewire_mst)
constant
c_SDB_LAYOUT
:
t_sdb_record_array
(
c_NR_SLAVES
-1
downto
0
)
:
=
(
c_SLV_CONV_REGS
=>
f_sdb_embed_device
(
c_CONV_REGS_SDB
,
c_ADDR_CONV_REGS
),
c_SLV_MULTIBOOT
=>
f_sdb_embed_device
(
c_XWB_XIL_MULTIBOOT_SDB
,
c_ADDR_MULTIBOOT
)
);
-- Tag bufferdata width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- xx -- channel mask for max. nr. channels
constant
c_
tagbuff_data_width
:
positive
:
=
40
+
28
+
1
+
c_max_nr_chans
;
constant
c_
TAGBUFF_DATA_WIDTH
:
positive
:
=
40
+
28
+
1
+
c_max_nr_chans
;
--============================================================================
-- Type declarations
--============================================================================
-- Max. channel count of c_max_nr_chans enforced here:
type
t_pulse_led_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
18
downto
0
);
type
t_inv_pulse_led_cnt
is
array
(
g_
nr_inv_chans
-1
downto
0
)
of
unsigned
(
18
downto
0
);
type
t_inv_pulse_led_cnt
is
array
(
g_
NR_INV_CHANS
-1
downto
0
)
of
unsigned
(
18
downto
0
);
type
t_temp_rise_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
39
downto
0
);
type
t_pulse_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_ch_pcr
is
array
(
c_max_nr_chans
-1
downto
0
)
of
std_logic_vector
(
31
downto
0
);
-- Latest timestamp
type
t_lts_tai
is
array
(
c_max_nr_chans
-1
downto
0
)
of
std_logic_vector
(
39
downto
0
);
...
...
@@ -309,189 +273,190 @@ architecture arch of conv_common_gw is
-- Signal declarations
--============================================================================
-- Per-domain clock and reset signals
signal
clk_125
:
std_logic
;
signal
rst_125_n
:
std_logic
;
signal
rst_20_n
:
std_logic
;
signal
rst_20
:
std_logic
;
signal
rst_ext
:
std_logic
;
signal
clk_125
:
std_logic
;
signal
rst_125_n
:
std_logic
;
signal
rst_20_n
:
std_logic
;
signal
rst_20
:
std_logic
;
signal
rst_ext
:
std_logic
;
signal
rst_time
:
positive
:
=
10
;
-- Pulse logic signals
signal
trig_a
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_synced
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_degl
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_chan
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_chan_redge_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_chan_fedge_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_man
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_pgen
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_en_n
:
std_logic
;
signal
pulse_outp_cont
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_sh
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_r_edge_lg_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
pulse_f_edge_lg_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
pulse_r_edge_sh_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
pulse_f_edge_sh_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
pulse_outp_sh
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_lg
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_lg
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
temp_rise_c_lg
:
t_temp_rise_cnt
;
signal
temp_rise_c_sh
:
t_temp_rise_cnt
;
signal
pulse_outp_d0
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_redge_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
inv_pulse_outp
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
signal
inv_pulse_outp_d0
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
signal
inv_pulse_outp_fedge_p
:
std_logic_vector
(
g_
nr_inv_chans
-1
downto
0
);
signal
pmisse_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
flim_pmisse_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
fwdg_pmisse_p
:
std_logic_vector
(
g_
nr_chans
-1
downto
0
);
signal
pulse_outp_err_cont
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_err_lg_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_err_sh_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_err_lg_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_err_sh_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
trig_a
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_synced
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_degl
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_chan
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_chan_redge_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_chan_fedge_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_man
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
trig_pgen
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
burst_en_n
:
std_logic
;
signal
pulse_outp_cont
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
burst_outp_sh
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_r_edge_lg_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
pulse_f_edge_lg_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
pulse_r_edge_sh_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
pulse_f_edge_sh_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
pulse_outp_sh
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
burst_outp_lg
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_outp_lg
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_outp
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
temp_rise_c_lg
:
t_temp_rise_cnt
;
signal
temp_rise_c_sh
:
t_temp_rise_cnt
;
signal
pulse_outp_d0
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_outp_redge_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
inv_pulse_outp
:
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
signal
inv_pulse_outp_d0
:
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
signal
inv_pulse_outp_fedge_p
:
std_logic_vector
(
g_
NR_INV_CHANS
-1
downto
0
);
signal
pmisse_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
flim_pmisse_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
fwdg_pmisse_p
:
std_logic_vector
(
g_
NR_CHANS
-1
downto
0
);
signal
pulse_outp_err_cont
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_outp_err_lg_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
pulse_outp_err_sh_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
burst_outp_err_lg_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
burst_outp_err_sh_p
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Output enable signals
signal
global_oen
:
std_logic
;
signal
front_oen
,
invttl_oen
:
std_logic
;
signal
rear_oen
:
std_logic
;
signal
global_oen
:
std_logic
;
signal
front_oen
,
invttl_oen
:
std_logic
;
signal
rear_oen
:
std_logic
;
-- I2C bridge signals
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
i2c_tip
:
std_logic
;
signal
i2c_err_p
:
std_logic
;
signal
i2c_wdto_p
:
std_logic
;
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
i2c_tip
:
std_logic
;
signal
i2c_err_p
:
std_logic
;
signal
i2c_wdto_p
:
std_logic
;
-- Signals to/from converter system registers component
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
sw_gp
:
std_logic_vector
(
7
downto
0
);
signal
sw_multicast
:
std_logic_vector
(
3
downto
0
);
signal
rst_unlock
:
std_logic
;
signal
rst_unlock_bit
:
std_logic
;
signal
rst_unlock_bit_ld
:
std_logic
;
signal
rst_bit
:
std_logic
;
signal
rst_bit_ld
:
std_logic
;
signal
rst_fr_reg
:
std_logic
;
signal
i2c_wdto_bit
:
std_logic
;
signal
i2c_wdto_bit_rst
:
std_logic
;
signal
i2c_wdto_bit_rst_ld
:
std_logic
;
signal
pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit_rst
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit_rst_ld
:
std_logic
;
signal
fwdg_pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
fwdg_pmisse_bit_rst
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
fwdg_pmisse_bit_rst_ld
:
std_logic
;
signal
pmisse_bits_or
:
std_logic
;
--signals for pulse counters
signal
rst_front_cnt
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
rst_
rear_cnt
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
pulse_cnt
:
t_pulse_cnt
;
signal
front_pulse_cnt
:
t_pulse_cnt
;
signal
rear_pulse_cnt
:
t_pulse_cnt
;
signal
front_pulse_cnt_offset
:
t_pulse_cnt
;
signal
rear_pulse_cnt_offset
:
t_pulse_cnt
;
signal
front_pulse_c
:
t_pulse_cnt
;
signal
rear_pulse_c
:
t_pulse_cnt
;
signal
ch_front_pcr
:
t_ch_pcr
;
signal
ch_front_pcr_ld
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
ch_rear_pcr
:
t_ch_pcr
;
signal
ch_rear_pcr_ld
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
mpt_ld
:
std_logic
;
signal
mpt
:
std_logic_vector
(
7
downto
0
);
signal
tvlr
:
std_logic_vector
(
31
downto
0
);
signal
tvlr_ld
:
std_logic
;
signal
tvhr
:
std_logic_vector
(
7
downto
0
);
signal
tvhr_ld
:
std_logic
;
signal
wrpres
:
std_logic
;
signal
i2c_err_bit
:
std_logic
;
signal
i2c_err_bit_rst
:
std_logic
;
signal
i2c_err_bit_rst_ld
:
std_logic
;
signal
line_front
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_rear
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_front_fs
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_rear_fs
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
sw_gp
:
std_logic_vector
(
7
downto
0
);
signal
sw_multicast
:
std_logic_vector
(
3
downto
0
);
signal
rst_unlock
:
std_logic
;
signal
rst_unlock_bit
:
std_logic
;
signal
rst_unlock_bit_ld
:
std_logic
;
signal
rst_bit
:
std_logic
;
signal
rst_bit_ld
:
std_logic
;
signal
rst_fr_reg
:
std_logic
;
signal
i2c_wdto_bit
:
std_logic
;
signal
i2c_wdto_bit_rst
:
std_logic
;
signal
i2c_wdto_bit_rst_ld
:
std_logic
;
signal
pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit_rst
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
flim_pmisse_bit_rst_ld
:
std_logic
;
signal
fwdg_pmisse_bit
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
fwdg_pmisse_bit_rst
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
fwdg_pmisse_bit_rst_ld
:
std_logic
;
signal
pmisse_bits_or
:
std_logic
;
-- Signals for pulse counters
signal
rst_
front_cnt
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
rst_rear_cnt
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
)
;
signal
front_pulse_cnt
:
t_pulse_cnt
;
signal
rear_pulse_cnt
:
t_pulse_cnt
;
signal
front_pulse_cnt_offset
:
t_pulse_cnt
;
signal
rear_pulse_cnt_offset
:
t_pulse_cnt
;
signal
front_pulse_c
:
t_pulse_cnt
;
signal
rear_pulse_c
:
t_pulse_cnt
;
signal
ch_front_pcr
:
t_ch_pcr
;
signal
ch_front_pcr_ld
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
ch_rear_pcr
:
t_ch_pcr
;
signal
ch_rear_pcr_ld
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
mpt_ld
:
std_logic
;
signal
mpt
:
std_logic_vector
(
7
downto
0
);
signal
tvlr
:
std_logic_vector
(
31
downto
0
);
signal
tvlr_ld
:
std_logic
;
signal
tvhr
:
std_logic_vector
(
7
downto
0
);
signal
tvhr_ld
:
std_logic
;
signal
wrpres
:
std_logic
;
signal
i2c_err_bit
:
std_logic
;
signal
i2c_err_bit_rst
:
std_logic
;
signal
i2c_err_bit_rst_ld
:
std_logic
;
signal
line_front
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_rear
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_front_fs
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
line_rear_fs
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
-- LED signals
signal
led_pulse
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
led_pulse_cnt
:
t_pulse_led_cnt
;
signal
led_inv_pulse
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
signal
led_inv_pulse_cnt
:
t_pulse_led_cnt
;
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
signal
led_i2c_blink
:
std_logic
;
signal
led_pulse
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
led_pulse_cnt
:
t_pulse_led_cnt
;
signal
led_inv_pulse
:
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
signal
led_inv_pulse_cnt
:
t_pulse_led_cnt
;
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
signal
led_i2c_blink
:
std_logic
;
-- Wishbone crossbar signals
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-1
downto
0
);
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_NR_MASTERS
-1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_NR_MASTERS
-1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_NR_SLAVES
-1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_NR_SLAVES
-1
downto
0
);
-- Time-tagging component signals
signal
tm_cycles
:
std_logic_vector
(
27
downto
0
);
signal
tm_tai
:
std_logic_vector
(
39
downto
0
);
signal
buf_wr_req_p
:
std_logic
;
signal
buf_rd_req_p
:
std_logic
;
signal
buf_count
:
std_logic_vector
(
f_log2_size
(
128
)
-1
downto
0
);
signal
buf_full
:
std_logic
;
signal
buf_empty
:
std_logic
;
signal
buf_chan
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
buf_wrtag
:
std_logic
;
signal
buf_clr_bit
:
std_logic
;
signal
buf_clr_bit_ld
:
std_logic
;
signal
buf_clr_p
:
std_logic
;
signal
buf_dat_in
:
std_logic_vector
(
c_tagbuff_data_width
-1
downto
0
);
signal
buf_dat_out
:
std_logic_vector
(
c_tagbuff_data_width
-1
downto
0
);
signal
tm_cycles
:
std_logic_vector
(
27
downto
0
);
signal
tm_tai
:
std_logic_vector
(
39
downto
0
);
signal
buf_wr_req_p
:
std_logic
;
signal
buf_rd_req_p
:
std_logic
;
signal
buf_count
:
std_logic_vector
(
f_log2_size
(
128
)
-1
downto
0
);
signal
buf_full
:
std_logic
;
signal
buf_empty
:
std_logic
;
signal
buf_chan
:
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
signal
buf_wrtag
:
std_logic
;
signal
buf_clr_bit
:
std_logic
;
signal
buf_clr_bit_ld
:
std_logic
;
signal
buf_clr_p
:
std_logic
;
signal
buf_dat_in
:
std_logic_vector
(
c_TAGBUFF_DATA_WIDTH
-1
downto
0
);
signal
buf_dat_out
:
std_logic_vector
(
c_TAGBUFF_DATA_WIDTH
-1
downto
0
);
-- Latest timestamp signals
signal
lts_ld_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_rdy_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_tai_125
:
t_lts_tai
;
signal
lts_cycles_125
:
t_lts_cycles
;
signal
lts_wrtag_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle_d0
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle_d1
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_20
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_tai_20
:
t_lts_tai
;
signal
lts_cycles_20
:
t_lts_cycles
;
signal
lts_wrtag_20
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_rdy_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_tai_125
:
t_lts_tai
;
signal
lts_cycles_125
:
t_lts_cycles
;
signal
lts_wrtag_125
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle_d0
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_toggle_d1
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_ld_20
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
signal
lts_tai_20
:
t_lts_tai
;
signal
lts_cycles_20
:
t_lts_cycles
;
signal
lts_wrtag_20
:
std_logic_vector
(
c_max_nr_chans
-1
downto
0
);
-- One-wire master signals
signal
owr_en
:
std_logic_vector
(
0
downto
0
);
signal
owr_in
:
std_logic_vector
(
0
downto
0
);
signal
pps_is_zero
:
std_logic
;
signal
tmp_id
:
std_logic_vector
(
63
downto
0
);
signal
tmp_temper
:
std_logic_vector
(
15
downto
0
);
signal
onewire_read_p
:
std_logic
;
signal
pps_load_p
:
std_logic
;
signal
id
:
std_logic_vector
(
63
downto
0
);
signal
temper
:
std_logic_vector
(
15
downto
0
);
--
Chipscope signals
signal
owr_en
:
std_logic_vector
(
0
downto
0
);
signal
owr_in
:
std_logic_vector
(
0
downto
0
);
signal
pps_is_zero
:
std_logic
;
signal
tmp_id
:
std_logic_vector
(
63
downto
0
);
signal
tmp_temper
:
std_logic_vector
(
15
downto
0
);
signal
onewire_read_p
:
std_logic
;
signal
pps_load_p
:
std_logic
;
signal
id
:
std_logic_vector
(
63
downto
0
);
signal
temper
:
std_logic_vector
(
15
downto
0
);
--
Chipscope signals
---------------------------------------------------------------------------------------------------
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0_in
:
std_logic_vector
(
7
downto
0
);
-- signal TRIG1_in : std_logic_vector(7 downto 0);
-- signal TRIG2_in : std_logic_vector(7 downto 0);
-- signal TRIG3_in : std_logic_vector(7 downto 0);
-- signal TRIG4_in : std_logic_vector(7 downto 0);
-- signal TRIG5_in : std_logic_vector(7 downto 0);
-- signal TRIG6_in : std_logic_vector(7 downto 0);
-- signal TRIG7_in : std_logic_vector(7 downto 0);
-- signal TRIG8_in : std_logic_vector(7 downto 0);
-- signal TRIG9_in : std_logic_vector(7 downto 0);
-- signal TRIG10_in : std_logic_vector(7 downto 0);
-- signal TRIG11_in : std_logic_vector(7 downto 0);
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0_in
:
std_logic_vector
(
7
downto
0
);
-- signal TRIG1_in
: std_logic_vector(7 downto 0);
-- signal TRIG2_in
: std_logic_vector(7 downto 0);
-- signal TRIG3_in
: std_logic_vector(7 downto 0);
-- signal TRIG4_in
: std_logic_vector(7 downto 0);
-- signal TRIG5_in
: std_logic_vector(7 downto 0);
-- signal TRIG6_in
: std_logic_vector(7 downto 0);
-- signal TRIG7_in
: std_logic_vector(7 downto 0);
-- signal TRIG8_in
: std_logic_vector(7 downto 0);
-- signal TRIG9_in
: std_logic_vector(7 downto 0);
-- signal TRIG10_in
: std_logic_vector(7 downto 0);
-- signal TRIG11_in
: std_logic_vector(7 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
...
...
@@ -509,18 +474,18 @@ begin
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0_in(0) <= pulse_outp_err_sh_p(5);
-- TRIG0_in(1) <= burst_outp_err_sh_p(5);
-- TRIG0_in(2) <= trig_pgen(5);
-- TRIG0_in(3) <= pulse_outp_sh(5);
-- TRIG0_in(4) <= pulse_outp_err_lg_p(5);
-- TRIG0_in(5) <= burst_outp_err_lg_p(5);
-- TRIG0_in(5) <= burst_outp_err_lg_p(5);
-- TRIG0_in(6) <= pulse_outp_lg(5);
-- TRIG0_in(7) <= ch_front_pcr_ld(5);
--============================================================================
-- Differential input buffer for 125 MHz clock
...
...
@@ -543,12 +508,13 @@ begin
-- External reset input to reset generator
rst_ext
<=
rst_fr_reg
or
(
not
vme_sysreset_n_i
);
-- Configure reset generator for 100ms reset
cmp_reset_gen
:
conv_reset_gen
generic
map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time
=>
2
*
(
10
**
6
)
g_RESET_TIME
=>
g_RST_TIME
)
port
map
(
...
...
@@ -579,11 +545,11 @@ begin
--============================================================================
-- Enable outputs only when the FPGA is ready to handle them
-- One clock cycle delay from global OEN to rest of OENs
p_delay_oen
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
global_oen
<=
'0'
;
front_oen
<=
'0'
;
invttl_oen
<=
'0'
;
...
...
@@ -613,13 +579,13 @@ begin
trig_a
<=
pulse_i
;
--------------------------------------------------------------------------------
gen_man_trig
:
if
(
g_with_man_trig
=
true
)
generate
gen_man_trig
:
if
g_WITH_MAN_TRIG
=
true
generate
-- Manual trigger logic
cmp_man_trig
:
conv_man_trig
cmp_man_trig
:
conv_man_trig
generic
map
(
g_nr_chan
=>
g_
nr_chans
,
g_pwidth
=>
g_
man_trig_pwidth
g_nr_chan
=>
g_
NR_CHANS
,
g_pwidth
=>
g_
MAN_TRIG_PWIDTH
)
port
map
(
...
...
@@ -629,22 +595,22 @@ begin
reg_i
=>
mpt
,
trig_o
=>
trig_man
);
end
generate
gen_man_trig
;
end
generate
gen_man_trig
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_no_man_trig
:
if
(
g_with_man_trig
=
false
)
generate
trig_man
<=
(
others
=>
'0'
);
end
generate
gen_no_man_trig
;
gen_no_man_trig
:
if
g_WITH_MAN_TRIG
=
false
generate
trig_man
<=
(
others
=>
'0'
);
end
generate
gen_no_man_trig
;
--------------------------------------------------------------------------------
-- Glitch filter
--------------------------------------------------------------------------------
gen_pulse_chan_logic
:
for
i
in
0
to
g_nr_chans
-1
generate
gen_pulse_chan_logic
:
for
i
in
0
to
g_NR_CHANS
-1
generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
cmp_trig_sync
:
gc_sync_ffs
cmp_trig_sync
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
...
...
@@ -658,10 +624,10 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
);
-- Deglitch synchronized trigger signal
cmp_inp_glitch_filt
:
gc_glitch_filt
cmp_inp_glitch_filt
:
gc_glitch_filt
generic
map
(
g_len
=>
g_
pgen_gf_len
g_len
=>
g_
PGEN_GF_LEN
)
port
map
(
...
...
@@ -673,13 +639,13 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan
(
i
)
<=
trig_a
(
i
)
when
(
gf_en_n_i
=
'1'
)
else
trig_chan
(
i
)
<=
trig_a
(
i
)
when
gf_en_n_i
=
'1'
else
trig_degl
(
i
);
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen
(
i
)
<=
trig_chan
(
i
)
or
trig_man
(
i
);
trig_pgen
(
i
)
<=
trig_chan
(
i
)
or
trig_man
(
i
);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- The pulse counter is triggered only by a pulse that actually makes it
...
...
@@ -688,8 +654,8 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and should have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs
:
gc_sync_ffs
cmp_sync_ffs
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_20_i
,
...
...
@@ -699,408 +665,361 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
npulse_o
=>
trig_chan_fedge_p
(
i
)
);
--------------------------------------------------------------------------------
-- Pulse counters:
--------------------------------------------------------------------------------
-- Use Flacter based fast counters to count fast pulses
-- See for more details https://www.doulos.com/knowhow/fpga/fastcounter/
-- The counter below has additional integer output value of the counter plus a
-- The counter below has additional integer output value of the counter plus a
-- reset signal that depends on the system reset in addition to the counter load pulse
--------------------------------------------------------------------------------
gen_pulse_cnt
:
if
(
g_with_pulse_cnt
=
true
)
generate
rst_front_cnt
(
i
)
<=
rst_20
or
ch_front_pcr_ld
(
i
);
rst_rear_cnt
(
i
)
<=
rst_20
or
ch_rear_pcr_ld
(
i
);
cmp_pulse_cnt_front
:
fastevent_counter
port
map
(
sysclk_i
=>
clk_20_i
,
rstcount_i
=>
rst_front_cnt
(
i
),
en_i
=>
'1'
,
trig_i
=>
pulse_front_i
(
i
),
count_int_o
=>
front_pulse_c
(
i
)
);
cmp_pulse_cnt_rear
:
fastevent_counter
port
map
(
sysclk_i
=>
clk_20_i
,
rstcount_i
=>
rst_rear_cnt
(
i
),
en_i
=>
'1'
,
trig_i
=>
pulse_rear_i
(
i
),
count_int_o
=>
rear_pulse_c
(
i
)
);
-- First, the pulse counters for the used channels (up to g_nr_chans)
p_pulse_cnt
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
gen_pulse_cnt
:
if
g_WITH_PULSE_CNT
=
true
generate
rst_front_cnt
(
i
)
<=
rst_20
or
ch_front_pcr_ld
(
i
);
rst_rear_cnt
(
i
)
<=
rst_20
or
ch_rear_pcr_ld
(
i
);
cmp_pulse_cnt_front
:
fastevent_counter
port
map
(
sysclk_i
=>
clk_20_i
,
rstcount_i
=>
rst_front_cnt
(
i
),
en_i
=>
'1'
,
trig_i
=>
pulse_front_i
(
i
),
count_int_o
=>
front_pulse_c
(
i
));
cmp_pulse_cnt_rear
:
fastevent_counter
port
map
(
sysclk_i
=>
clk_20_i
,
rstcount_i
=>
rst_rear_cnt
(
i
),
en_i
=>
'1'
,
trig_i
=>
pulse_rear_i
(
i
),
count_int_o
=>
rear_pulse_c
(
i
));
-- First, the pulse counters for the used channels (up to g_NR_CHANS)
p_pulse_cnt
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
rst_20_n
=
'0'
then
front_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
rear_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
front_pulse_cnt_offset
(
i
)
<=
(
others
=>
'0'
);
rear_pulse_cnt_offset
(
i
)
<=
(
others
=>
'0'
);
elsif
(
ch_front_pcr_ld
(
i
)
=
'1'
)
then
front_pulse_cnt_offset
(
i
)
<=
unsigned
(
ch_front_pcr
(
i
));
elsif
(
ch_rear_pcr_ld
(
i
)
=
'1'
)
then
rear_pulse_cnt_offset
(
i
)
<=
unsigned
(
ch_rear_pcr
(
i
));
else
front_pulse_cnt
(
i
)
<=
front_pulse_cnt_offset
(
i
)
+
front_pulse_c
(
i
);
rear_pulse_cnt
(
i
)
<=
rear_pulse_cnt_offset
(
i
)
+
rear_pulse_c
(
i
);
elsif
ch_front_pcr_ld
(
i
)
=
'1'
then
front_pulse_cnt_offset
(
i
)
<=
unsigned
(
ch_front_pcr
(
i
));
elsif
ch_rear_pcr_ld
(
i
)
=
'1'
then
rear_pulse_cnt_offset
(
i
)
<=
unsigned
(
ch_rear_pcr
(
i
));
else
front_pulse_cnt
(
i
)
<=
front_pulse_cnt_offset
(
i
)
+
front_pulse_c
(
i
);
rear_pulse_cnt
(
i
)
<=
rear_pulse_cnt_offset
(
i
)
+
rear_pulse_c
(
i
);
end
if
;
end
if
;
end
if
;
end
process
p_pulse_cnt
;
end
process
p_pulse_cnt
;
--------------------------------------------------------------------------------
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans
:
if
(
g_nr_chans
<
c_max_nr_chans
)
generate
pulse_cnt
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
front_pulse_cnt
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
rear_pulse_cnt
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
end
generate
gen_pulse_cnt_unused_chans
;
--------------------------------------------------------------------------------
gen_pulse_cnt_unused_chans
:
if
g_NR_CHANS
<
c_max_nr_chans
generate
front_pulse_cnt
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
rear_pulse_cnt
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
end
generate
gen_pulse_cnt
;
end
generate
gen_pulse_cnt_unused_chans
;
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation
end
generate
gen_pulse_cnt
;
--
-------------------------------------------------------------------------------------------------
-- CONTINUOUS MODE
--
Instantiate pulse generator alone for
CONTINUOUS MODE
-------------------
--
Instantiate pulse generator block for continuous operation without burst feature
cmp_pulse_gen_cont
:
conv_pulse_gen
--
Instantiate pulse generator block for continuous operation without burst feature
cmp_pulse_gen_cont
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
g_
pgen_fixed_width
,
g_pwidth
=>
g_
pgen_pwidth_lg
,
g_pperiod
=>
g_
pgen_pperiod_cont
g_with_fixed_pwidth
=>
g_
PGEN_FIXED_WIDTH
,
g_pwidth
=>
g_
PGEN_PWIDTH_LG
,
g_pperiod
=>
g_
PGEN_PPERIOD_CONT
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_cont
(
i
),
pulse_o
=>
pulse_outp_cont
(
i
)
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_cont
(
i
),
pulse_o
=>
pulse_outp_cont
(
i
)
);
----------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for
long
pulse operation
-- Instantiate pulse generator + burst controller block for the channel for
LONG
pulse operation
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH LONG PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
--
Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_lg
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
g_
pgen_fixed_width
,
g_pwidth
=>
g_
pgen_pwidth_lg
,
g_pperiod
=>
g_
pgen_pperiod_lg
g_with_fixed_pwidth
=>
g_
PGEN_FIXED_WIDTH
,
g_pwidth
=>
g_
PGEN_PWIDTH_LG
,
g_pperiod
=>
g_
PGEN_PPERIOD_LG
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_lg_p
(
i
),
pulse_o
=>
pulse_outp_lg
(
i
),
pulse_r_edge_p_o
=>
pulse_r_edge_lg_p
(
i
),
pulse_f_edge_p_o
=>
pulse_f_edge_lg_p
(
i
)
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_lg_p
(
i
),
pulse_o
=>
pulse_outp_lg
(
i
),
pulse_r_edge_p_o
=>
pulse_r_edge_lg_p
(
i
),
pulse_f_edge_p_o
=>
pulse_f_edge_lg_p
(
i
)
);
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_lg
:
conv_dyn_burst_ctrl
generic
map
(
g_pwidth
=>
g_pgen_pwidth_lg
,
g_temp_decre_step
=>
g_temp_decre_step_lg
,
g_1_pulse_temp_rise
=>
g_burstctrl_1_pulse_temp_rise_lg
,
g_max_temp
=>
g_burstctrl_max_temp_lg_sh
g_pwidth
=>
g_PGEN_PWIDTH_LG
,
g_temp_decre_step
=>
g_TEMP_DECRE_STEP_LG
,
g_1_pulse_temp_rise
=>
g_BURSTCTRL_1_PULSE_TEMP_RISE_LG
,
g_max_temp
=>
g_BURSTCTRL_MAX_TEMP_LG_SH
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
en_i
=>
'1'
,
pulse_burst_i
=>
pulse_outp_lg
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_lg_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_lg_p
(
i
),
temp_rise_o
=>
temp_rise_c_lg
(
i
),
pulse_burst_o
=>
burst_outp_lg
(
i
),
burst_err_p_o
=>
burst_outp_err_lg_p
(
i
)
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
en_i
=>
'1'
,
pulse_burst_i
=>
pulse_outp_lg
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_lg_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_lg_p
(
i
),
temp_rise_o
=>
temp_rise_c_lg
(
i
),
pulse_burst_o
=>
burst_outp_lg
(
i
),
burst_err_p_o
=>
burst_outp_err_lg_p
(
i
)
);
----------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for SHORT pulse operation
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH SHORT PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_sh
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
g_pgen_fixed_width
,
g_pwidth
=>
g_pgen_pwidth_sh
,
g_pperiod
=>
g_pgen_pperiod_sh
-- Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_sh
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
g_PGEN_FIXED_WIDTH
,
g_pwidth
=>
g_PGEN_PWIDTH_SH
,
g_pperiod
=>
g_PGEN_PPERIOD_SH
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_sh_p
(
i
),
pulse_o
=>
pulse_outp_sh
(
i
),
pulse_r_edge_p_o
=>
pulse_r_edge_sh_p
(
i
)
,
pulse_f_edge_p_o
=>
pulse_f_edge_sh_p
(
i
)
);
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
gf_en_n_i
,
en_i
=>
'1'
,
trig_a_i
=>
trig_pgen
(
i
),
trig_r_edge_p_i
=>
trig_chan_redge_p
(
i
),
trig_f_edge_p_i
=>
trig_chan_fedge_p
(
i
),
pulse_err_p_o
=>
pulse_outp_err_sh_p
(
i
),
pulse_o
=>
pulse_outp_sh
(
i
),
pulse_r_edge_p_o
=>
pulse_r_edge_sh_p
(
i
),
pulse_f_edge_p_o
=>
pulse_f_edge_sh_p
(
i
));
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_sh
:
conv_dyn_burst_ctrl
generic
map
(
g_pwidth
=>
g_pgen_pwidth_sh
,
g_temp_decre_step
=>
g_temp_decre_step_sh
,
g_1_pulse_temp_rise
=>
g_burstctrl_1_pulse_temp_rise_sh
,
g_max_temp
=>
g_burstctrl_max_temp_lg_sh
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
en_i
=>
'1'
,
pulse_burst_i
=>
pulse_outp_sh
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_sh_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_sh_p
(
i
),
temp_rise_o
=>
temp_rise_c_sh
(
i
),
pulse_burst_o
=>
burst_outp_sh
(
i
),
burst_err_p_o
=>
burst_outp_err_sh_p
(
i
)
generic
map
(
g_pwidth
=>
g_PGEN_PWIDTH_SH
,
g_temp_decre_step
=>
g_TEMP_DECRE_STEP_SH
,
g_1_pulse_temp_rise
=>
g_BURSTCTRL_1_PULSE_TEMP_RISE_SH
,
g_max_temp
=>
g_BURSTCTRL_MAX_TEMP_LG_SH
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
en_i
=>
'1'
,
pulse_burst_i
=>
pulse_outp_sh
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_sh_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_sh_p
(
i
),
temp_rise_o
=>
temp_rise_c_sh
(
i
),
pulse_burst_o
=>
burst_outp_sh
(
i
),
burst_err_p_o
=>
burst_outp_err_sh_p
(
i
)
);
----------------------------------------------------------------------
--Select output depending on mode of operation.
--
Select output depending on mode of operation.
----------------------------------------------------------------------
pulse_outp
(
i
)
<=
(
burst_outp_lg
(
i
)
and
pulse_width_sel_n_i
)
or
(
burst_outp_sh
(
i
)
and
not
pulse_width_sel_n_i
)
(
burst_outp_sh
(
i
)
and
not
pulse_width_sel_n_i
)
when
burst_en_n
=
'0'
else
pulse_outp_cont
(
i
);
----------------------------------------------------------------------
--Generate error pulses depending on mode of operation
--
Generate error pulses depending on mode of operation
----------------------------------------------------------------------
-- flim_pmisse_p gives out a pulse when a pulse is missed because its
-- frequency is above the set maximum frequency
flim_pmisse_p
(
i
)
<=
(
pulse_outp_err_lg_p
(
i
)
and
pulse_width_sel_n_i
)
or
(
pulse_outp_err_sh_p
(
i
)
and
not
pulse_width_sel_n_i
)
(
pulse_outp_err_sh_p
(
i
)
and
not
pulse_width_sel_n_i
)
when
burst_en_n
=
'0'
else
pulse_outp_err_cont
(
i
)
;
-- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the
else
pulse_outp_err_cont
(
i
);
-- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the
-- frequency watchdog only supports a high frequency for a limited period
fwdg_pmisse_p
(
i
)
<=
(
burst_outp_err_lg_p
(
i
)
and
pulse_width_sel_n_i
)
or
(
burst_outp_err_sh_p
(
i
)
and
not
pulse_width_sel_n_i
)
(
burst_outp_err_sh_p
(
i
)
and
not
pulse_width_sel_n_i
)
when
burst_en_n
=
'0'
else
'0'
;
pmisse_p
(
i
)
<=
flim_pmisse_p
(
i
)
or
fwdg_pmisse_p
(
i
);
else
'0'
;
pmisse_p
(
i
)
<=
flim_pmisse_p
(
i
)
or
fwdg_pmisse_p
(
i
);
-----------------------------------------------------------------------
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
pulse_outp_d0
(
i
)
<=
'0'
;
pulse_outp_redge_p
(
i
)
<=
'0'
;
led_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
led_pulse
(
i
)
<=
'0'
;
else
pulse_outp_d0
(
i
)
<=
pulse_outp
(
i
);
pulse_outp_redge_p
(
i
)
<=
pulse_outp
(
i
)
and
(
not
pulse_outp_d0
(
i
));
case
led_pulse
(
i
)
is
when
'0'
=>
if
(
pulse_outp_redge_p
(
i
)
=
'1'
)
then
led_pulse
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
led_pulse_cnt
(
i
)
<=
led_pulse_cnt
(
i
)
+
1
;
if
(
led_pulse_cnt
(
i
)
=
(
led_pulse_cnt
(
i
)
'range
=>
'1'
))
then
p_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
rst_20_n
=
'0'
then
pulse_outp_d0
(
i
)
<=
'0'
;
pulse_outp_redge_p
(
i
)
<=
'0'
;
led_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
led_pulse
(
i
)
<=
'0'
;
else
pulse_outp_d0
(
i
)
<=
pulse_outp
(
i
);
pulse_outp_redge_p
(
i
)
<=
pulse_outp
(
i
)
and
(
not
pulse_outp_d0
(
i
));
case
led_pulse
(
i
)
is
when
'0'
=>
if
pulse_outp_redge_p
(
i
)
=
'1'
then
led_pulse
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
led_pulse_cnt
(
i
)
<=
led_pulse_cnt
(
i
)
+
1
;
if
led_pulse_cnt
(
i
)
=
(
led_pulse_cnt
(
i
)
'range
=>
'1'
)
then
led_pulse
(
i
)
<=
'0'
;
end
if
;
when
others
=>
led_pulse
(
i
)
<=
'0'
;
end
if
;
when
others
=>
led_pulse
(
i
)
<=
'0'
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
p_pulse_led
;
end
process
p_pulse_led
;
end
generate
gen_pulse_chan_logic
;
end
generate
gen_pulse_chan_logic
;
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
gen_inv_ttl_leds
:
for
i
in
0
to
g_nr_inv_chans
-1
generate
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
-- INV-TTL outputs
inv_pulse_outp
(
i
)
<=
inv_pulse_i_n
(
i
);
inv_pulse_o
(
i
)
<=
inv_pulse_outp
(
i
);
gen_inv_ttl_leds
:
for
i
in
0
to
g_NR_INV_CHANS
-1
generate
p_inv_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
inv_pulse_outp_d0
(
i
)
<=
'0'
;
inv_pulse_outp_fedge_p
(
i
)
<=
'0'
;
led_inv_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
led_inv_pulse
(
i
)
<=
'0'
;
else
inv_pulse_outp_d0
(
i
)
<=
inv_pulse_outp
(
i
);
inv_pulse_outp_fedge_p
(
i
)
<=
(
not
inv_pulse_outp
(
i
))
and
inv_pulse_outp_d0
(
i
);
case
led_inv_pulse
(
i
)
is
when
'0'
=>
if
(
inv_pulse_outp_fedge_p
(
i
)
=
'1'
)
then
led_inv_pulse
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
led_inv_pulse_cnt
(
i
)
<=
led_inv_pulse_cnt
(
i
)
+
1
;
if
(
led_inv_pulse_cnt
(
i
)
=
(
led_inv_pulse_cnt
(
i
)
'range
=>
'1'
))
then
-- INV-TTL outputs
inv_pulse_outp
(
i
)
<=
inv_pulse_n_i
(
i
);
inv_pulse_o
(
i
)
<=
inv_pulse_outp
(
i
);
p_inv_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
rst_20_n
=
'0'
then
inv_pulse_outp_d0
(
i
)
<=
'0'
;
inv_pulse_outp_fedge_p
(
i
)
<=
'0'
;
led_inv_pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
led_inv_pulse
(
i
)
<=
'0'
;
else
inv_pulse_outp_d0
(
i
)
<=
inv_pulse_outp
(
i
);
inv_pulse_outp_fedge_p
(
i
)
<=
(
not
inv_pulse_outp
(
i
))
and
inv_pulse_outp_d0
(
i
);
case
led_inv_pulse
(
i
)
is
when
'0'
=>
if
inv_pulse_outp_fedge_p
(
i
)
=
'1'
then
led_inv_pulse
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
led_inv_pulse_cnt
(
i
)
<=
led_inv_pulse_cnt
(
i
)
+
1
;
if
led_inv_pulse_cnt
(
i
)
=
(
led_inv_pulse_cnt
(
i
)
'range
=>
'1'
)
then
led_inv_pulse
(
i
)
<=
'0'
;
end
if
;
when
others
=>
led_inv_pulse
(
i
)
<=
'0'
;
end
if
;
when
others
=>
led_inv_pulse
(
i
)
<=
'0'
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
p_inv_pulse_led
;
end
generate
gen_inv_ttl_leds
;
end
process
p_inv_pulse_led
;
end
generate
gen_inv_ttl_leds
;
--------------------------------------------------------------------------------
gen_pulse_timetag
:
if
(
g_with_pulse_timetag
=
true
)
generate
cmp_pulse_timetag
:
conv_pulse_timetag
generic
map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate
=>
125000000
,
-- Number of repetition channels
g_nr_chan
=>
g_nr_chans
)
port
map
(
gen_pulse_timetag
:
if
g_WITH_PULSE_TIMETAG
=
true
generate
cmp_pulse_timetag
:
conv_pulse_timetag
generic
map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate
=>
125000000
,
-- Number of repetition channels
g_nr_chan
=>
g_NR_CHANS
)
port
map
(
-- Clock and active-low reset
clk_i
=>
clk_125
,
rst_n_i
=>
rst_125_n
,
clk_i
=>
clk_125
,
rst_n_i
=>
rst_125_n
,
-- Asynchronous pulse input
pulse_a_i
=>
trig_chan
,
pulse_a_i
=>
trig_chan
,
-- Time inputs from White Rabbit
wr_tm_cycles_i
=>
(
others
=>
'0'
),
wr_tm_tai_i
=>
(
others
=>
'0'
),
wr_tm_valid_i
=>
'0'
,
wr_tm_cycles_i
=>
(
others
=>
'0'
),
wr_tm_tai_i
=>
(
others
=>
'0'
),
wr_tm_valid_i
=>
'0'
,
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i
=>
tvlr
,
wb_tm_tai_l_ld_i
=>
tvlr_ld
,
wb_tm_tai_h_i
=>
tvhr
,
wb_tm_tai_h_ld_i
=>
tvhr_ld
,
wb_tm_tai_l_i
=>
tvlr
,
wb_tm_tai_l_ld_i
=>
tvlr_ld
,
wb_tm_tai_h_i
=>
tvhr
,
wb_tm_tai_h_ld_i
=>
tvhr_ld
,
-- Timing outputs
tm_cycles_o
=>
tm_cycles
,
tm_tai_o
=>
tm_tai
,
tm_wrpres_o
=>
buf_wrtag
,
chan_p_o
=>
buf_chan
,
tm_cycles_o
=>
tm_cycles
,
tm_tai_o
=>
tm_tai
,
tm_wrpres_o
=>
buf_wrtag
,
chan_p_o
=>
buf_chan
,
-- Ring buffer I/O
buf_wr_req_p_o
=>
buf_wr_req_p
buf_wr_req_p_o
=>
buf_wr_req_p
);
--------------------------------------------------------------------------------
gen_buf_chan
:
if
(
g_nr_chans
=
c_max_nr_chans
)
generate
buf_dat_in
(
c_max_nr_chans
-1
downto
0
)
<=
buf_chan
;
end
generate
gen_buf_chan
;
gen_buf_chan_unused_chans
:
if
(
g_nr_chans
<
c_max_nr_chans
)
generate
buf_dat_in
(
g_nr_chans
-1
downto
0
)
<=
buf_chan
;
buf_dat_in
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
end
generate
gen_buf_chan_unused_chans
;
gen_buf_chan
:
if
g_NR_CHANS
=
c_max_nr_chans
generate
buf_dat_in
(
c_max_nr_chans
-1
downto
0
)
<=
buf_chan
;
end
generate
gen_buf_chan
;
gen_buf_chan_unused_chans
:
if
g_NR_CHANS
<
c_max_nr_chans
generate
buf_dat_in
(
g_NR_CHANS
-1
downto
0
)
<=
buf_chan
;
buf_dat_in
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
end
generate
gen_buf_chan_unused_chans
;
--------------------------------------------------------------------------------
buf_dat_in
(
6
)
<=
buf_wrtag
;
buf_dat_in
(
34
downto
7
)
<=
tm_cycles
;
buf_dat_in
(
74
downto
35
)
<=
tm_tai
;
buf_dat_in
(
6
)
<=
buf_wrtag
;
buf_dat_in
(
34
downto
7
)
<=
tm_cycles
;
buf_dat_in
(
74
downto
35
)
<=
tm_tai
;
-- Instantiate the ring buffer
cmp_ring_buf
:
conv_ring_buf
generic
map
(
g_data_width
=>
c_tagbuff_data_width
,
g_size
=>
128
)
port
map
(
cmp_ring_buf
:
conv_ring_buf
generic
map
(
g_data_width
=>
c_TAGBUFF_DATA_WIDTH
,
g_size
=>
128
)
port
map
(
-- Clocks and reset
clk_rd_i
=>
clk_20_i
,
clk_wr_i
=>
clk_125
,
rst_n_a_i
=>
rst_20_n
,
clk_rd_i
=>
clk_20_i
,
clk_wr_i
=>
clk_125
,
rst_n_a_i
=>
rst_20_n
,
-- Buffer inputs
buf_dat_i
=>
buf_dat_in
,
buf_rd_req_i
=>
buf_rd_req_p
,
buf_wr_req_i
=>
buf_wr_req_p
,
buf_clr_i
=>
buf_clr_p
,
buf_dat_i
=>
buf_dat_in
,
buf_rd_req_i
=>
buf_rd_req_p
,
buf_wr_req_i
=>
buf_wr_req_p
,
buf_clr_i
=>
buf_clr_p
,
-- Buffer outputs
buf_dat_o
=>
buf_dat_out
,
buf_full_o
=>
buf_full
,
buf_empty_o
=>
buf_empty
,
buf_count_o
=>
buf_count
);
end
generate
gen_pulse_timetag
;
buf_dat_o
=>
buf_dat_out
,
buf_full_o
=>
buf_full
,
buf_empty_o
=>
buf_empty
,
buf_count_o
=>
buf_count
);
end
generate
gen_pulse_timetag
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Channel output assignments
pulse_o
<=
pulse_outp
;
led_pulse_o
<=
led_pulse
;
pulse_o
<=
pulse_outp
;
led_pulse_o
<=
led_pulse
;
led_inv_pulse_o
<=
led_inv_pulse
;
--============================================================================
...
...
@@ -1155,8 +1074,7 @@ end generate gen_pulse_timetag;
wbm_adr_o
=>
xbar_slave_in
(
0
)
.
adr
,
wbm_ack_i
=>
xbar_slave_out
(
0
)
.
ack
,
wbm_rty_i
=>
xbar_slave_out
(
0
)
.
rty
,
wbm_err_i
=>
xbar_slave_out
(
0
)
.
err
);
wbm_err_i
=>
xbar_slave_out
(
0
)
.
err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
...
...
@@ -1165,7 +1083,7 @@ end generate gen_pulse_timetag;
p_i2c_blink
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
led_i2c_clkdiv
<=
(
others
=>
'0'
);
led_i2c_cnt
<=
(
others
=>
'0'
);
led_i2c
<=
'0'
;
...
...
@@ -1175,17 +1093,17 @@ end generate gen_pulse_timetag;
when
'0'
=>
led_i2c
<=
'0'
;
if
(
i2c_tip
=
'1'
)
then
if
i2c_tip
=
'1'
then
led_i2c_blink
<=
'1'
;
end
if
;
when
'1'
=>
led_i2c_clkdiv
<=
led_i2c_clkdiv
+
1
;
if
(
led_i2c_clkdiv
=
399999
)
then
if
led_i2c_clkdiv
=
399999
then
led_i2c_clkdiv
<=
(
others
=>
'0'
);
led_i2c_cnt
<=
led_i2c_cnt
+
1
;
led_i2c
<=
not
led_i2c
;
if
(
led_i2c_cnt
=
7
)
then
if
led_i2c_cnt
=
7
then
led_i2c_cnt
<=
(
others
=>
'0'
);
led_i2c_blink
<=
'0'
;
end
if
;
...
...
@@ -1206,9 +1124,9 @@ end generate gen_pulse_timetag;
p_sr_wdto_bit
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
i2c_wdto_bit
<=
'0'
;
elsif
(
i2c_wdto_p
=
'1'
)
then
elsif
i2c_wdto_p
=
'1'
then
i2c_wdto_bit
<=
'1'
;
elsif
(
i2c_wdto_bit_rst_ld
=
'1'
)
and
(
i2c_wdto_bit_rst
=
'1'
)
then
i2c_wdto_bit
<=
'0'
;
...
...
@@ -1220,9 +1138,9 @@ end generate gen_pulse_timetag;
p_i2c_err_led
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
i2c_err_bit
<=
'0'
;
elsif
(
i2c_err_p
=
'1'
)
then
elsif
i2c_err_p
=
'1'
then
i2c_err_bit
<=
'1'
;
elsif
(
i2c_err_bit_rst_ld
=
'1'
)
and
(
i2c_err_bit_rst
=
'1'
)
then
i2c_err_bit
<=
'0'
;
...
...
@@ -1236,12 +1154,12 @@ end generate gen_pulse_timetag;
cmp_wb_crossbar
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_
nr_masters
,
g_num_slaves
=>
c_
nr_slaves
,
g_num_masters
=>
c_
NR_MASTERS
,
g_num_slaves
=>
c_
NR_SLAVES
,
g_registered
=>
false
,
g_wraparound
=>
true
,
g_layout
=>
c_
sdb_layout
,
g_sdb_addr
=>
c_
addr_sdb
g_layout
=>
c_
SDB_LAYOUT
,
g_sdb_addr
=>
c_
ADDR_SDB
)
port
map
(
...
...
@@ -1260,38 +1178,38 @@ end generate gen_pulse_timetag;
rtm_lines
<=
rtmp_i
&
rtmm_i
;
--------------------------------------------------------------------------------
gen_line
:
if
(
g_nr_chans
=
c_max_nr_chans
)
generate
line_front
<=
line_front_i
;
line_rear
<=
line_rear_i
;
line_front_fs
<=
line_front_fs_i
;
line_rear_fs
<=
line_rear_fs_i
;
end
generate
gen_line
;
gen_line
:
if
g_NR_CHANS
=
c_max_nr_chans
generate
line_front
<=
line_front_i
;
line_rear
<=
line_rear_i
;
line_front_fs
<=
line_front_fs_i
;
line_rear_fs
<=
line_rear_fs_i
;
end
generate
gen_line
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_line_unused_chans
:
if
(
g_nr_chans
<
c_max_nr_chans
)
generate
gen_line_unused_chans
:
if
g_NR_CHANS
<
c_max_nr_chans
generate
-- connect used lines
line_front
(
g_nr_chans
-1
downto
0
)
<=
line_front_i
;
line_rear
(
g_nr_chans
-1
downto
0
)
<=
line_rear_i
;
line_front_fs
(
g_nr_chans
-1
downto
0
)
<=
line_front_fs_i
;
line_rear_fs
(
g_nr_chans
-1
downto
0
)
<=
line_rear_fs_i
;
line_front
(
g_NR_CHANS
-1
downto
0
)
<=
line_front_i
;
line_rear
(
g_NR_CHANS
-1
downto
0
)
<=
line_rear_i
;
line_front_fs
(
g_NR_CHANS
-1
downto
0
)
<=
line_front_fs_i
;
line_rear_fs
(
g_NR_CHANS
-1
downto
0
)
<=
line_rear_fs_i
;
-- unused lines to zeroes
line_front
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
line_rear
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
line_front_fs
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
line_rear_fs
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
end
generate
gen_line_unused_chans
;
line_front
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
line_rear
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
line_front_fs
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
line_rear_fs
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
end
generate
gen_line_unused_chans
;
--------------------------------------------------------------------------------
-- Implement the RST_UNLOCK bit
p_rst_unlock
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
rst_unlock
<=
'0'
;
elsif
(
rst_unlock_bit_ld
=
'1'
)
then
if
(
rst_unlock_bit
=
'1'
)
then
elsif
rst_unlock_bit_ld
=
'1'
then
if
rst_unlock_bit
=
'1'
then
rst_unlock
<=
'1'
;
else
rst_unlock
<=
'0'
;
...
...
@@ -1305,7 +1223,7 @@ end generate gen_line_unused_chans;
p_rst_fr_reg
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
rst_fr_reg
<=
'0'
;
elsif
(
rst_bit_ld
=
'1'
)
and
(
rst_bit
=
'1'
)
and
(
rst_unlock
=
'1'
)
then
rst_fr_reg
<=
'1'
;
...
...
@@ -1320,62 +1238,60 @@ end generate gen_line_unused_chans;
p_err_pmisse_bit
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
for
i
in
0
to
g_
nr_chans
-1
loop
if
(
rst_20_n
=
'0'
)
then
for
i
in
0
to
g_
NR_CHANS
-1
loop
if
rst_20_n
=
'0'
then
flim_pmisse_bit
(
i
)
<=
'0'
;
fwdg_pmisse_bit
(
i
)
<=
'0'
;
fwdg_pmisse_bit
(
i
)
<=
'0'
;
pmisse_bit
(
i
)
<=
'0'
;
elsif
(
pmisse_p
(
i
)
=
'1'
)
then
elsif
pmisse_p
(
i
)
=
'1'
then
if
flim_pmisse_p
(
i
)
=
'1'
then
flim_pmisse_bit
(
i
)
<=
'1'
;
flim_pmisse_bit
(
i
)
<=
'1'
;
end
if
;
if
fwdg_pmisse_p
(
i
)
=
'1'
then
fwdg_pmisse_bit
(
i
)
<=
'1'
;
end
if
;
else
if
(
flim_pmisse_bit_rst_ld
=
'1'
)
and
(
flim_pmisse_bit_rst
(
i
)
=
'1'
)
then
flim_pmisse_bit
(
i
)
<=
'0'
;
end
if
;
if
(
fwdg_pmisse_bit_rst_ld
=
'1'
)
and
(
fwdg_pmisse_bit_rst
(
i
)
=
'1'
)
then
fwdg_pmisse_bit
(
i
)
<=
'0'
;
end
if
;
else
if
(
flim_pmisse_bit_rst_ld
=
'1'
)
and
(
flim_pmisse_bit_rst
(
i
)
=
'1'
)
then
flim_pmisse_bit
(
i
)
<=
'0'
;
end
if
;
if
(
fwdg_pmisse_bit_rst_ld
=
'1'
)
and
(
fwdg_pmisse_bit_rst
(
i
)
=
'1'
)
then
fwdg_pmisse_bit
(
i
)
<=
'0'
;
end
if
;
end
if
;
pmisse_bit
(
i
)
<=
flim_pmisse_bit
(
i
)
or
fwdg_pmisse_bit
(
i
);
pmisse_bit
(
i
)
<=
flim_pmisse_bit
(
i
)
or
fwdg_pmisse_bit
(
i
);
end
loop
;
end
if
;
end
process
p_err_pmisse_bit
;
-- Create an OR of all PMISSE bits
pmisse_bits_or
<=
'0'
when
(
pmisse_bit
=
(
pmisse_bit
'range
=>
'0'
)
)
else
pmisse_bits_or
<=
'0'
when
pmisse_bit
=
(
pmisse_bit
'range
=>
'0'
)
else
'1'
;
--------------------------------------------------------------------------------
-- Set the rest of the PMISSE bits to zero when g_
nr_chans
< c_max_nr_chans
gen_pmisse_unused_chans
:
if
(
g_nr_chans
<
c_max_nr_chans
)
generate
pmisse_bit
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
end
generate
;
-- Set the rest of the PMISSE bits to zero when g_
NR_CHANS
< c_max_nr_chans
gen_pmisse_unused_chans
:
if
g_NR_CHANS
<
c_max_nr_chans
generate
pmisse_bit
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
end
generate
gen_pmisse_unused_chans
;
--------------------------------------------------------------------------------
-- Synchronize WR valid signal to implement the WRPRES bit
cmp_wrpres_sync
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
data_i
=>
buf_wrtag
,
synced_o
=>
wrpres
);
synced_o
=>
wrpres
);
-- Implement the TBCSR.CLR bit
p_tbcsr_clr
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
rst_20_n
=
'0'
then
buf_clr_p
<=
'0'
;
else
buf_clr_p
<=
'0'
;
...
...
@@ -1393,8 +1309,8 @@ end generate;
p_lts_125
:
process
(
clk_125
)
begin
if
rising_edge
(
clk_125
)
then
for
i
in
0
to
g_
nr_chans
-1
loop
if
(
rst_125_n
=
'0'
)
then
for
i
in
0
to
g_
NR_CHANS
-1
loop
if
rst_125_n
=
'0'
then
lts_cycles_125
(
i
)
<=
(
others
=>
'0'
);
lts_tai_125
(
i
)
<=
(
others
=>
'0'
);
lts_wrtag_125
(
i
)
<=
'0'
;
...
...
@@ -1409,33 +1325,31 @@ end generate;
end
process
p_lts_125
;
-- Pulse synchronizer: sync. lts_ld from 125 MHz to 20MHz domain
gen_lts_ld_pulse_sync
:
for
i
in
0
to
g_nr_chans
-1
generate
cmp_pulse_sync
:
gc_pulse_synchronizer2
port
map
(
clk_in_i
=>
clk_125
,
rst_in_n_i
=>
rst_125_n
,
gen_lts_ld_pulse_sync
:
for
i
in
0
to
g_NR_CHANS
-1
generate
cmp_pulse_sync
:
gc_pulse_synchronizer2
port
map
(
clk_in_i
=>
clk_125
,
rst_in_n_i
=>
rst_125_n
,
clk_out_i
=>
clk_20_i
,
rst_out_n_i
=>
rst_20_n
,
clk_out_i
=>
clk_20_i
,
rst_out_n_i
=>
rst_20_n
,
d_ready_o
=>
lts_ld_rdy_125
(
i
),
d_ready_o
=>
lts_ld_rdy_125
(
i
),
d_p_i
=>
lts_ld_125
(
i
),
q_p_o
=>
lts_ld_20
(
i
)
);
end
generate
gen_lts_ld_pulse_sync
;
d_p_i
=>
lts_ld_125
(
i
),
q_p_o
=>
lts_ld_20
(
i
));
end
generate
gen_lts_ld_pulse_sync
;
-- Latest timestamp regs in 20MHz clock domain
p_lts_20
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
for
i
in
0
to
g_
nr_chans
-1
loop
if
(
rst_20_n
=
'0'
)
then
for
i
in
0
to
g_
NR_CHANS
-1
loop
if
rst_20_n
=
'0'
then
lts_cycles_20
(
i
)
<=
(
others
=>
'0'
);
lts_tai_20
(
i
)
<=
(
others
=>
'0'
);
lts_wrtag_20
(
i
)
<=
'0'
;
elsif
(
lts_ld_20
(
i
)
=
'1'
)
then
elsif
lts_ld_20
(
i
)
=
'1'
then
lts_cycles_20
(
i
)
<=
lts_cycles_125
(
i
);
lts_tai_20
(
i
)
<=
lts_tai_125
(
i
);
lts_wrtag_20
(
i
)
<=
lts_wrtag_125
(
i
);
...
...
@@ -1446,164 +1360,161 @@ end generate gen_lts_ld_pulse_sync;
--------------------------------------------------------------------------------
-- Connect unused timestamps to all zeroes
gen_latest_timestamp_unused_chans
:
if
(
g_nr_chans
<
c_max_nr_chans
)
generate
lts_ld_125
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
lts_ld_rdy_125
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
lts_cycles_125
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
lts_tai_125
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
lts_wrtag_125
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
lts_ld_20
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
lts_cycles_20
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
lts_tai_20
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
lts_wrtag_20
(
c_max_nr_chans
-1
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
end
generate
gen_latest_timestamp_unused_chans
;
gen_latest_timestamp_unused_chans
:
if
g_NR_CHANS
<
c_max_nr_chans
generate
lts_ld_125
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
lts_ld_rdy_125
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
lts_cycles_125
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
lts_tai_125
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
lts_wrtag_125
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
lts_ld_20
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
lts_cycles_20
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
lts_tai_20
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
(
others
=>
'0'
));
lts_wrtag_20
(
c_max_nr_chans
-1
downto
g_NR_CHANS
)
<=
(
others
=>
'0'
);
end
generate
gen_latest_timestamp_unused_chans
;
--------------------------------------------------------------------------------
-- Then, instantiate the component
cmp_conv_regs
:
conv_regs
port
map
(
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
7
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
stall
,
reg_bidr_i
=>
g_board_id
,
reg_sr_gwvers_i
=>
g_gwvers
,
reg_sr_switches_i
=>
sw_gp_i
,
reg_sr_rtm_i
=>
rtm_lines
,
reg_sr_hwvers_i
=>
hwvers_i
,
reg_sr_wrpres_i
=>
wrpres
,
reg_err_i2c_wdto_o
=>
i2c_wdto_bit_rst
,
reg_err_i2c_wdto_i
=>
i2c_wdto_bit
,
reg_err_i2c_wdto_load_o
=>
i2c_wdto_bit_rst_ld
,
reg_err_i2c_err_o
=>
i2c_err_bit_rst
,
reg_err_i2c_err_i
=>
i2c_err_bit
,
reg_err_i2c_err_load_o
=>
i2c_err_bit_rst_ld
,
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
adr
(
7
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_SLV_CONV_REGS
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_SLV_CONV_REGS
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_SLV_CONV_REGS
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_SLV_CONV_REGS
)
.
stall
,
reg_bidr_i
=>
g_BOARD_ID
,
reg_sr_gwvers_i
=>
g_GWVERS
,
reg_sr_switches_i
=>
sw_gp_i
,
reg_sr_rtm_i
=>
rtm_lines
,
reg_sr_hwvers_i
=>
hwvers_i
,
reg_sr_wrpres_i
=>
wrpres
,
reg_err_i2c_wdto_o
=>
i2c_wdto_bit_rst
,
reg_err_i2c_wdto_i
=>
i2c_wdto_bit
,
reg_err_i2c_wdto_load_o
=>
i2c_wdto_bit_rst_ld
,
reg_err_i2c_err_o
=>
i2c_err_bit_rst
,
reg_err_i2c_err_i
=>
i2c_err_bit
,
reg_err_i2c_err_load_o
=>
i2c_err_bit_rst_ld
,
reg_err_flim_pmisse_o
=>
flim_pmisse_bit_rst
,
reg_err_flim_pmisse_i
=>
flim_pmisse_bit
,
reg_err_flim_pmisse_load_o
=>
flim_pmisse_bit_rst_ld
,
reg_err_flim_pmisse_load_o
=>
flim_pmisse_bit_rst_ld
,
reg_err_fwdg_pmisse_o
=>
fwdg_pmisse_bit_rst
,
reg_err_fwdg_pmisse_i
=>
fwdg_pmisse_bit
,
reg_err_fwdg_pmisse_load_o
=>
fwdg_pmisse_bit_rst_ld
,
reg_cr_rst_unlock_o
=>
rst_unlock_bit
,
reg_cr_rst_unlock_i
=>
rst_unlock
,
reg_cr_rst_unlock_load_o
=>
rst_unlock_bit_ld
,
reg_cr_rst_o
=>
rst_bit
,
reg_cr_rst_i
=>
rst_fr_reg
,
reg_cr_rst_load_o
=>
rst_bit_ld
,
reg_cr_mpt_o
=>
mpt
,
reg_cr_mpt_wr_o
=>
mpt_ld
,
reg_ch1fppcr_o
=>
ch_front_pcr
(
0
),
reg_ch1fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
0
)),
reg_ch1fppcr_load_o
=>
ch_front_pcr_ld
(
0
),
reg_ch2fppcr_o
=>
ch_front_pcr
(
1
),
reg_ch2fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
1
)),
reg_ch2fppcr_load_o
=>
ch_front_pcr_ld
(
1
),
reg_ch3fppcr_o
=>
ch_front_pcr
(
2
),
reg_ch3fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
2
)),
reg_ch3fppcr_load_o
=>
ch_front_pcr_ld
(
2
),
reg_ch4fppcr_o
=>
ch_front_pcr
(
3
),
reg_ch4fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
3
)),
reg_ch4fppcr_load_o
=>
ch_front_pcr_ld
(
3
),
reg_ch5fppcr_o
=>
ch_front_pcr
(
4
),
reg_ch5fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
4
)),
reg_ch5fppcr_load_o
=>
ch_front_pcr_ld
(
4
),
reg_ch6fppcr_o
=>
ch_front_pcr
(
5
),
reg_ch6fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
5
)),
reg_ch6fppcr_load_o
=>
ch_front_pcr_ld
(
5
),
reg_ch1rppcr_o
=>
ch_rear_pcr
(
0
),
reg_ch1rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
0
)),
reg_ch1rppcr_load_o
=>
ch_rear_pcr_ld
(
0
),
reg_ch2rppcr_o
=>
ch_rear_pcr
(
1
),
reg_ch2rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
1
)),
reg_ch2rppcr_load_o
=>
ch_rear_pcr_ld
(
1
),
reg_ch3rppcr_o
=>
ch_rear_pcr
(
2
),
reg_ch3rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
2
)),
reg_ch3rppcr_load_o
=>
ch_rear_pcr_ld
(
2
),
reg_ch4rppcr_o
=>
ch_rear_pcr
(
3
),
reg_ch4rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
3
)),
reg_ch4rppcr_load_o
=>
ch_rear_pcr_ld
(
3
),
reg_ch5rppcr_o
=>
ch_rear_pcr
(
4
),
reg_ch5rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
4
)),
reg_ch5rppcr_load_o
=>
ch_rear_pcr_ld
(
4
),
reg_ch6rppcr_o
=>
ch_rear_pcr
(
5
),
reg_ch6rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
5
)),
reg_ch6rppcr_load_o
=>
ch_rear_pcr_ld
(
5
),
reg_tvlr_o
=>
tvlr
,
reg_tvlr_i
=>
tm_tai
(
31
downto
0
),
reg_tvlr_load_o
=>
tvlr_ld
,
reg_tvhr_o
=>
tvhr
,
reg_tvhr_i
=>
tm_tai
(
39
downto
32
),
reg_tvhr_load_o
=>
tvhr_ld
,
reg_tbmr_chan_i
=>
buf_dat_out
(
5
downto
0
),
reg_tbmr_wrtag_i
=>
buf_dat_out
(
6
),
reg_tb_rd_req_p_o
=>
buf_rd_req_p
,
reg_tbcyr_i
=>
buf_dat_out
(
34
downto
7
),
reg_tbtlr_i
=>
buf_dat_out
(
66
downto
35
),
reg_tbthr_i
=>
buf_dat_out
(
74
downto
67
),
reg_tbcsr_clr_o
=>
buf_clr_bit
,
reg_tbcsr_clr_i
=>
'0'
,
reg_tbcsr_clr_load_o
=>
buf_clr_bit_ld
,
reg_tbcsr_usedw_i
=>
buf_count
,
reg_tbcsr_full_i
=>
buf_full
,
reg_tbcsr_empty_i
=>
buf_empty
,
reg_ch1ltscyr_i
=>
lts_cycles_20
(
0
),
reg_ch1ltstlr_i
=>
lts_tai_20
(
0
)(
31
downto
0
),
reg_ch1ltsthr_tai_i
=>
lts_tai_20
(
0
)(
39
downto
32
),
reg_ch1ltsthr_wrtag_i
=>
lts_wrtag_20
(
0
),
reg_ch2ltscyr_i
=>
lts_cycles_20
(
1
),
reg_ch2ltstlr_i
=>
lts_tai_20
(
1
)(
31
downto
0
),
reg_ch2ltsthr_tai_i
=>
lts_tai_20
(
1
)(
39
downto
32
),
reg_ch2ltsthr_wrtag_i
=>
lts_wrtag_20
(
1
),
reg_ch3ltscyr_i
=>
lts_cycles_20
(
2
),
reg_ch3ltstlr_i
=>
lts_tai_20
(
2
)(
31
downto
0
),
reg_ch3ltsthr_tai_i
=>
lts_tai_20
(
2
)(
39
downto
32
),
reg_ch3ltsthr_wrtag_i
=>
lts_wrtag_20
(
2
),
reg_ch4ltscyr_i
=>
lts_cycles_20
(
3
),
reg_ch4ltstlr_i
=>
lts_tai_20
(
3
)(
31
downto
0
),
reg_ch4ltsthr_tai_i
=>
lts_tai_20
(
3
)(
39
downto
32
),
reg_ch4ltsthr_wrtag_i
=>
lts_wrtag_20
(
3
),
reg_ch5ltscyr_i
=>
lts_cycles_20
(
4
),
reg_ch5ltstlr_i
=>
lts_tai_20
(
4
)(
31
downto
0
),
reg_ch5ltsthr_tai_i
=>
lts_tai_20
(
4
)(
39
downto
32
),
reg_ch5ltsthr_wrtag_i
=>
lts_wrtag_20
(
4
),
reg_ch6ltscyr_i
=>
lts_cycles_20
(
5
),
reg_ch6ltstlr_i
=>
lts_tai_20
(
5
)(
31
downto
0
),
reg_ch6ltsthr_tai_i
=>
lts_tai_20
(
5
)(
39
downto
32
),
reg_ch6ltsthr_wrtag_i
=>
lts_wrtag_20
(
5
),
reg_lsr_front_i
=>
line_front
,
reg_lsr_frontinv_i
=>
line_inv_i
,
reg_lsr_rear_i
=>
line_rear
,
reg_lsr_frontfs_i
=>
line_front_fs
,
reg_lsr_frontinvfs_i
=>
line_inv_fs_i
,
reg_lsr_rearfs_i
=>
line_rear_fs
,
reg_oswr_switches_i
=>
sw_other_i
,
reg_uidlr_i
=>
id
(
31
downto
0
),
reg_uidhr_i
=>
id
(
63
downto
32
),
reg_tempr_i
=>
temper
reg_cr_rst_unlock_o
=>
rst_unlock_bit
,
reg_cr_rst_unlock_i
=>
rst_unlock
,
reg_cr_rst_unlock_load_o
=>
rst_unlock_bit_ld
,
reg_cr_rst_o
=>
rst_bit
,
reg_cr_rst_i
=>
rst_fr_reg
,
reg_cr_rst_load_o
=>
rst_bit_ld
,
reg_cr_mpt_o
=>
mpt
,
reg_cr_mpt_wr_o
=>
mpt_ld
,
reg_ch1fppcr_o
=>
ch_front_pcr
(
0
),
reg_ch1fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
0
)),
reg_ch1fppcr_load_o
=>
ch_front_pcr_ld
(
0
),
reg_ch2fppcr_o
=>
ch_front_pcr
(
1
),
reg_ch2fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
1
)),
reg_ch2fppcr_load_o
=>
ch_front_pcr_ld
(
1
),
reg_ch3fppcr_o
=>
ch_front_pcr
(
2
),
reg_ch3fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
2
)),
reg_ch3fppcr_load_o
=>
ch_front_pcr_ld
(
2
),
reg_ch4fppcr_o
=>
ch_front_pcr
(
3
),
reg_ch4fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
3
)),
reg_ch4fppcr_load_o
=>
ch_front_pcr_ld
(
3
),
reg_ch5fppcr_o
=>
ch_front_pcr
(
4
),
reg_ch5fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
4
)),
reg_ch5fppcr_load_o
=>
ch_front_pcr_ld
(
4
),
reg_ch6fppcr_o
=>
ch_front_pcr
(
5
),
reg_ch6fppcr_i
=>
std_logic_vector
(
front_pulse_cnt
(
5
)),
reg_ch6fppcr_load_o
=>
ch_front_pcr_ld
(
5
),
reg_ch1rppcr_o
=>
ch_rear_pcr
(
0
),
reg_ch1rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
0
)),
reg_ch1rppcr_load_o
=>
ch_rear_pcr_ld
(
0
),
reg_ch2rppcr_o
=>
ch_rear_pcr
(
1
),
reg_ch2rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
1
)),
reg_ch2rppcr_load_o
=>
ch_rear_pcr_ld
(
1
),
reg_ch3rppcr_o
=>
ch_rear_pcr
(
2
),
reg_ch3rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
2
)),
reg_ch3rppcr_load_o
=>
ch_rear_pcr_ld
(
2
),
reg_ch4rppcr_o
=>
ch_rear_pcr
(
3
),
reg_ch4rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
3
)),
reg_ch4rppcr_load_o
=>
ch_rear_pcr_ld
(
3
),
reg_ch5rppcr_o
=>
ch_rear_pcr
(
4
),
reg_ch5rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
4
)),
reg_ch5rppcr_load_o
=>
ch_rear_pcr_ld
(
4
),
reg_ch6rppcr_o
=>
ch_rear_pcr
(
5
),
reg_ch6rppcr_i
=>
std_logic_vector
(
rear_pulse_cnt
(
5
)),
reg_ch6rppcr_load_o
=>
ch_rear_pcr_ld
(
5
),
reg_tvlr_o
=>
tvlr
,
reg_tvlr_i
=>
tm_tai
(
31
downto
0
),
reg_tvlr_load_o
=>
tvlr_ld
,
reg_tvhr_o
=>
tvhr
,
reg_tvhr_i
=>
tm_tai
(
39
downto
32
),
reg_tvhr_load_o
=>
tvhr_ld
,
reg_tbmr_chan_i
=>
buf_dat_out
(
5
downto
0
),
reg_tbmr_wrtag_i
=>
buf_dat_out
(
6
),
reg_tb_rd_req_p_o
=>
buf_rd_req_p
,
reg_tbcyr_i
=>
buf_dat_out
(
34
downto
7
),
reg_tbtlr_i
=>
buf_dat_out
(
66
downto
35
),
reg_tbthr_i
=>
buf_dat_out
(
74
downto
67
),
reg_tbcsr_clr_o
=>
buf_clr_bit
,
reg_tbcsr_clr_i
=>
'0'
,
reg_tbcsr_clr_load_o
=>
buf_clr_bit_ld
,
reg_tbcsr_usedw_i
=>
buf_count
,
reg_tbcsr_full_i
=>
buf_full
,
reg_tbcsr_empty_i
=>
buf_empty
,
reg_ch1ltscyr_i
=>
lts_cycles_20
(
0
),
reg_ch1ltstlr_i
=>
lts_tai_20
(
0
)(
31
downto
0
),
reg_ch1ltsthr_tai_i
=>
lts_tai_20
(
0
)(
39
downto
32
),
reg_ch1ltsthr_wrtag_i
=>
lts_wrtag_20
(
0
),
reg_ch2ltscyr_i
=>
lts_cycles_20
(
1
),
reg_ch2ltstlr_i
=>
lts_tai_20
(
1
)(
31
downto
0
),
reg_ch2ltsthr_tai_i
=>
lts_tai_20
(
1
)(
39
downto
32
),
reg_ch2ltsthr_wrtag_i
=>
lts_wrtag_20
(
1
),
reg_ch3ltscyr_i
=>
lts_cycles_20
(
2
),
reg_ch3ltstlr_i
=>
lts_tai_20
(
2
)(
31
downto
0
),
reg_ch3ltsthr_tai_i
=>
lts_tai_20
(
2
)(
39
downto
32
),
reg_ch3ltsthr_wrtag_i
=>
lts_wrtag_20
(
2
),
reg_ch4ltscyr_i
=>
lts_cycles_20
(
3
),
reg_ch4ltstlr_i
=>
lts_tai_20
(
3
)(
31
downto
0
),
reg_ch4ltsthr_tai_i
=>
lts_tai_20
(
3
)(
39
downto
32
),
reg_ch4ltsthr_wrtag_i
=>
lts_wrtag_20
(
3
),
reg_ch5ltscyr_i
=>
lts_cycles_20
(
4
),
reg_ch5ltstlr_i
=>
lts_tai_20
(
4
)(
31
downto
0
),
reg_ch5ltsthr_tai_i
=>
lts_tai_20
(
4
)(
39
downto
32
),
reg_ch5ltsthr_wrtag_i
=>
lts_wrtag_20
(
4
),
reg_ch6ltscyr_i
=>
lts_cycles_20
(
5
),
reg_ch6ltstlr_i
=>
lts_tai_20
(
5
)(
31
downto
0
),
reg_ch6ltsthr_tai_i
=>
lts_tai_20
(
5
)(
39
downto
32
),
reg_ch6ltsthr_wrtag_i
=>
lts_wrtag_20
(
5
),
reg_lsr_front_i
=>
line_front
,
reg_lsr_frontinv_i
=>
line_inv_i
,
reg_lsr_rear_i
=>
line_rear
,
reg_lsr_frontfs_i
=>
line_front_fs
,
reg_lsr_frontinvfs_i
=>
line_inv_fs_i
,
reg_lsr_rearfs_i
=>
line_rear_fs
,
reg_oswr_switches_i
=>
sw_other_i
,
reg_uidlr_i
=>
id
(
31
downto
0
),
reg_uidhr_i
=>
id
(
63
downto
32
),
reg_tempr_i
=>
temper
);
--============================================================================
...
...
@@ -1614,8 +1525,8 @@ end generate gen_latest_timestamp_unused_chans;
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
wbs_i
=>
xbar_master_out
(
c_
slv_multiboot
),
wbs_o
=>
xbar_master_in
(
c_
slv_multiboot
),
wbs_i
=>
xbar_master_out
(
c_
SLV_MULTIBOOT
),
wbs_o
=>
xbar_master_in
(
c_
SLV_MULTIBOOT
),
spi_cs_n_o
=>
flash_cs_n_o
,
spi_sclk_o
=>
flash_sclk_o
,
spi_mosi_o
=>
flash_mosi_o
,
...
...
@@ -1626,26 +1537,25 @@ end generate gen_latest_timestamp_unused_chans;
-- On-board DS18B20 Thermometer logic
--============================================================================
--------------------------------------------------------------------------------
gen_thermometer
:
if
(
g_with_thermometer
=
true
)
generate
--The one-wire interface component is used to read-out the on-board DS18B20
gen_thermometer
:
if
g_WITH_THERMOMETER
=
true
generate
--
The one-wire interface component is used to read-out the on-board DS18B20
-- unique ID and temperature
cmp_onewire
:
gc_ds182x_interface
generic
map
(
freq
=>
20
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
pps_p_i
=>
pps_is_zero
,
onewire_b
=>
thermometer_b
,
id_o
=>
tmp_id
,
temper_o
=>
tmp_temper
,
id_read_o
=>
onewire_read_p
,
id_ok_o
=>
open
);
end
generate
gen_thermometer
;
cmp_onewire
:
gc_ds182x_interface
generic
map
(
freq
=>
20
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
pps_p_i
=>
pps_is_zero
,
onewire_b
=>
thermometer_b
,
id_o
=>
tmp_id
,
temper_o
=>
tmp_temper
,
id_read_o
=>
onewire_read_p
,
id_ok_o
=>
open
);
end
generate
gen_thermometer
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 20 MHz clk
cmp_pps_gen
:
wf_decr_counter
cmp_pps_gen
:
wf_decr_counter
generic
map
(
g_counter_lgth
=>
25
)
...
...
@@ -1661,20 +1571,20 @@ end generate gen_thermometer;
rst_20
<=
not
rst_20_n
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering of the read values
reg_reading
:
process
(
clk_20_i
)
reg_reading
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
temper
<=
(
others
=>
'0'
);
id
<=
(
others
=>
'0'
);
if
(
onewire_read_p
=
'1'
)
then
if
onewire_read_p
=
'1'
then
temper
<=
tmp_temper
;
id
<=
tmp_id
;
end
if
;
end
if
;
end
process
;
end
process
reg_reading
;
-- ============================================================================
-- Bicolor LED matrix logic
-- ============================================================================
...
...
@@ -1682,8 +1592,8 @@ end generate gen_thermometer;
cmp_bicolor_led_ctrl
:
gc_bicolor_led_ctrl
generic
map
(
g_NB_COLUMN
=>
g_
bicolor_led_columns
,
g_NB_LINE
=>
g_
bicolor_led_lines
,
g_NB_COLUMN
=>
g_
BICOLOR_LED_COLUMNS
,
g_NB_LINE
=>
g_
BICOLOR_LED_LINES
,
g_clk_freq
=>
20000000
,
g_refresh_rate
=>
250
)
...
...
@@ -1715,7 +1625,7 @@ end generate gen_thermometer;
-- SFP lines all open-drain, set to high-impedance
sfp_rate_select_o
<=
'Z'
;
sfp_sda_b
<=
'Z'
;
sfp_scl_
i
<=
'Z'
;
sfp_scl_
b
<=
'Z'
;
sfp_tx_disable_o
<=
'Z'
;
end
architecture
arch
;
...
...
top/conv_common_gw_pkg.vhd
View file @
a381f447
--
==============================================================================
--
------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Converter board common gateware package
--==============================================================================
-- URL https://www.ohwr.org/projects/conv-common-gw/wiki/wiki
--------------------------------------------------------------------------------
--
-- Converter common gateware package
-- Description: Package for conv_common_gw entity
--
--
-- date of creation: 2014-08-01
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
GNU LESSER GENERAL PUBLIC LICENSE
--
------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
...
...
@@ -27,15 +21,8 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-08-01 Theodor Stana File created
-- 2016-11 Denia Bouhired Added component for dynamic burst control module
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs
-- 2017-01-23 Denia Bouhired Modified conv_common_gw, added array type for thermal model
--==============================================================================
-- TODO: -
--==============================================================================
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
@@ -54,14 +41,14 @@ package conv_common_gw_pkg is
-- Note that if you change this constant you will make conv-common-gw
-- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
-- _reimplement_ the conv_regs module
constant
c_
max_nr_chans
:
natural
:
=
6
;
--============================================================================
--Type declarations
--
============================================================================
--
Array of constants for temperature model implemented for short pulse mode
type
t_temp_decre_step
is
array
(
0
to
15
)
of
integer
;
constant
c_
MAX_NR_CHANS
:
natural
:
=
6
;
--
============================================================================
--
Type declarations
--
============================================================================
--
Array of constants for temperature model implemented for short pulse mode
type
t_temp_decre_step
is
array
(
0
to
15
)
of
integer
;
--============================================================================
-- Component declarations
--============================================================================
...
...
@@ -69,174 +56,155 @@ package conv_common_gw_pkg is
-- Top-level module
------------------------------------------------------------------------------
component
conv_common_gw
is
generic
(
generic
(
-- Reduces some timeouts to speed up simulations
g_SIMUL
:
boolean
:
=
false
;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_RST_TIME
:
positive
:
=
2
*
(
10
**
6
);
-- Number of repeater channels
g_nr_chans
:
integer
:
=
6
;
g_nr_inv_chans
:
integer
:
=
4
;
g_NR_CHANS
:
integer
:
=
6
;
-- Number of inverter channels
g_NR_INV_CHANS
:
integer
:
=
4
;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_
board_id
:
std_logic_vector
(
31
downto
0
)
;
g_
BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
-- Gateware version
g_gwvers
:
std_logic_vector
(
7
downto
0
);
g_GWVERS
:
std_logic_vector
(
7
downto
0
)
:
=
x"40"
;
-- Generate pulse repetition logic with fixed output pulse width
g_
pgen_fixed_width
:
boolean
;
g_
PGEN_FIXED_WIDTH
:
boolean
:
=
true
;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_
pgen_pwidth_lg
:
natural
range
2
to
40
:
=
24
;
--**DB: was 20 to 40
g_pgen_pwidth_sh
:
natural
range
2
to
40
:
=
5
;
-- output pulse will be limited to pulse period
g_pgen_pperiod_cont
:
natural
range
2
to
5000
:
=
4800
;
--For continuous mode operation max freq 4.12
kHz
g_
pgen_pperiod_lg
:
natural
range
6
to
300
:
=
191
;
--for LONG pulses changes maximum
g_pgen_pperiod_sh
:
natural
range
2
to
300
:
=
9
;
--for SHORT pulses changes maximum
g_PGEN_PWIDTH_LG
:
natural
range
2
to
40
:
=
24
;
g_
PGEN_PWIDTH_SH
:
natural
range
2
to
40
:
=
5
;
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_PGEN_PPERIOD_CONT
:
natural
range
2
to
5000
:
=
4800
;
-- for LONG pulses changes maximum frequency to ~104
kHz
g_
PGEN_PPERIOD_LG
:
natural
range
6
to
300
:
=
191
;
-- for SHORT pulses changes maximum frequency to ~2MHz
g_PGEN_PPERIOD_SH
:
natural
range
2
to
300
:
=
9
;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len
:
integer
:
=
4
;
-- Burst-mode-specific generics:
g_temp_decre_step_lg
:
t_temp_decre_step
:
=
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
5750
,
100
,
79
,
13
,
12
,
4
,
5
,
13
);
g_temp_decre_step_sh
:
t_temp_decre_step
:
=
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
-- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise_lg
:
in
unsigned
(
19
downto
0
)
:
=
x"17700"
;
-- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_sh
:
in
unsigned
(
19
downto
0
)
:
=
x"01388"
;
--For short 250ns pulses
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh
:
in
unsigned
(
39
downto
0
)
:
=
x"02540BE400"
;
-- Generate logic with pulse counters
g_with_pulse_cnt
:
boolean
:
=
false
;
g_PGEN_GF_LEN
:
integer
:
=
4
;
-- Burst-mode-specific generics:
g_TEMP_DECRE_STEP_LG
:
t_temp_decre_step
:
=
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
5750
,
100
,
79
,
13
,
12
,
4
,
5
,
13
);
g_TEMP_DECRE_STEP_SH
:
t_temp_decre_step
:
=
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
-- Single pulse temperature rise for long 1.2us pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_LG
:
in
unsigned
(
19
downto
0
)
:
=
x"17700"
;
-- Single pulse temperature rise for short 250ns pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_SH
:
in
unsigned
(
19
downto
0
)
:
=
x"01388"
;
-- Maximum temperature allowed (scaled)
-- For both long 1.2us pulses and short 250ns
g_BURSTCTRL_MAX_TEMP_LG_SH
:
in
unsigned
(
39
downto
0
)
:
=
x"02540BE400"
;
-- Generate logic with pulse counters
g_with_pulse_timetag
:
boolean
:
=
false
;
g_WITH_PULSE_CNT
:
boolean
:
=
false
;
-- Generate logic with pulse timetag
g_WITH_PULSE_TIMETAG
:
boolean
:
=
false
;
-- Generate logic with manual trigger
g_with_man_trig
:
boolean
:
=
false
;
g_man_trig_pwidth
:
integer
:
=
24
;
g_WITH_MAN_TRIG
:
boolean
:
=
false
;
g_MAN_TRIG_PWIDTH
:
integer
:
=
24
;
-- Generate one-wire master for thermometer
g_with_thermometer
:
boolean
:
=
false
;
g_WITH_THERMOMETER
:
boolean
:
=
false
;
-- Bicolor LED controller signals
g_bicolor_led_columns
:
integer
:
=
6
;
g_bicolor_led_lines
:
integer
:
=
2
);
port
(
g_BICOLOR_LED_COLUMNS
:
integer
:
=
6
;
g_BICOLOR_LED_LINES
:
integer
:
=
2
);
port
(
-- Clocks
clk_20_i
:
in
std_logic
;
clk_125_p_i
:
in
std_logic
;
clk_125_n_i
:
in
std_logic
;
clk_20_i
:
in
std_logic
;
clk_125_p_i
:
in
std_logic
;
clk_125_n_i
:
in
std_logic
;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o
:
out
std_logic
;
rst_n_o
:
out
std_logic
;
-- Glitch filter active-low enable signal
gf_en_n_i
:
in
std_logic
;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
:
in
std_logic
;
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i
:
in
std_logic
;
gf_en_n_i
:
in
std_logic
;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
:
in
std_logic
;
-- Pulse width selection, port low means 250ns, high means 1.2us
pulse_width_sel_n_i
:
in
std_logic
;
-- Channel enable
global_ch_oen_o
:
out
std_logic
;
pulse_front_oen_o
:
out
std_logic
;
pulse_rear_oen_o
:
out
std_logic
;
inv_oen_o
:
out
std_logic
;
-- Pulse inputs
pulse_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_front_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_rear_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
-- Channel leds
global_ch_oen_o
:
out
std_logic
;
pulse_front_oen_o
:
out
std_logic
;
pulse_rear_oen_o
:
out
std_logic
;
inv_oen_o
:
out
std_logic
;
-- Pulse I/O
pulse_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_front_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_rear_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
pulse_o
:
out
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Inverted pulse I/O
inv_pulse_n_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
-- Channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
inv_pulse_i_n
:
in
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
led_pulse_o
:
out
std_logic_vector
(
g_nr_chans
-1
downto
0
);
led_inv_pulse_o
:
out
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
led_pulse_o
:
out
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Inverted channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o
:
out
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
-- I2C interface
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_err_o is high when either SR.I2C_ERR = '1' or SR.I2C_WDTO = '1'
led_i2c_o
:
out
std_logic
;
led_i2c_o
:
out
std_logic
;
-- VME interface
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
-- SPI interface to on-board flash chip
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o
:
out
std_logic
;
dac20_sclk_o
:
out
std_logic
;
dac20_sync_n_o
:
out
std_logic
;
dac20_din_o
:
out
std_logic
;
dac20_sclk_o
:
out
std_logic
;
dac20_sync_n_o
:
out
std_logic
;
-- 125 MHz clock generator control
dac125_din_o
:
out
std_logic
;
dac125_sclk_o
:
out
std_logic
;
dac125_sync_n_o
:
out
std_logic
;
dac125_din_o
:
out
std_logic
;
dac125_sclk_o
:
out
std_logic
;
dac125_sync_n_o
:
out
std_logic
;
-- SFP lines
sfp_los_i
:
in
std_logic
;
sfp_present_i
:
in
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_sda_b
:
inout
std_logic
;
sfp_scl_
i
:
inout
std_logic
;
sfp_scl_
b
:
inout
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
;
-- Switch inputs (for readout from converter status register)
sw_gp_i
:
in
std_logic_vector
(
7
downto
0
);
sw_other_i
:
in
std_logic_vector
(
31
downto
0
);
-- PCB Version information
hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
sw_gp_i
:
in
std_logic_vector
(
7
downto
0
);
sw_other_i
:
in
std_logic_vector
(
31
downto
0
);
-- PCB Version information
hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
-- RTM lines
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_inv_i
:
in
std_logic_vector
(
3
downto
0
);
line_rear_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_front_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
line_inv_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
line_rear_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_inv_fs_i
:
in
std_logic_vector
(
3
downto
0
);
line_rear_fs_i
:
in
std_logic_vector
(
g_nr_chans
-1
downto
0
);
line_front_fs_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
line_inv_fs_i
:
in
std_logic_vector
(
g_NR_INV_CHANS
-1
downto
0
);
line_rear_fs_i
:
in
std_logic_vector
(
g_NR_CHANS
-1
downto
0
);
-- Thermometer line
thermometer_b
:
inout
std_logic
;
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o
:
out
std_logic
;
led_syserr_o
:
out
std_logic
;
-- Bicolor LED signals
bicolor_led_state_i
:
in
std_logic_vector
(
2
*
g_bicolor_led_columns
*
g_bicolor_led_lines
-1
downto
0
);
bicolor_led_col_o
:
out
std_logic_vector
(
g_bicolor_led_columns
-1
downto
0
);
bicolor_led_line_o
:
out
std_logic_vector
(
g_bicolor_led_lines
-1
downto
0
);
bicolor_led_line_oen_o
:
out
std_logic_vector
(
g_bicolor_led_lines
-1
downto
0
)
);
bicolor_led_state_i
:
in
std_logic_vector
(
2
*
g_BICOLOR_LED_COLUMNS
*
g_BICOLOR_LED_LINES
-1
downto
0
);
bicolor_led_col_o
:
out
std_logic_vector
(
g_BICOLOR_LED_COLUMNS
-1
downto
0
);
bicolor_led_line_o
:
out
std_logic_vector
(
g_BICOLOR_LED_LINES
-1
downto
0
);
bicolor_led_line_oen_o
:
out
std_logic_vector
(
g_BICOLOR_LED_LINES
-1
downto
0
));
end
component
conv_common_gw
;
------------------------------------------------------------------------------
...
...
@@ -246,7 +214,7 @@ package conv_common_gw_pkg is
generic
(
-- Reset time in number of clk_i cycles
g_
reset_time
:
positive
:
=
2
_
000
_
000
g_
RESET_TIME
:
positive
:
=
2
_
000
_
000
);
port
(
...
...
@@ -257,16 +225,20 @@ package conv_common_gw_pkg is
end
component
conv_reset_gen
;
------------------------------------------------------------------------------
-- Pulse counter - Used for scenarios where clocks are shorter than the time it takes to synchronise them (Normally it taked 3 clk cycles to synchronise trigger edge.)
------------------------------------------------------------------------------
-- Pulse counter - Used for scenarios where clocks are shorter than the time
-- it takes to synchronise them (Normally it taked 3 clk cycles to synchronise
-- trigger edge.)
------------------------------------------------------------------------------
component
fastevent_counter
is
port
(
sysclk_i
:
in
std_logic
;
rstcount_i
:
in
std_logic
;
en_i
:
in
std_logic
;
trig_i
:
in
std_logic
;
count_o
:
out
std_logic_vector
(
31
downto
0
);
count_int_o
:
out
unsigned
(
31
downto
0
));
end
component
;
port
(
sysclk_i
:
in
std_logic
;
rstcount_i
:
in
std_logic
;
en_i
:
in
std_logic
;
trig_i
:
in
std_logic
;
count_o
:
out
std_logic_vector
(
31
downto
0
);
count_int_o
:
out
unsigned
(
31
downto
0
)
);
end
component
fastevent_counter
;
------------------------------------------------------------------------------
...
...
@@ -276,16 +248,16 @@ package conv_common_gw_pkg is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_
with_fixed_pwidth
:
boolean
;
g_
WITH_FIXED_PWIDTH
:
boolean
;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_
pwidth
:
natural
range
2
to
40
:
=
24
;
--DB was 20 to 40
g_
PWIDTH
:
natural
range
2
to
40
:
=
24
;
-- Pulse period in unit of clock cycles
g_
pperiod
:
natural
:
=
5
g_
PPERIOD
:
natural
:
=
5
);
port
(
...
...
@@ -304,285 +276,280 @@ package conv_common_gw_pkg is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i
:
in
std_logic
;
trig_r_edge_p_i
:
in
std_logic
;
--synced 1 cycle-long r edge output
trig_f_edge_p_i
:
in
std_logic
;
--synced 1 cycle-long f edge output
trig_r_edge_p_i
:
in
std_logic
;
--
synced 1 cycle-long r edge output
trig_f_edge_p_i
:
in
std_logic
;
--
synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o
:
out
std_logic
;
-- Pulse output, active-high
-- latency:
--
glitch filter disabled: none
--
glitch filter enabled: glitch filter length + 5 clk_i cycles
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o
:
out
std_logic
;
pulse_r_edge_p_o
:
out
std_logic
;
--synced 1 cycle-long r edge output
pulse_r_edge_p_o
:
out
std_logic
;
--
synced 1 cycle-long r edge output
pulse_f_edge_p_o
:
out
std_logic
);
end
component
conv_pulse_gen
;
------------------------------------------------------------------------------
-- Controller for burst mode operation with configurable maximum pulse burst length and timeout
------------------------------------------------------------------------------
component
conv_dyn_burst_ctrl
is
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth
:
natural
range
2
to
40
:
=
5
;
-- Thermal model constants, depend on mode selected short or long.
g_temp_decre_step
:
t_temp_decre_step
;
-- Temperature rise resulting from with 250ns pulse
g_1_pulse_temp_rise
:
in
unsigned
(
19
downto
0
);
-- Check every "g_eval_burst_len" pulses
-- Maximum temperature allowed (scaled)
g_max_temp
:
in
unsigned
(
39
downto
0
)
:
=
x"174876E800"
);
port
(
-- Clock and active-low reset inputs
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Enable input, pulse generation is enabled when '1'
en_i
:
in
std_logic
;
pulse_burst_i
:
in
std_logic
;
pulse_r_edge_p_i
:
in
std_logic
;
pulse_f_edge_p_i
:
in
std_logic
;
-- Temp_rise is output for external probing
temp_rise_o
:
out
unsigned
(
39
downto
0
)
;
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o
:
out
std_logic
;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o
:
out
std_logic
);
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_PWIDTH
:
natural
range
2
to
40
:
=
5
;
-- Thermal model constants, depend on mode selected short or long.
g_TEMP_DECRE_STEP
:
t_temp_decre_step
;
-- Temperature rise resulting from with 250ns pulse
g_1_PULSE_TEMP_RISE
:
in
unsigned
(
19
downto
0
);
-- Check every "g_eval_burst_len" pulses
-- Maximum temperature allowed (scaled)
g_MAX_TEMP
:
in
unsigned
(
39
downto
0
)
:
=
x"174876E800"
);
port
(
-- Clock and active-low reset inputs
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Enable input, pulse generation is enabled when '1'
en_i
:
in
std_logic
;
pulse_burst_i
:
in
std_logic
;
pulse_r_edge_p_i
:
in
std_logic
;
pulse_f_edge_p_i
:
in
std_logic
;
-- Temp_rise is output for external probing
temp_rise_o
:
out
unsigned
(
39
downto
0
);
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o
:
out
std_logic
;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o
:
out
std_logic
);
end
component
conv_dyn_burst_ctrl
;
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
component
conv_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i
:
in
std_logic
;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_err_i2c_wdto_o
:
out
std_logic
;
reg_err_i2c_wdto_i
:
in
std_logic
;
reg_err_i2c_wdto_load_o
:
out
std_logic
;
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_err_i2c_err_o
:
out
std_logic
;
reg_err_i2c_err_i
:
in
std_logic
;
reg_err_i2c_err_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o
:
out
std_logic_vector
(
5
downto
0
);
reg_err_flim_pmisse_i
:
in
std_logic_vector
(
5
downto
0
);
reg_err_flim_pmisse_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o
:
out
std_logic_vector
(
5
downto
0
);
reg_err_fwdg_pmisse_i
:
in
std_logic_vector
(
5
downto
0
);
reg_err_fwdg_pmisse_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o
:
out
std_logic
;
reg_cr_rst_unlock_i
:
in
std_logic
;
reg_cr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o
:
out
std_logic_vector
(
7
downto
0
);
reg_cr_mpt_wr_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch1fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch1fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch2fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch2fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch3fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch3fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch4fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch4fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch5fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch5fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch6fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch6fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch1rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch1rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch2rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch2rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch3rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch3rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch4rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch4rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch5rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch5rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch6rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch6rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_tvlr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_tvlr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o
:
out
std_logic_vector
(
7
downto
0
);
reg_tvhr_i
:
in
std_logic_vector
(
7
downto
0
);
reg_tvhr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i
:
in
std_logic_vector
(
5
downto
0
);
reg_tb_rd_req_p_o
:
out
std_logic
;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i
:
in
std_logic_vector
(
6
downto
0
);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i
:
in
std_logic
;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i
:
in
std_logic
;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
reg_lsr_frontfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
reg_lsr_frontinvfs_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
reg_uidhr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i
:
in
std_logic_vector
(
15
downto
0
)
);
end
component
conv_regs
;
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i
:
in
std_logic
;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_err_i2c_wdto_o
:
out
std_logic
;
reg_err_i2c_wdto_i
:
in
std_logic
;
reg_err_i2c_wdto_load_o
:
out
std_logic
;
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_err_i2c_err_o
:
out
std_logic
;
reg_err_i2c_err_i
:
in
std_logic
;
reg_err_i2c_err_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o
:
out
std_logic_vector
(
5
downto
0
);
reg_err_flim_pmisse_i
:
in
std_logic_vector
(
5
downto
0
);
reg_err_flim_pmisse_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o
:
out
std_logic_vector
(
5
downto
0
);
reg_err_fwdg_pmisse_i
:
in
std_logic_vector
(
5
downto
0
);
reg_err_fwdg_pmisse_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o
:
out
std_logic
;
reg_cr_rst_unlock_i
:
in
std_logic
;
reg_cr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o
:
out
std_logic_vector
(
7
downto
0
);
reg_cr_mpt_wr_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch1fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch1fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch2fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch2fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch3fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch3fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch4fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch4fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch5fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch5fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6fppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch6fppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch6fppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch1rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch1rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch2rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch2rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch3rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch3rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch4rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch4rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch5rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch5rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6rppcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch6rppcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch6rppcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_tvlr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_tvlr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o
:
out
std_logic_vector
(
7
downto
0
);
reg_tvhr_i
:
in
std_logic_vector
(
7
downto
0
);
reg_tvhr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i
:
in
std_logic_vector
(
5
downto
0
);
reg_tb_rd_req_p_o
:
out
std_logic
;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i
:
in
std_logic_vector
(
6
downto
0
);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i
:
in
std_logic
;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i
:
in
std_logic
;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
reg_lsr_frontfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
reg_lsr_frontinvfs_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
reg_uidhr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i
:
in
std_logic_vector
(
15
downto
0
));
end
component
conv_regs
;
-- Converter board registers SDB definition
constant
c_
conv_regs_sdb
:
t_sdb_device
:
=
(
constant
c_
CONV_REGS_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"00"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"3ab464e8"
,
-- echo "conv_regs " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20140731"
,
name
=>
"conv_regs "
)));
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"3ab464e8"
,
-- echo "conv_regs " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20140731"
,
name
=>
"conv_regs "
)));
------------------------------------------------------------------------------
-- Pulse time-tagging component
...
...
@@ -591,10 +558,10 @@ end component conv_regs;
generic
(
-- Frequency in Hz of the clk_i signal
g_
clk_rate
:
positive
:
=
125000000
;
g_
CLK_RATE
:
positive
:
=
125000000
;
-- Number of repetition channels
g_
nr_chan
:
positive
:
=
6
g_
NR_CHAN
:
positive
:
=
6
);
port
(
...
...
@@ -634,8 +601,8 @@ end component conv_regs;
component
conv_ring_buf
is
generic
(
g_
data_width
:
positive
;
g_
size
:
positive
g_
DATA_WIDTH
:
positive
;
g_
SIZE
:
positive
);
port
(
...
...
@@ -665,10 +632,10 @@ end component conv_regs;
generic
(
-- Number of conversion channels
g_
nr_chan
:
positive
:
=
6
;
g_
NR_CHAN
:
positive
:
=
6
;
-- Length of pulse in clk_i cycles generated at trig_o output
g_
pwidth
:
positive
:
=
1
g_
PWIDTH
:
positive
:
=
1
);
port
(
...
...
@@ -688,49 +655,45 @@ end component conv_regs;
------------------------------------------------------------------------------
-- PPS trigger for one-wire master
------------------------------------------------------------------------------
component
wf_decr_counter
is
generic
(
g_counter_lgth
:
natural
:
=
4
);
-- default length
port
(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i
:
in
std_logic
;
-- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i
:
in
std_logic
;
-- resets counter to all '1'
component
wf_decr_counter
is
generic
(
g_COUNTER_LGTH
:
natural
:
=
4
);
-- default length
port
(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i
:
in
std_logic
;
-- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i
:
in
std_logic
;
-- resets counter to all '1'
-- Signals from any unit
counter_decr_i
:
in
std_logic
;
-- decrement enable
counter_load_i
:
in
std_logic
;
-- load enable; loads counter to counter_top_i
counter_top_i
:
in
unsigned
(
g_counter_lgth
-1
downto
0
);
-- load value
-- Signals from any unit
counter_decr_i
:
in
std_logic
;
-- decrement enable
counter_load_i
:
in
std_logic
;
-- load enable; loads counter to counter_top_i
counter_top_i
:
in
unsigned
(
g_counter_lgth
-1
downto
0
);
-- load value
-- OUTPUTS
-- Signal to any unit
counter_o
:
out
unsigned
(
g_counter_lgth
-1
downto
0
);
-- counter
counter_is_zero_o
:
out
std_logic
);
-- empty counter indication
-- OUTPUTS
-- Signal to any unit
counter_o
:
out
unsigned
(
g_counter_lgth
-1
downto
0
);
-- counter
counter_is_zero_o
:
out
std_logic
);
-- empty counter indication
end
component
wf_decr_counter
;
end
component
wf_decr_counter
;
------------------------------------------------------------------------------
-- CHIPSCOPE COMPONENTS
------------------------------------------------------------------------------
component
chipscope_ila
IS
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
7
downto
0
));
END
component
chipscope_ila
;
component
chipscope_icon
IS
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
END
component
chipscope_icon
;
end
package
conv_common_gw_pkg
;
component
chipscope_ila
is
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
7
downto
0
));
end
component
chipscope_ila
;
-----------------------------------------------------------------------------------
component
chipscope_icon
is
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
chipscope_icon
;
end
package
conv_common_gw_pkg
;
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