Modified top files to support all modifications in register map plus the new…

Modified top files to support all modifications in register map plus the new burst controller. Note that the burst controller supported in this commit is the one that averages frequency over 1000 pulses

Modified top files to support all modifications in register map plus the new…
Modified top files to support all modifications in register map plus the new burst controller. Note that the burst controller supported in this commit is the one that averages frequency over 1000 pulses
cce8e778 · Denia Bouhired-Ferrag · 0161ea17 · 9a40120b · cce8e778 · cce8e778
Commit cce8e778 authored Dec 07, 2016 by Denia Bouhired-Ferrag
5 changed files
--- a/general-cores @ 9a40120b
+++ b/general-cores @ 9a40120b
-Subproject commit 382b46c19757e0c7c8574ebe56f32169c5a84b20
+Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
--- a/modules/conv_burst_ctrl.vhd
+++ b/modules/conv_burst_ctrl.vhd
--- a/modules/conv_burst_ctrl_v1.vhd
+++ b/modules/conv_burst_ctrl_v1.vhd
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -53,6 +53,7 @@ package conv_common_gw_pkg is
  -- _reimplement_ the conv_regs module
  constant c_max_nr_chans : natural := 6;

+  
  --============================================================================
  -- Component declarations
  --============================================================================
@@ -74,13 +75,19 @@ package conv_common_gw_pkg is
      -- Generate pulse repetition logic with fixed output pulse width
      g_pgen_fixed_width    : boolean;
      -- Pulse width at pulse generator output (valid with fixed output pulse width)
-      g_pgen_pwidth         : natural range 20 to 40 := 24;
+      g_pgen_pwidth         : natural range 2 to 40 := 24; --**DB: was 20 to 40
      -- Duty cycle divider ratio for pulse generator
      -- output pulse will be limited to 1/g_pgen_duty_cycle_div
-      g_pgen_duty_cycle_div : natural := 5;
+      g_pgen_duty_cycle_div : natural := 200;
      -- Pulse generator glitch filter length in number of clk_20_i cycles
      g_pgen_gf_len         : integer := 4;
 	  
+	 -- Burst-mode-specific generics:
+	-- Maximum number of pulses in burst before forced burst rejection. Number dictated by hardware limitations
+	g_burstctrl_max_burst_len 	   : natural := 4;
+	-- 20000000 corresponds to 1 second timeout, 60000 corresponds to 3ms timeout. When timeout is reached burst rejection may start if necessary else go back to IDLE. Useful when pulses are not frequent.
+	g_burstctrl_timeout 	   	   : natural := 200000;
+
      -- Generate logic with pulse counters
      g_with_pulse_cnt       : boolean := false;

@@ -111,6 +118,10 @@ package conv_common_gw_pkg is
      -- Glitch filter active-low enable signal
      gf_en_n_i               : in  std_logic;
 	  
+	  -- Burst mode or short pulse mode enable signal
+	  burst_en_n_i			: in std_logic;
+
+
      -- Channel enable
      global_ch_oen_o         : out std_logic;
      pulse_front_oen_o       : out std_logic;
@@ -235,7 +246,7 @@ package conv_common_gw_pkg is
      -- Default pulse width (20 MHz clock): 1.2 us
      -- Minimum allowable pulse width (20 MHz clock): 1 us
      -- Maximum allowable pulse width (20 MHz clock): 2 us
-      g_pwidth : natural range 20 to 40 := 24;
+      g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40

      -- Duty cycle divider: D = 1/g_duty_cycle_div
      g_duty_cycle_div : natural := 5
@@ -271,6 +282,47 @@ package conv_common_gw_pkg is
  end component conv_pulse_gen;
  
    ------------------------------------------------------------------------------
+  -- Controller for burst mode operation with configurable maximum pulse burst length and timeout
+  ------------------------------------------------------------------------------
+
+  component conv_burst_ctrl is
+	generic
+	(
+	-- Short pulse width, in number of clk_i cycles
+    -- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
+	g_pwidth : natural range 2 to 40 	:= 5; 
+    
+	-- Duty cycle divider: D = 1/g_duty_cycle_div
+    g_duty_cycle_div : natural 			:= 200;
+	
+	-- Number of pulses allowed before decision is made on whether to continue burst
+	-- Maximum number of pulses that can be received at the worst case 2MHz scenario
+	g_max_burst_len : natural 			:= 1000;   -- Check every "g_eval_burst_len" pulses
+	
+	-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s.
+	g_burst_timeout : natural 			:= 200000 -- 20000000 corresponds to 1 second timeout
+										  -- 60000 corresponds to 3ms timeout
+	);
+	port
+	(
+    -- Clock and active-low reset inputs
+    clk_i        	: in  std_logic;
+    rst_n_i      	: in  std_logic;
+	
+	-- Enable input, pulse generation is enabled when '1'
+    en_i         	 	: in  std_logic;
+	pulse_burst_i 		: in std_logic;
+	pulse_burst_o		: out std_logic;
+	
+	-- Burst error output, pulses high for one clock cycle when a pulse arrives
+    -- within a burst rejection phase
+    burst_err_p_o : out std_logic	
+	
+	);
+  
+  
+  end component conv_burst_ctrl;
+  ------------------------------------------------------------------------------
  -- Converter board control registers
  ------------------------------------------------------------------------------
  component conv_regs is
@@ -461,7 +513,15 @@ package conv_common_gw_pkg is
  -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
      reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
  -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
-      reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0)
+  
+      reg_mswr_switches_i                      : in     std_logic_vector(31 downto 0); 
+      reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0);
+	  -- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: '32 least significant bits of DS18B20U'
+    reg_ds18b20u_id_lsb_i                    : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: '32 most significant bits of DS18B20U'
+    reg_ds18b20u_id_msb_i                    : in     std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'Temperature from DS18B20 thermometer' in reg: 'Board temperature'
+    reg_ds18b20u_temp_i                      : in     std_logic_vector(15 downto 0)
    );
  end component conv_regs;

@@ -583,5 +643,34 @@ package conv_common_gw_pkg is
    );
  end component conv_man_trig;

+  ------------------------------------------------------------------------------
+  -- PPS trigger for one-wire master
+  ------------------------------------------------------------------------------
+  
+component wf_decr_counter is
+  generic(g_counter_lgth : natural := 4);                         -- default length
+  port(
+  -- INPUTS
+    -- nanoFIP User Interface general signal
+    uclk_i            : in std_logic;                             -- 40 MHz clock
+
+    -- Signal from the wf_reset_unit
+    counter_rst_i     : in std_logic;                             -- resets counter to all '1'
+
+    -- Signals from any unit
+    counter_decr_i    : in std_logic;                             -- decrement enable
+    counter_load_i    : in std_logic;                             -- load enable; loads counter to counter_top_i
+    counter_top_i     : in unsigned (g_counter_lgth-1 downto 0);  -- load value
+
+
+  -- OUTPUTS
+    -- Signal to any unit
+    counter_o         : out unsigned (g_counter_lgth-1 downto 0); -- counter
+    counter_is_zero_o : out std_logic);                           -- empty counter indication
+
+end component wf_decr_counter;
 end package conv_common_gw_pkg;

+
+-----------------------------------------------------------------------------------
+