--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo_v2.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--         Theodor-Adrian Stana (t.stana@cern.ch)
--
-- date: 01-12-2012
--
-- version: 0.9
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------

library IEEE;
library unisim;
library work;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;

entity conv_ttl_blo_v2 is
  port 
  (
--  RST : in std_logic;
--    CLK20_VCXO           : in  std_logic;
    FPGA_CLK_P           : in  std_logic; --Using the 125MHz clock
    FPGA_CLK_N           : in  std_logic;
    
    -- LEDs
--     LED_CTRL0            : out std_logic;
--     LED_CTRL0_OEN        : out std_logic;
--     LED_CTRL1            : out std_logic;
--     LED_CTRL1_OEN        : out std_logic;
--     LED_MULTICAST_2_0    : out std_logic;
--     LED_MULTICAST_3_1    : out std_logic;
--     LED_WR_GMT_TTL_TTLN  : out std_logic;
--     LED_WR_LINK_SYSERROR : out std_logic;
--     LED_WR_OK_SYSPW      : out std_logic;
--     LED_WR_OWNADDR_I2C   : out std_logic;
    
    -- I/Os for pulses
    PULSE_FRONT_LED_N    : out std_logic_vector(6 downto 1);
--    PULSE_REAR_LED_N     : out std_logic_vector(6 downto 1);
    -- FPGA_INPUT_TTL_N     : in  std_logic_vector(6 downto 1);
    -- FPGA_OUT_TTL         : out std_logic_vector(6 downto 1);
--    FPGA_BLO_IN          : in  std_logic_vector(6 downto 1);
--    FPGA_TRIG_BLO        : out std_logic_vector(6 downto 1);
--    INV_IN_N             : in  std_logic_vector(4 downto 1);
--    INV_OUT              : out std_logic_vector(4 downto 1);
    
--    -- Lines for the i2c_slave
--    SCL_I                : in  std_logic;
--    SCL_O                : out std_logic;
--    SCL_OE               : out std_logic;
--    SDA_I                : in  std_logic;
--    SDA_O                : out std_logic;
--    SDA_OE               : out std_logic;
--    FPGA_GA              : in  std_logic_vector(4 downto 0);
--    FPGA_GAP             : in  std_logic;
--    
--    -- Pins of the SPI interface to write into the Flash memory
--    FPGA_PROM_CCLK       : out std_logic;
--    FPGA_PROM_CSO_B_N    : out std_logic;
--    FPGA_PROM_DIN        : in  std_logic;
--    FPGA_PROM_MOSI       : out std_logic;
--      
    -- FPGA_OE              : out std_logic;
    -- FPGA_BLO_OE          : out std_logic;
    -- FPGA_TRIG_TTL_OE     : out std_logic;
    -- FPGA_INV_OE          : out std_logic;
--    
--    --TTL/INV_TTL_N
--    LEVEL                : in  std_logic;
    
    
--    EXTRA_SWITCH         : in  std_logic_vector(7 downto 1);
    
    -- It allows power sequencing of the
    -- 24V rail after a security given delay
    MR_N                 : out std_logic

    -- RTM identifiers, should match with the expected values
    -- TODO: add matching
--    FPGA_RTMM_N        : in std_logic_vector(2 downto 0);
--    FPGA_RTMP_N        : in std_logic_vector(2 downto 0)
  );
end conv_ttl_blo_v2;


architecture Behavioral of conv_ttl_blo_v2 is

  --============================================================================
  -- Component declarations
  --============================================================================

  component reset_gen is
    generic
    (
    -- Reset time in number of clk_i cycles
      g_reset_time : positive := 5_000_000
    );
    port
    (
      clk_i   : in  std_logic;
      rst_n_o : out std_logic
    );
  end component reset_gen;

  --============================================================================
  -- Signal declarations
  --============================================================================
  signal clk_125         : std_logic;
--  signal s_led_array     : t_led_array_o := c_led_array_default;
--  signal i2c_slave       : t_i2c_slave_i;
--  signal s_i2c_slave_o   : t_i2c_slave_o;
--  signal s_spi_master_i  : t_spi_master_i;
--  signal s_spi_master_o  : t_spi_master_o;
--  signal s_rtm_i         : t_rtm_i;
  signal rst_n: std_logic;
  signal rst : std_logic;
  signal switch          : std_logic_vector(7 downto 1);
  
  signal rtmm, rtmp      : std_logic_vector(2 downto 0);

  signal clk_50, clk_buf_50   : std_logic;
  signal clk_200, clk_buf_200 : std_logic;
  signal clk_250, clk_buf_250 : std_logic;
  signal pll_fb_in            : std_logic;
  signal pll_fb_out           : std_logic;
  signal pll_locked           : std_logic;
  signal front_leds           : std_logic_vector(6 downto 1);

  signal trig                 : std_logic;
  signal cnt : unsigned(6 downto 1) := (others => '0');
  signal cnt2 : unsigned(31 downto 0) := (others => '0');
  signal p : std_logic := '0';

begin

  --============================================================================
  -- Internal and external reset generation
  --============================================================================
  -- Configure reset generator for 100ms power-on reset
  cmp_reset_gen: reset_gen
    generic map
    (
      g_reset_time => 5_000_000
    )
    port map
    (
      clk_i   => clk_125,
      rst_n_o => rst_n
    );

  rst  <= not rst_n;
  MR_N <= rst_n;

  cmp_125_diff_buf: IBUFGDS
  generic map 
  (
    DIFF_TERM    => TRUE,
    IBUF_LOW_PWR => TRUE
  )
  port map 
  (
    I  => FPGA_CLK_P,
    IB => FPGA_CLK_N,
    O  => clk_125
  );

  --============================================================================
  -- Generation of internal clock signals
  --============================================================================
--  -- set up the fabric PLL_BASE to drive the BUFPLL
--  pll_base_inst : PLL_BASE
--  generic map 
--  (
--    BANDWIDTH          => "OPTIMIZED",
--    CLK_FEEDBACK       => "CLKFBOUT",
--    COMPENSATION       => "SYSTEM_SYNCHRONOUS",
--    DIVCLK_DIVIDE      => 1,
--    CLKFBOUT_MULT      => 8,       -- 1 GHz at FBOUT
--    CLKFBOUT_PHASE     => 0.000,
--    CLKOUT0_DIVIDE     => 20,      -- 50 MHz at OUT0
--    CLKOUT0_PHASE      => 0.000,
--    CLKOUT0_DUTY_CYCLE => 0.500,
--    CLKOUT1_DIVIDE     => 5,       -- 200 MHz at OUT1
--    CLKOUT1_PHASE      => 0.000,
--    CLKOUT1_DUTY_CYCLE => 0.500,
--    CLKOUT2_DIVIDE     => 4,       -- 250 MHz at OUT1
--    CLKOUT2_PHASE      => 0.000,
--    CLKOUT2_DUTY_CYCLE => 0.500,
--    CLKIN_PERIOD       => 8.0,
--    REF_JITTER         => 0.010
--  )
--  port map 
--  (
--    -- Output clocks
--    CLKFBOUT => pll_fb_out,
--    CLKOUT0  => clk_buf_50,
--    CLKOUT1  => open, -- clk_buf_200,
--    CLKOUT2  => open, -- clk_buf_250,
--    CLKOUT3  => open,
--    CLKOUT4  => open,
--    CLKOUT5  => open,
--    -- Status and control signals
--    LOCKED   => pll_locked,  
--    RST      => RST,
--    -- Input clock control
--    CLKFBIN  => pll_fb_in,
--    CLKIN    => clk_125
--  );
--
--  -- Clock buffer on the PLL feedback line
--  cmp_pll_feedback_bufg : BUFG
--  port map
--  (
--    I => pll_fb_out,
--    O => pll_fb_in
--  );
--
--  -- Clock buffer for distributing the 50 MHz clock signal
--  cmp_clk50_buf : BUFG
--  port map 
--  (
--    I => clk_buf_50,
--    O => clk_50
--  );

  p_cnt: process(clk_125)
  begin
    if rising_edge(clk_125) then
     if (rst_n = '0') then
       cnt <= (others => '0');
     elsif (p = '1') then
       cnt <= cnt + 1;
     end if;
    end if;
  end process;
  
  p_cnt2: process(clk_125)
  begin
    if rising_edge(clk_125) then
      cnt2 <= cnt2 + 1;
      p <= '0';
      if (cnt2 = 25_000_000) then
        cnt2 <= (others => '0');
        p <= '1';
      end if;
    end if;
  end process p_cnt2;

  PULSE_FRONT_LED_N        <= not std_logic_vector(cnt);



  -- LED_CTRL0            <= s_led_array.CTRL0;
  -- LED_CTRL0_OEN        <= s_led_array.CTRL0_OEN;
  -- LED_CTRL1            <= s_led_array.CTRL1;
  -- LED_CTRL1_OEN        <= s_led_array.CTRL1_OEN;
  -- LED_MULTICAST_2_0    <= s_led_array.MULTICAST_2_0;
  -- LED_MULTICAST_3_1    <= s_led_array.MULTICAST_3_1;
  -- LED_WR_GMT_TTL_TTLN  <= s_led_array.WR_GMT_TTL_TTLN;
  -- LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
  -- LED_WR_OK_SYSPW      <= s_led_array.WR_OK_SYSPW;
  -- LED_WR_OWNADDR_I2C   <= s_led_array.WR_OWNADDR_I2C;

  -- i2c_slave.SCL_I      <= SCL_I;
  -- i2c_slave.SDA_I      <= SDA_I;
  -- SCL_O                <= s_i2c_slave_o.SCL_O;
  -- SCL_OE               <= s_i2c_slave_o.SCL_OE;
  -- SDA_O                <= s_i2c_slave_o.SDA_O;
  -- SDA_OE               <= s_i2c_slave_o.SDA_OE;

  -- s_spi_master_i.DIN   <= FPGA_PROM_DIN;
  -- FPGA_PROM_CCLK       <= s_spi_master_o.CCLK;
  -- FPGA_PROM_CSO_B_N    <= s_spi_master_o.CSO_B_N;
  -- FPGA_PROM_MOSI       <= s_spi_master_o.MOSI;

  -- rtmm                 <= not FPGA_RTMM_N;
  -- rtmp                 <= not FPGA_RTMP_N;

  -- switch               <= EXTRA_SWITCH;

  -- cmp_image1_core: image1_core
  -- generic map
  -- (
  --   g_number_of_channels => 6
  -- )
  -- port map
  -- (
  --   rst_i           => RST,
  --   clk_20_i        => CLK20_VCXO,
  --   clk_125_i       => clk_125,
  --   led_array_o     => s_led_array,
  --   led_front_n_o   => PULSE_FRONT_LED_N,
  --   led_rear_n_o    => PULSE_REAR_LED_N,
  --   pulse_front_n_i => FPGA_INPUT_TTL_N,
  --   pulse_front_o   => FPGA_OUT_TTL,
  --   pulse_rear_i    => FPGA_BLO_IN,
  --   pulse_rear_o    => FPGA_TRIG_BLO,
  --   inv_n_i         => INV_IN_N,
  --   inv_o           => INV_OUT,
  --   i2c_slave_i     => i2c_slave,
  --   i2c_slave_o     => s_i2c_slave_o,
  --   fpga_ga_i       => FPGA_GA ,
  --   fpga_gap_i      => FPGA_GAP,
  --   spi_master_i    => s_spi_master_i,
  --   spi_master_o    => s_spi_master_o,
  --   fpga_out_en_o   => FPGA_OE,
  --   fpga_blo_en_o   => FPGA_BLO_OE,
  --   fpga_ttl_en_o   => FPGA_TRIG_TTL_OE,
  --   fpga_inv_en_o   => FPGA_INV_OE,
  --   level_i         => LEVEL,
  --   switch_i        => switch(1),
  --   manual_rst_n_o  => MR_N,
  --   rtmm_i          => rtmm,
  --   rtmp_i          => rtmp
  -- );

end Behavioral;
