--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description: 
--
-- dependencies:
--
-- references:
-- 
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
--==============================================================================
-- TODO: - 
--==============================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity testbench is
end entity testbench;


architecture behav of testbench is

  --============================================================================
  -- Type declarations
  --============================================================================

  --============================================================================
  -- Constant declarations
  --============================================================================
  constant c_clk_per : time := 8 ns;
  constant c_reset_width : time := 31 ns;

  --============================================================================
  -- Component declarations
  --============================================================================

  component ctb_pulse_gen is
    generic 
    (
      -- Pulse width, in number of clk_i cycles
      g_pulse_width     : natural := 15;

      -- Glitch filter length:
      -- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
      -- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
      -- etc.
      g_glitch_filt_len : natural := 4

    );
    port
    (
      clk_i        : in  std_logic;
      rst_n_i      : in  std_logic;
      
      -- Glitch filter enable input
      -- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
      -- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
      glitch_filt_en_n_i : in  std_logic;

      -- Enable input, pulse generation is enabled when '1'
      en_i         : in  std_logic;

      -- Trigger input, has to be '1' to assure pulse output with delay no greater
      -- than internal gate delays.
      trig_i       : in  std_logic;
      
      -- Pulse output, active-high
      -- latency:
      --    glitch filter disabled: none
      --    glitch filter enabled: g_glitch_filt_len+3 clk_i cycles
      pulse_o      : out std_logic
    );
  end component ctb_pulse_gen;

  component pulse_gen_gp is
    generic
    (
      g_pwidth : natural := 200;
      g_freq   : natural := 400;
      g_delay  : natural := 0
    );
    port
    (
      clk_i   : in  std_logic;
      rst_n_i : in  std_logic;
      en_i    : in  std_logic;
      pulse_o : out std_logic
    );
  end component pulse_gen_gp;

  --============================================================================
  -- Signal declarations
  --============================================================================
  signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
  signal actual_trig : std_logic := '0';
  signal actual_pulse : std_logic := '0';
  signal gf_en : std_logic;
  signal gf_en_n : std_logic;

--==============================================================================
--  architecture begin
--==============================================================================
begin

  -- DUT INSTANTIATION
  DUT: ctb_pulse_gen
  generic map
  (
    g_pulse_width     => 150,
    g_glitch_filt_len => 4
  )
  port map
  (
    clk_i        => clk,
    rst_n_i      => rst_n,
    glitch_filt_en_n_i => gf_en_n,
    en_i         => '1',
    trig_i       => actual_trig,
    pulse_o      => pulse
  );

  -- CLOCK GENERATION
  p_clk: process
  begin
    clk <= not clk;
    wait for c_clk_per/2;
  end process p_clk;

  -- SECOND CLOCK GENERATION
  p_clk2: process
  begin
    clk2 <= not clk2;
    wait for 2 ns;
  end process p_clk2;

  -- RESET GENERATION
  p_rst_n: process
  begin
    rst_n <= '0';
    wait for c_reset_width;
    rst_n <= '1';
    wait;
  end process p_rst_n;

  -- PULSE GENERATOR FOR TRIGGER
  cmp_pulse_gen: pulse_gen_gp
  generic map
  (
    g_pwidth => 5,
    g_freq   => 751
  )
  port map
  (
    clk_i   => clk,
    rst_n_i => rst_n,
    en_i    => '1',
    pulse_o => trig
  );
  actual_trig  <= trig;
  actual_pulse <= pulse;
  
  cmp_pulse_gen_gp: pulse_gen_gp
  generic map
  (
    g_pwidth => 1033,
    g_freq   => 2066
  )
  port map
  (
    clk_i   => clk,
    rst_n_i => rst_n,
    en_i    => '1',
    pulse_o => gf_en
  );
  
  gf_en_n <= '1'; --not gf_en;
end architecture behav;
--==============================================================================
--  architecture end
--==============================================================================
