--==============================================================================
-- CERN (BE-CO-HT)
-- Long-term register test for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
--    This is the top-level file for the register test for TTL pulse converter
--    boards. It instantiates a single-port RAM from the general-cores OHWR
--    repository and connects this RAM via an xwb_crossbar (also from
--    general-cores) to the i2c_bridge component.
--
--    An external program on the PC should send commands according to the I2C
--    protocol established with ELMA [2], to write and read from the single-port
--    RAM. The CONV-TTL-BLO is plugged into this ELMA crate. The wb_i2c_bridge
--    translates these commands into wishbone accesses to the RAM.
--
--    An example program can be found in the conv-ttl-blo repository [3], under
--    the software/regtest/ folder. This Python script writes to and reads back
--    all data from the RAM and checks for correct reading.
--
-- dependencies:
--    general-cores repository [1]
--
-- references:
--    [1] Platform-independent core collection webpage on OHWR,
--        http://www.ohwr.org/projects/general-cores/repository
--    [2] ELMA, Access to board data using SNMP and I2C
--        http://www.ohwr.org/documents/227
--    [3] CONV-TTL-BLO project repository on OHWR,
--        http://www.ohwr.org/projects/conv-ttl-blo/repository
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--   26-11-2013   Theodor Stana       Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;

use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;

entity regtest is
  generic
  (
    g_nr_ttl_chan : natural := 6;
    g_nr_inv_chan : natural := 4
  );
  port
  (
    -- Clocks
    -- 20 MHz from VCXO
    clk20_vcxo_i           : in  std_logic;
    -- 125 MHz from clock generator
    fpga_clk_p_i           : in  std_logic;
    fpga_clk_n_i           : in  std_logic;

    -- LEDs
    led_ctrl0_o            : out std_logic;
    led_ctrl0_oen_o        : out std_logic;
    led_ctrl1_o            : out std_logic;
    led_ctrl1_oen_o        : out std_logic;
    led_multicast_2_0_o    : out std_logic;
    led_multicast_3_1_o    : out std_logic;
    led_wr_gmt_ttl_ttln_o  : out std_logic;
    led_wr_link_syserror_o : out std_logic;
    led_wr_ok_syspw_o      : out std_logic;
    led_wr_ownaddr_i2c_o   : out std_logic;

    -- I/Os for pulses
    pulse_front_led_n_o    : out std_logic_vector(g_nr_ttl_chan downto 1);
    pulse_rear_led_n_o     : out std_logic_vector(g_nr_ttl_chan downto 1);
    fpga_input_ttl_n_i     : in  std_logic_vector(g_nr_ttl_chan downto 1);
    fpga_out_ttl_o         : out std_logic_vector(g_nr_ttl_chan downto 1);
    fpga_blo_in_i          : in  std_logic_vector(g_nr_ttl_chan downto 1);
    fpga_trig_blo_o        : out std_logic_vector(g_nr_ttl_chan downto 1);
    inv_in_n_i             : in  std_logic_vector(g_nr_inv_chan downto 1);
    inv_out_o              : out std_logic_vector(g_nr_inv_chan downto 1);

    -- Output enable lines
    fpga_oe_o              : out std_logic;
    fpga_blo_oe_o          : out std_logic;
    fpga_trig_ttl_oe_o     : out std_logic;
    fpga_inv_oe_o          : out std_logic;

    --TTL/INV_TTL_N
    ttl_switch_n_i         : in  std_logic;

    extra_switch_n_i       : in  std_logic_vector(7 downto 1);

    -- Lines for the i2c_slave
    scl_i                  : in  std_logic;
    scl_o                  : out std_logic;
    scl_oe_o               : out std_logic;
    sda_i                  : in  std_logic;
    sda_o                  : out std_logic;
    sda_oe_o               : out std_logic;
    fpga_ga_i              : in  std_logic_vector(4 downto 0);
    fpga_gap_i             : in  std_logic;

    -- Flash memory lines
    fpga_prom_cclk_o       : out std_logic;
    fpga_prom_cso_b_n_o    : out std_logic;
    fpga_prom_mosi_o       : out std_logic;
    fpga_prom_miso_i       : in  std_logic;

    -- Blocking power supply reset line
    mr_n_o                 : out std_logic;

    -- Thermometer line
    thermometer_b          : inout std_logic;

    -- PLL DACs
    -- DAC1: 20 MHz VCXO control
    fpga_plldac1_din_o     : out std_logic;
    fpga_plldac1_sclk_o    : out std_logic;
    fpga_plldac1_sync_n_o  : out std_logic;
    -- DAC2: 125 MHz clock generator control
    fpga_plldac2_din_o     : out std_logic;
    fpga_plldac2_sclk_o    : out std_logic;
    fpga_plldac2_sync_n_o  : out std_logic;

    -- SFP lines
    fpga_sfp_los_i         : in    std_logic;
    fpga_sfp_mod_def0_i    : in    std_logic;
    fpga_sfp_rate_select_o : out   std_logic;
    fpga_sfp_mod_def1_b    : inout std_logic;
    fpga_sfp_mod_def2_b    : inout std_logic;
    fpga_sfp_tx_disable_o  : out   std_logic;
    fpga_sfp_tx_fault_i    : in    std_logic;

    -- RTM identifiers, should match with the expected values
    fpga_rtmm_n_i          : in std_logic_vector(2 downto 0);
    fpga_rtmp_n_i          : in std_logic_vector(2 downto 0)
  );
end regtest;


architecture behav of regtest is

  --============================================================================
  -- Constant declarations
  --============================================================================
  -- Number of Wishbone masters and slaves, for wb_crossbar
  constant c_nr_masters      : natural :=  1;
  constant c_nr_slaves       : natural :=  1;

  -----------------------------------------
  -- Memory map
  -- * all registers are word-addressable
  -- * all registers are word-aligned
  -----------------------------------------
  --    MEM       [000-FFF]
  -----------------------------------------
  -- slave order definitions
  constant c_slv_mem : natural := 0;

  -- base address definitions
  constant c_addr_mem : t_wishbone_address := x"00000000";

  -- address mask definitions
  constant c_mask_mem : t_wishbone_address := x"00000000";

  -- addresses constant for Wishbone crossbar
  constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
                  := (
                       c_slv_mem => c_addr_mem
                     );

  -- masks constant for Wishbone crossbar
  constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
                  := (
                       c_slv_mem => c_mask_mem
                     );

  --============================================================================
  -- Component declarations
  --============================================================================
  -- Reset generator component
  -- (use: global reset generation, output reset generation)
  component reset_gen is
    generic
    (
      -- Reset time in number of clk_i cycles
      g_reset_time : positive := 2_000_000
    );
    port
    (
      clk_i   : in  std_logic;
      rst_i   : in  std_logic;
      rst_n_o : out std_logic
    );
  end component reset_gen;

  --============================================================================
  -- Signal declarations
  --============================================================================
  -- Reset signals
  signal rst_n             : std_logic;

  -- Wishbone crossbar signals
  signal xbar_slave_in     : t_wishbone_slave_in_array  (c_nr_masters - 1 downto 0);
  signal xbar_slave_out    : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
  signal xbar_master_in    : t_wishbone_master_in_array (c_nr_slaves  - 1 downto 0);
  signal xbar_master_out   : t_wishbone_master_out_array(c_nr_slaves  - 1 downto 0);

  -- RAM signals
  signal ram_we            : std_logic;
  signal ram_ack           : std_logic;

  -- Signal for controlling the bicolor LED matrix
  signal bicolor_led_state : std_logic_vector(23 downto 0);

  -- I2C bridge signals
  signal i2c_tip           : std_logic;
  signal i2c_tip_d0        : std_logic;
  signal i2c_err_p         : std_logic;
  signal i2c_up            : std_logic;
  signal i2c_wdto_p        : std_logic;
  signal i2c_addr          : std_logic_vector(6 downto 0);
  signal led_i2c           : std_logic;
  signal led_i2c_clkdiv    : unsigned(22 downto 0);
  signal led_i2c_cnt       : unsigned( 2 downto 0);
  signal led_i2c_err       : std_logic;
  signal led_i2c_blink     : std_logic;
  signal led_wdto          : std_logic;

  -- Transfer trigger for oscilloscope
  signal trig_p            : std_logic;

--==============================================================================
--  architecture begin
--==============================================================================
begin

  --============================================================================
  -- Internal and external reset generation
  --============================================================================
  -- Configure reset generator for 96ms power-on reset
  cmp_reset_gen : reset_gen
    generic map
    (
      -- Reset time: 12 * 8ns * (10**6) = 96 ms
      g_reset_time => 12*(10**6)
    )
    port map
    (
      clk_i   => clk20_vcxo_i,
      rst_i   => '0',
      rst_n_o => rst_n
    );

--  rst  <= not rst_n;
  mr_n_o <= rst_n;

  --============================================================================
  -- I2C bridge logic
  --============================================================================
  -- Set the I2C address signal according to ELMA protocol [1]
  i2c_addr <= "10" & fpga_ga_i;

  -- Instantiate I2C bridge component
  --
  -- FSM watchdog timeout timer:
  -- * consider bit period of 30 us
  -- * 10 bits / byte transfer => 300 us
  -- * 40 bytes in one transfer => 12000 us
  -- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
  -- * multiply by two for extra safety => g_fsm_wdt = 480000
  -- * Time to watchdog timeout: 480000 * 50ns = 24 ms
  cmp_i2c_bridge : wb_i2c_bridge
    generic map
    (
      g_fsm_wdt => 480000
    )
    port map
    (
      -- Clock, reset
      clk_i      => clk20_vcxo_i,
      rst_n_i    => rst_n,

      -- I2C lines
      scl_i      => scl_i,
      scl_o      => scl_o,
      scl_en_o   => scl_oe_o,
      sda_i      => sda_i,
      sda_o      => sda_o,
      sda_en_o   => sda_oe_o,

      -- I2C address and status
      i2c_addr_i => i2c_addr,
      tip_o      => i2c_tip,
      err_p_o    => i2c_err_p,
      wdto_p_o   => i2c_wdto_p,

      -- Wishbone master signals
      wbm_stb_o  => xbar_slave_in(0).stb,
      wbm_cyc_o  => xbar_slave_in(0).cyc,
      wbm_sel_o  => xbar_slave_in(0).sel,
      wbm_we_o   => xbar_slave_in(0).we,
      wbm_dat_i  => xbar_slave_out(0).dat,
      wbm_dat_o  => xbar_slave_in(0).dat,
      wbm_adr_o  => xbar_slave_in(0).adr,
      wbm_ack_i  => xbar_slave_out(0).ack,
      wbm_rty_i  => xbar_slave_out(0).rty,
      wbm_err_i  => xbar_slave_out(0).err
    );

  -- Process to blink the LED when an I2C transfer is in progress
  -- blinks four times per transfer
  -- blink width : 20 ms
  -- blink period: 40 ms
  p_i2c_blink : process(clk20_vcxo_i)
  begin
    if rising_edge(clk20_vcxo_i) then
      if (rst_n = '0') then
        led_i2c_clkdiv <= (others => '0');
        led_i2c_cnt    <= (others => '0');
        led_i2c        <= '0';
        led_i2c_blink  <= '0';
      else
        case led_i2c_blink is

          when '0' =>
            led_i2c <= '0';
            if (i2c_tip = '1') then
              led_i2c_blink <= '1';
            end if;

          when '1' =>
            led_i2c_clkdiv <= led_i2c_clkdiv + 1;
            if (led_i2c_clkdiv = 399999) then
              led_i2c_clkdiv <= (others => '0');
              led_i2c_cnt    <= led_i2c_cnt + 1;
              led_i2c        <= not led_i2c;
              if (led_i2c_cnt = 7) then
                led_i2c_cnt <= (others => '0');
                led_i2c_blink <= '0';
              end if;
            end if;

          when others =>
            led_i2c_blink <= '0';

        end case;
      end if;
    end if;
  end process p_i2c_blink;

  -- Process to set the I2C error LED signal for display on the front panel
  -- of the front module. The I2C error signal is permanently set once an
  -- error is detected from the bridge module.
  p_i2c_err_led : process (clk20_vcxo_i) is
  begin
  if rising_edge(clk20_vcxo_i) then
    if (rst_n = '0') then
      led_i2c_err <= '0';
    elsif (i2c_err_p = '1') then
      led_i2c_err <= '1';
    end if;
  end if;
  end process p_i2c_err_led;

  -- Process to light a LED in case of WDTO error
  p_wdto_led : process (clk20_vcxo_i)
  begin
    if rising_edge(clk20_vcxo_i) then
      if (rst_n = '0') then
        led_wdto <= '0';
      elsif (i2c_wdto_p = '1') then
        led_wdto <= '1';
      end if;
    end if;
  end process p_wdto_led;

  -- Pulse the first LEMO output on the card's front panel when a transfer is
  -- finished. This is used to scope the bus in case of error
  p_trig_oscilloscope : process (clk20_vcxo_i)
  begin
    if rising_edge(clk20_vcxo_i) then
      if (rst_n = '0') then
        i2c_tip_d0 <= '0';
        trig_p     <= '0';
      else
        i2c_tip_d0 <= i2c_tip;
        trig_p     <= (not i2c_tip) and (i2c_tip_d0);
      end if;
    end if;
  end process p_trig_oscilloscope;

  fpga_out_ttl_o(1) <= trig_p;

  --============================================================================
  -- Instantiation and connection of the main Wishbone crossbar
  --============================================================================
  xbar_master_in(0).int <= '0';
  xbar_master_in(0).err <= '0';

  cmp_wb_crossbar : xwb_crossbar
  generic map
  (
    g_num_masters => c_nr_masters,
    g_num_slaves  => c_nr_slaves,
    g_registered  => false,
    g_address     => c_addresses,
    g_mask        => c_masks
  )
  port map
  (
    clk_sys_i => clk20_vcxo_i,
    rst_n_i   => rst_n,
    slave_i   => xbar_slave_in,
    slave_o   => xbar_slave_out,
    master_i  => xbar_master_in,
    master_o  => xbar_master_out
  );

  --============================================================================
  -- Instantiate single-port RAM
  --============================================================================
  cmp_memory: generic_spram
    generic map (
      g_data_width => 32,
      g_size       => 2**12
    )
    port map (
      rst_n_i => rst_n,
      clk_i   => clk20_vcxo_i,
      bwe_i   => (others => '0'),
      we_i    => ram_we,
      a_i     => xbar_master_out(c_slv_mem).adr(11 downto 0),
      d_i     => xbar_master_out(c_slv_mem).dat,
      q_o     => xbar_master_in(c_slv_mem).dat
    );

  ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
            xbar_master_out(c_slv_mem).cyc;

  xbar_master_in(c_slv_mem).ack <= ram_ack;
  xbar_master_in(c_slv_mem).err <= '0';

  p_ram_ack : process (clk20_vcxo_i) is
  begin
    if rising_edge(clk20_vcxo_i) then
      if (rst_n = '0') then
        ram_ack <= '0';
      else
        ram_ack <= '0';
        if (xbar_master_out(c_slv_mem).stb = '1') and
           (xbar_master_out(c_slv_mem).cyc = '1') then
          ram_ack <= '1';
        end if;
      end if;
    end if;
  end process p_ram_ack;

  --============================================================================
  -- Bicolor LED matrix logic
  --============================================================================
  -- Bicolor LED controls, corresponding to the column orders on the
  -- bicolor_led_ctrl unit.

  -- WR address
  bicolor_led_state( 1 downto  0) <= c_LED_OFF;

  -- WR GMT
  bicolor_led_state( 3 downto  2) <= c_LED_OFF;

  -- WR link
  bicolor_led_state( 5 downto  4) <= c_LED_OFF;

  -- WR OK
  bicolor_led_state( 7 downto  6) <= c_LED_OFF;

  -- MULTICAST 0
  bicolor_led_state( 9 downto  8) <= c_LED_RED when led_wdto = '1' else
                                     c_LED_OFF;

  -- MULTICAST 1
  bicolor_led_state(11 downto 10) <= c_LED_OFF;


  -- I2C
  bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
                                     c_LED_RED   when (led_i2c_err = '1') else
                                     c_LED_OFF;

  -- State of TTL/TTL_N switch
  bicolor_led_state(15 downto 14) <= c_LED_OFF;

  -- System error
  bicolor_led_state(17 downto 16) <= c_LED_OFF;

  -- System power
  bicolor_led_state(19 downto 18) <= c_LED_GREEN;

  -- MULTICAST 2
  bicolor_led_state(21 downto 20) <= c_LED_OFF;

  -- MULTICAST 3
  bicolor_led_state(23 downto 22) <= c_LED_OFF;

  cmp_bicolor_led_ctrl : bicolor_led_ctrl
    generic map
    (
      g_NB_COLUMN    => 6,
      g_NB_LINE      => 2,
      g_clk_freq     => 20000000,
      g_refresh_rate => 250
    )
    port map
    (
      clk_i           => clk20_vcxo_i,
      rst_n_i         => rst_n,
      led_intensity_i => "1111111",
      led_state_i     => bicolor_led_state,
      column_o(0)     => led_wr_ownaddr_i2c_o,
      column_o(1)     => led_wr_gmt_ttl_ttln_o,
      column_o(2)     => led_wr_link_syserror_o,
      column_o(3)     => led_wr_ok_syspw_o,
      column_o(4)     => led_multicast_2_0_o,
      column_o(5)     => led_multicast_3_1_o,
      line_o(0)       => led_ctrl0_o,
      line_o(1)       => led_ctrl1_o,
      line_oen_o(0)   => led_ctrl0_oen_o,
      line_oen_o(1)   => led_ctrl1_oen_o
    );

  --============================================================================
  -- Drive unused outputs with safe values
  --============================================================================
  -- Theremometer output to high-impedance
  thermometer_b <= 'Z';

  -- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
  fpga_plldac1_sync_n_o <= '1';
  fpga_plldac1_din_o    <= '0';
  fpga_plldac1_sclk_o   <= '0';
  fpga_plldac2_sync_n_o <= '1';
  fpga_plldac2_din_o    <= '0';
  fpga_plldac2_sclk_o   <= '0';

  -- SFP lines all open-drain, set to high-impedance
  fpga_sfp_rate_select_o <= 'Z';
  fpga_sfp_mod_def1_b    <= 'Z';
  fpga_sfp_mod_def2_b    <= 'Z';
  fpga_sfp_tx_disable_o  <= 'Z';

  -- Pulse outputs and pulse LEDs
  fpga_oe_o           <= '1';
  fpga_blo_oe_o       <= '0';
  fpga_trig_ttl_oe_o  <= '1';
  fpga_inv_oe_o       <= '0';

  pulse_front_led_n_o <= (others => '1');
  pulse_rear_led_n_o  <= (others => '1');
  fpga_out_ttl_o(6 downto 2) <= (others => '0');
  fpga_trig_blo_o     <= (others => '0');
  inv_out_o           <= (others => '0');

  -- Flash outputs
  fpga_prom_cclk_o    <= '0';
  fpga_prom_cso_b_n_o <= '1';
  fpga_prom_mosi_o    <= '0';

end behav;
--==============================================================================
--  architecture end
--==============================================================================

