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-- Title          : Wishbone slave core for Converter board registers
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-- File           : conv_regs.vhd
-- Author         : auto-generated by wbgen2 from conv_regs.wb
-- Created        : Mon Apr  7 16:50:55 2014
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity conv_regs is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(3 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
    reg_bidr_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
    reg_sr_gwvers_i                          : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
    reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
    reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
    reg_sr_i2c_wdto_o                        : out    std_logic;
    reg_sr_i2c_wdto_i                        : in     std_logic;
    reg_sr_i2c_wdto_load_o                   : out    std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
    reg_sr_wrpres_i                          : in     std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
    reg_sr_i2c_err_o                         : out    std_logic;
    reg_sr_i2c_err_i                         : in     std_logic;
    reg_sr_i2c_err_load_o                    : out    std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
    reg_sr_pmisse_o                          : out    std_logic;
    reg_sr_pmisse_i                          : in     std_logic;
    reg_sr_pmisse_load_o                     : out    std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
    reg_cr_rst_unlock_o                      : out    std_logic;
    reg_cr_rst_unlock_i                      : in     std_logic;
    reg_cr_rst_unlock_load_o                 : out    std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
    reg_cr_rst_o                             : out    std_logic;
    reg_cr_rst_i                             : in     std_logic;
    reg_cr_rst_load_o                        : out    std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
    reg_cr_mpt_o                             : out    std_logic_vector(7 downto 0);
    reg_cr_mpt_wr_o                          : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
    reg_ch1pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch1pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch1pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
    reg_ch2pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch2pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch2pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
    reg_ch3pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch3pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch3pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
    reg_ch4pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch4pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch4pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
    reg_ch5pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch5pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch5pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
    reg_ch6pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch6pcr_i                             : in     std_logic_vector(31 downto 0);
    reg_ch6pcr_load_o                        : out    std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
    reg_tvlr_o                               : out    std_logic_vector(31 downto 0);
    reg_tvlr_i                               : in     std_logic_vector(31 downto 0);
    reg_tvlr_load_o                          : out    std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
    reg_tvhr_o                               : out    std_logic_vector(7 downto 0);
    reg_tvhr_i                               : in     std_logic_vector(7 downto 0);
    reg_tvhr_load_o                          : out    std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
    reg_tbmr_chan_i                          : in     std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
    reg_tbmr_wrtag_i                         : in     std_logic;
-- Tag buffer read request, asserted when reading from TBMR
    reg_tb_rd_req_p_o                        : out    std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
    reg_tbcyr_i                              : in     std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
    reg_tbtlr_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
    reg_tbthr_i                              : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
    reg_tbcsr_usedw_i                        : in     std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
    reg_tbcsr_full_i                         : in     std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
    reg_tbcsr_empty_i                        : in     std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
    reg_tbcsr_clr_o                          : out    std_logic;
    reg_tbcsr_clr_i                          : in     std_logic;
    reg_tbcsr_clr_load_o                     : out    std_logic
  );
end conv_regs;

architecture syn of conv_regs is

signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(3 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      reg_sr_i2c_wdto_load_o <= '0';
      reg_sr_i2c_err_load_o <= '0';
      reg_sr_pmisse_load_o <= '0';
      reg_cr_rst_unlock_load_o <= '0';
      reg_cr_rst_load_o <= '0';
      reg_cr_mpt_wr_o <= '0';
      reg_ch1pcr_load_o <= '0';
      reg_ch2pcr_load_o <= '0';
      reg_ch3pcr_load_o <= '0';
      reg_ch4pcr_load_o <= '0';
      reg_ch5pcr_load_o <= '0';
      reg_ch6pcr_load_o <= '0';
      reg_tvlr_load_o <= '0';
      reg_tvhr_load_o <= '0';
      reg_tbcsr_clr_load_o <= '0';
      reg_tb_rd_req_p_o <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          reg_sr_i2c_wdto_load_o <= '0';
          reg_sr_i2c_err_load_o <= '0';
          reg_sr_pmisse_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
          reg_cr_mpt_wr_o <= '0';
          reg_ch1pcr_load_o <= '0';
          reg_ch2pcr_load_o <= '0';
          reg_ch3pcr_load_o <= '0';
          reg_ch4pcr_load_o <= '0';
          reg_ch5pcr_load_o <= '0';
          reg_ch6pcr_load_o <= '0';
          reg_tvlr_load_o <= '0';
          reg_tvhr_load_o <= '0';
          reg_tbcsr_clr_load_o <= '0';
          reg_tb_rd_req_p_o <= '0';
          ack_in_progress <= '0';
        else
          reg_sr_i2c_wdto_load_o <= '0';
          reg_sr_i2c_err_load_o <= '0';
          reg_sr_pmisse_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
          reg_cr_mpt_wr_o <= '0';
          reg_ch1pcr_load_o <= '0';
          reg_ch2pcr_load_o <= '0';
          reg_ch3pcr_load_o <= '0';
          reg_ch4pcr_load_o <= '0';
          reg_ch5pcr_load_o <= '0';
          reg_ch6pcr_load_o <= '0';
          reg_tvlr_load_o <= '0';
          reg_tvhr_load_o <= '0';
          reg_tbcsr_clr_load_o <= '0';
          reg_tb_rd_req_p_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(3 downto 0) is
          when "0000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_bidr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
            if (wb_we_i = '1') then
              reg_sr_i2c_wdto_load_o <= '1';
              reg_sr_i2c_err_load_o <= '1';
              reg_sr_pmisse_load_o <= '1';
            end if;
            rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
            rddata_reg(15 downto 8) <= reg_sr_switches_i;
            rddata_reg(21 downto 16) <= reg_sr_rtm_i;
            rddata_reg(22) <= reg_sr_i2c_wdto_i;
            rddata_reg(23) <= reg_sr_wrpres_i;
            rddata_reg(24) <= reg_sr_i2c_err_i;
            rddata_reg(25) <= reg_sr_pmisse_i;
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010" => 
            if (wb_we_i = '1') then
              reg_cr_rst_unlock_load_o <= '1';
              reg_cr_rst_load_o <= '1';
              reg_cr_mpt_wr_o <= '1';
            end if;
            rddata_reg(0) <= reg_cr_rst_unlock_i;
            rddata_reg(1) <= reg_cr_rst_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011" => 
            if (wb_we_i = '1') then
              reg_ch1pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch1pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100" => 
            if (wb_we_i = '1') then
              reg_ch2pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch2pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101" => 
            if (wb_we_i = '1') then
              reg_ch3pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch3pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110" => 
            if (wb_we_i = '1') then
              reg_ch4pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch4pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111" => 
            if (wb_we_i = '1') then
              reg_ch5pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch5pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000" => 
            if (wb_we_i = '1') then
              reg_ch6pcr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_ch6pcr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001" => 
            if (wb_we_i = '1') then
              reg_tvlr_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= reg_tvlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1010" => 
            if (wb_we_i = '1') then
              reg_tvhr_load_o <= '1';
            end if;
            rddata_reg(7 downto 0) <= reg_tvhr_i;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1011" => 
            if (wb_we_i = '1') then
            end if;
            reg_tb_rd_req_p_o <= '1';
            rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
            rddata_reg(31) <= reg_tbmr_wrtag_i;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= reg_tbcyr_i;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= reg_tbtlr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= reg_tbthr_i;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1111" => 
            if (wb_we_i = '1') then
              reg_tbcsr_clr_load_o <= '1';
            end if;
            rddata_reg(6 downto 0) <= reg_tbcsr_usedw_i;
            rddata_reg(16) <= reg_tbcsr_full_i;
            rddata_reg(17) <= reg_tbcsr_empty_i;
            rddata_reg(18) <= reg_tbcsr_clr_i;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- ID register bits
-- Gateware version
-- Status of on-board switches
-- RTM detection lines~\cite{rtm-det}
-- I2C communication watchdog timeout error
  reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present
-- I2C communication error
  reg_sr_i2c_err_o <= wrdata_reg(24);
-- Pulse missed error
  reg_sr_pmisse_o <= wrdata_reg(25);
-- Reset unlock bit
  reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
  reg_cr_rst_o <= wrdata_reg(1);
-- Manual Pulse Trigger
-- pass-through field: Manual Pulse Trigger in register: CR
  reg_cr_mpt_o <= wrdata_reg(9 downto 2);
-- Pulse counter value
  reg_ch1pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  reg_ch2pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  reg_ch3pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  reg_ch4pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  reg_ch5pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  reg_ch6pcr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 31..0
  reg_tvlr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 39..32
  reg_tvhr_o <= wrdata_reg(7 downto 0);
-- Channel mask
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- Buffer counter
-- Buffer full
-- Buffer empty
-- Clear tag buffer
  reg_tbcsr_clr_o <= wrdata_reg(18);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
