Commit 0dd7106c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Work on release v2.1

hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming

sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle

syn:
- update project file with new files
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent b7a79518
......@@ -2,5 +2,6 @@ files = [
"conv_regs.vhd",
"conv_pulse_gen.vhd",
"conv_man_trig.vhd",
"pulse_timetag.vhd"
"conv_ring_buf.vhd",
"conv_pulse_timetag.vhd"
];
conv_regs.wb
============
If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.
conv_regs.vhd
=============
You need to make some changes to this file after EVERY RUN of wbgen2:
1. Add the following output port declaration after the reg_tbmr_wrtag_i port:
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
2. Assign the port FOUR TIMES in the register bank process:
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
-- [...]
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
-- [...]
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
-- [...]
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
[...]
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
[...]
......@@ -23,8 +23,8 @@
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- isolation transformers on the CONV-TTL-BLO boards. The isolation phase
-- limits the input pulse to 1/5 duty cycle.
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
......@@ -64,7 +64,10 @@ entity conv_pulse_gen is
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -116,19 +119,20 @@ architecture behav of conv_pulse_gen is
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * 5*g_pwidth: 1/5 duty cycle
-- * 5*g_pwidth-5: 5-cycle delay added from the generate phase
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * 5*g_pwidth: 1/5 duty cycle
-- * 5*g_pwidth-2: need one cycle less to allow for true 1/5 duty cycle,
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := 5*g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := 5*g_pwidth-2;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
......@@ -163,7 +167,7 @@ architecture behav of conv_pulse_gen is
signal inh_fp_gf_on : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(6*g_pwidth)-1 downto 0);
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
......
......@@ -40,7 +40,7 @@ use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity pulse_timetag is
entity conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
......@@ -75,14 +75,13 @@ entity pulse_timetag is
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
-- FIFO I/O
fifo_full_i : in std_logic;
fifo_wr_req_p_o : out std_logic
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end entity pulse_timetag;
end entity conv_pulse_timetag;
architecture behav of pulse_timetag is
architecture behav of conv_pulse_timetag is
--============================================================================
-- Signal declarations
......@@ -183,21 +182,21 @@ begin
);
end generate gen_sync_chains;
-- Set the control signals to the FIFO on the rising edge of any pulse channel
p_fifo_ctrl : process (clk_i)
-- Set the control signals to the ring buffer on the rising edge of any
-- pulse channel
p_buf_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fifo_wr_req_p_o <= '0';
buf_wr_req_p_o <= '0';
else
fifo_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0'))
and (fifo_full_i = '0') then
fifo_wr_req_p_o <= '1';
buf_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0')) then
buf_wr_req_p_o <= '1';
end if;
end if;
end if;
end process p_fifo_ctrl;
end process p_buf_ctrl;
-- And delay the pulse rising edge for sampling (this is due to the delayed
-- setting of the write signal to the FIFO)
......
This diff is collapsed.
......@@ -8,11 +8,10 @@ peripheral {
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "id";
prefix = "bidr";
reset_value = "0x54424c4f";
field {
name = "ID register bits";
prefix = "bits";
reset_value = "0x54424c4f";
type = SLV;
size = 32;
......@@ -100,8 +99,8 @@ peripheral {
-- Logic reset bits
field {
name = "Reset unlock bit";
description = "1 - Reset bit unlocked \
0 - Reset bit locked";
description = "1 -- Reset bit unlocked \
0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
access_dev = READ_WRITE;
......@@ -110,8 +109,8 @@ peripheral {
};
field {
name = "Reset bit";
description = "1 - initiate logic reset \
0 - no reset";
description = "1 -- initiate logic reset \
0 -- no reset";
prefix = "rst";
type = BIT;
access_bus = READ_WRITE;
......@@ -247,16 +246,10 @@ peripheral {
};
};
fifo_reg {
size = 128;
name = "Tag FIFO";
prefix = "tf";
direction = CORE_TO_BUS;
flags_bus = {FIFO_COUNT, FIFO_FULL, FIFO_EMPTY, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
clock="clk_wr_i";
reg {
name = "TBMR";
description = "Tag Buffer Meta Register";
prefix = "tbmr";
field {
name = "Channel mask";
description = "Mask for the channel(s) that triggered time-tag storage: \
......@@ -267,8 +260,9 @@ peripheral {
prefix = "chan";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
......@@ -276,32 +270,95 @@ peripheral {
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCYR";
description = "Tag Buffer Cycles Register";
prefix = "tbcyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
prefix = "cyc";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTLR";
description = "Tag Buffer TAI Low Register";
prefix = "tbtlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
prefix = "tai_l";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTHR";
description = "Tag Buffer TAI High Register";
prefix = "tbthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai_h";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCSR";
description = "Tag Buffer Control and Status Register";
prefix = "tbcsr";
field {
name = "Buffer counter";
prefix = "usedw";
description = "Number of samples in the ring buffer";
type = SLV;
size = 7;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer full";
description = "1 -- buffer full \
0 -- buffer is not full";
prefix = "full";
type = BIT;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer empty";
description = "1 -- buffer empty\
0 -- buffer is not empty";
prefix = "empty";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Clear tag buffer";
description = "1 -- clear\
0 -- no effect";
prefix = "clr";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
--==============================================================================
-- CERN (BE-CO-HT)
-- Ring buffer for converter board designs
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-03-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-03-19 Theodor Stana Created file and copied content from
-- fd_ring_buffer.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_ring_buf is
generic
(
-- Buffer data input and output width
g_data_width : positive;
-- Buffer size in number of samples
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end entity conv_ring_buf;
architecture behav of conv_ring_buf is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_fifo_size : positive := 8;
--============================================================================
-- Signal declarations
--============================================================================
-- FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_read : std_logic;
signal fifo_read_d0 : std_logic;
signal fifo_write : std_logic;
signal fifo_in : std_logic_vector(g_data_width-1 downto 0);
signal fifo_out : std_logic_vector(g_data_width-1 downto 0);
-- Buffer signals
signal buf_write : std_logic;
signal buf_read : std_logic;
signal buf_wr_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_rd_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_wr_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_rd_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_count : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_empty : std_logic;
signal buf_full : std_logic;
signal buf_overflow : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Buffer FIFO and RAM
--============================================================================
-- Assign FIFO input and control
fifo_in <= buf_dat_i;
fifo_write <= not fifo_full and buf_wr_req_i;
fifo_read <= not fifo_empty;
-- Instantiate FIFO to synchronize data inputs from read clock to write clock
cmp_clk_adjust_fifo : generic_async_fifo
generic map
(
g_data_width => fifo_in'length,
g_size => c_fifo_size
)
port map (
rst_n_i => rst_n_a_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => fifo_read,
rd_empty_o => fifo_empty);
-- Instantiate the actual buffer RAM
-- The buffer gets fed with data from the FIFO
buf_wr_data <= fifo_out;
cmp_buf_ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => false)
port map (
rst_n_i => rst_n_a_i,
clka_i => clk_rd_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
da_i => buf_wr_data,
qa_o => open,
clkb_i => clk_rd_i,
bweb_i => (others => '0'),
web_i => '0',
ab_i => std_logic_vector(buf_rd_ptr),
db_i => (others => '0'),
qb_o => buf_rd_data);
--============================================================================
-- Buffer control
--============================================================================
-- Assign buffer control signals
buf_write <= fifo_read_d0;
buf_read <= '1' when ((buf_rd_req_i = '1') and (buf_empty = '0')) or
(buf_overflow = '1')
else '0';
buf_overflow <= '1' when (buf_write = '1') and (buf_full = '1') else '0';
-- Buffer control process
p_buffer_control : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if (rst_n_a_i = '0') or (buf_clr_i = '1') then
buf_rd_ptr <= (others => '0');
buf_wr_ptr <= (others => '0');
buf_count <= (others => '0');
buf_full <= '0';
buf_empty <= '1';
fifo_read_d0 <= '0';
else
fifo_read_d0 <= fifo_read;
-- Read and write signals
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
end if;
if(buf_read = '1') then
buf_rd_ptr <= buf_rd_ptr + 1;
end if;
-- Buffer count and full/empty control
if (buf_write = '1') and (buf_read = '0') and (buf_full = '0') then
buf_count <= buf_count + 1;
buf_empty <= '0';
if (buf_count = (buf_count'range => '1')) then
buf_full <= '1';
end if;
end if;
if (buf_write = '0') and (buf_read = '1') and (buf_empty = '0') then
buf_count <= buf_count - 1;
buf_full <= '0';
if (buf_count = 1) then
buf_empty <= '1';
end if;
end if;
end if;
end if;
end process;
--============================================================================
-- Output signals
--============================================================================
buf_full_o <= buf_full;
buf_empty_o <= buf_empty;
buf_count_o <= std_logic_vector(buf_count);
buf_dat_o <= buf_rd_data;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
......@@ -39,12 +39,14 @@ work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := testbench.vhd \
VHDL_SRC := i2c_bus_model.vhd \
testbench.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/Release/conv_pulse_gen.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/Release/pulse_timetag.vhd \
../../modules/Release/conv_ring_buf.vhd \
../../modules/Release/conv_pulse_timetag.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
......@@ -104,7 +106,7 @@ VHDL_SRC := testbench.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
......@@ -136,7 +138,7 @@ VHDL_SRC := testbench.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../modules/Release/conv_regs.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
......@@ -148,12 +150,14 @@ VHDL_SRC := testbench.vhd \
../../top/Release/conv_ttl_blo.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
VHDL_OBJ := work/testbench/.testbench_vhd \
VHDL_OBJ := work/i2c_bus_model/.i2c_bus_model_vhd \
work/testbench/.testbench_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/conv_regs/.conv_regs_vhd \
work/conv_pulse_gen/.conv_pulse_gen_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/pulse_timetag/.pulse_timetag_vhd \
work/conv_ring_buf/.conv_ring_buf_vhd \
work/conv_pulse_timetag/.conv_pulse_timetag_vhd \
work/reset_gen/.reset_gen_vhd \
work/rtm_detector/.rtm_detector_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
......@@ -213,7 +217,7 @@ work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
......@@ -245,7 +249,7 @@ work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/conv_regs/.conv_regs_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
......@@ -339,6 +343,11 @@ work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32
work/i2c_bus_model/.i2c_bus_model_vhd: i2c_bus_model.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/testbench/.testbench_vhd: testbench.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -349,7 +358,7 @@ work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/ge
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -367,12 +376,20 @@ work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg
work/pulse_timetag/.pulse_timetag_vhd: ../../modules/Release/pulse_timetag.vhd
work/conv_ring_buf/.conv_ring_buf_vhd: ../../modules/Release/conv_ring_buf.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/pulse_timetag/.pulse_timetag: \
work/conv_ring_buf/.conv_ring_buf: \
work/genram_pkg/.genram_pkg
work/conv_pulse_timetag/.conv_pulse_timetag_vhd: ../../modules/Release/conv_pulse_timetag.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_pulse_timetag/.conv_pulse_timetag: \
work/gencores_pkg/.gencores_pkg
work/reset_gen/.reset_gen_vhd: ../../modules/reset_gen.vhd
......@@ -812,14 +829,11 @@ work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbo
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -1083,12 +1097,12 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/module
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_regs/.conv_regs: \
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
......@@ -1160,7 +1174,8 @@ work/conv_ttl_blo/.conv_ttl_blo_vhd: ../../top/Release/conv_ttl_blo.vhd
work/conv_ttl_blo/.conv_ttl_blo: \
work/wishbone_pkg/.wishbone_pkg \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg \
work/gencores_pkg/.gencores_pkg
work/gencores_pkg/.gencores_pkg \
work/genram_pkg/.genram_pkg
work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd: ../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
......
target = "xilinx"
action = "simulation"
files = "testbench.vhd"
files = [
"i2c_bus_model.vhd",
"testbench.vhd"
]
modules = { "local" : "../../top/Release" }
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--