Work on release v2.1
hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming
sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle
syn:
- update project file with new files
Signed-off-by: Theodor Stana <t.stana@cern.ch>
Showing
modules/Release/README.txt
0 → 100644
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Please
register
or
sign in
to comment