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Conv TTL Blocking - Gateware
Commit 10351064 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Updated HDL guide to version 3.01

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doc/hdlg/cern-title.tex
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......@@ -11,7 +11,7 @@
\hfill Gateware v3.0
\hfill September 25, 2014
\hfill January 27, 2015
\vspace*{3cm}
......
doc/hdlg/hdlg-conv-ttl-blo.tex
View file @ 10351064
......@@ -84,6 +84,7 @@ work, see \\
timetag FIFO for a timetag ring buffer \\
25-09-2014 & 3.00 & Version 3.0 of gateware, using the new converter board common gateware~\cite{conv-common-gw-ohwr} \newline
\textbf{This version changes the memory map} \\
27-01-2015 & 3.01 & Added repository download commands to Section~\ref{sec:intro} \\
\hline
\end{tabular}
}
......@@ -122,6 +123,16 @@ The HDL for the CONV-TTL-BLO board uses the converter board common gateware~\cit
as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-BLO.
This short HDL guide explains these peculiarities and the corresponding logic implemented.
The HDL files can be obtained by cloning the repository along with its submodules using the following commands:
\begin{footnotesize}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
cd conv-ttl-blo-gw/
git submodule update --init --recursive
\end{verbatim}
\end{footnotesize}
\subsection{Additional documentation}
\begin{itemize}
......@@ -141,12 +152,11 @@ A block diagram of the HDL is shown in Figure~\ref{fig:block-diagram}. This docu
will detail each of the blocks outside the converter common gateware block in the
following sections. The contents of the common gateware block are detailed in the
converter common gateware specification~\cite{conv-common-gw}.
For a more general look at the pulse repetition logic tailored to the CONV-TTL-BLO,
refer to the CONV-TTL-BLO User Guide~\cite{conv-ttl-blo-ug}.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/block-diagram}}
\centerline{\includegraphics[width=.88\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of CONV-TTL-BLO gateware}
\end{figure}
......
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