Small additions to reset_gen component

- changed component description at the top as per Erik's comments - changed generic default value to reflect 20 MHz input clock change at the design level Signed-off-by: Theodor Stana <t.stana@cern.ch>

Small additions to reset_gen component
- changed component description at the top as per Erik's comments - changed generic default value to reflect 20 MHz input clock change at the design level Signed-off-by: Theodor Stana <t.stana@cern.ch>
18bc9038 · Theodor-Adrian Stana · 02f3c449 · 18bc9038
Commit 18bc9038 authored Dec 08, 2013 by Theodor-Adrian Stana
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reset_gen.vhd modules/reset_gen.vhd +8 -8

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--- a/modules/reset_gen.vhd
+++ b/modules/reset_gen.vhd
@@ -10,12 +10,12 @@
 -- version: 1.0
 --
 -- description: 
--    This module generates a variable-width reset pulse. The width of the pulse
--    is set via the g_reset_time pulse; an internal counter counts up to this
--    value and de-asserts the active-low reset line when the value has been
--    reached. At the same time, the module is de-activated.
+--    This module generates a controllable-width reset pulse. The width of the
+--    reset pulse is set via the g_reset_time pulse; an internal counter counts
+--    up to this value and de-asserts the active-low reset line when the value
+--    has been reached. At the same time, the module is de-activated.
 --
--    By default, a 125 MHz clock is assumed (8ns period), resulting in a 96ms
+--    By default, a 20 MHz clock (50 ns period) is assumed, resulting in a 100ms
 --    reset width.
 --
 -- dependencies:
@@ -35,7 +35,7 @@
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
 --==============================================================================
 -- last changes:
--    2013-03-05   Theodor Stana     t.stana@cern.ch     File created
+--    2013-03-05   Theodor Stana    File created
 --==============================================================================
 -- TODO: - 
 --==============================================================================
@@ -49,7 +49,7 @@ entity reset_gen is
  generic
  (
    -- Reset time in number of clk_i cycles
-    g_reset_time : positive := 12_000_000
+    g_reset_time : positive := 2_000_000
  );
  port
  (
@@ -98,7 +98,7 @@ begin
      elsif (cnt_en = '1') then
        rst_n_o <= '0';
        cnt     <= cnt + 1;
-        if (cnt = g_reset_time) then
+        if (cnt = g_reset_time-1) then
          rst_n_o <= '1';
          cnt_en  <= '0';
        end if;