iprog cmd works in synthesized multiboot design

201bc482 · Theodor-Adrian Stana · ce720fdd · 201bc482 · 201bc482 · 201bc482
Commit 201bc482 authored Aug 20, 2013 by Theodor-Adrian Stana
15 changed files
--- a/hdl/multiboot/rtl/multiboot_fsm.vhd
+++ b/hdl/multiboot/rtl/multiboot_fsm.vhd
@@ -60,11 +60,9 @@ entity multiboot_fsm is
    bootsts_img_o   : out std_logic_vector(15 downto 0);
    bootsts_valid_o : out std_logic;

-    -- Data input and outputs for ICAP component
+    -- Ports for the external ICAP component
    icap_dat_i      : in  std_logic_vector(15 downto 0);
    icap_dat_o      : out std_logic_vector(15 downto 0);
-
-    -- Active low chip- and write-enable outputs for ICAP component icap_ce_n_o     : out std_logic;
    icap_ce_n_o     : out std_logic;
    icap_wr_n_o     : out std_logic
  );
@@ -135,10 +133,14 @@ begin
      if (rst_n_i = '0') then
        state     <= IDLE;
        icap_dout <= (others => '0');
+        icap_ce_n <= '1';
+        icap_wr_n <= '1';
      else
        case state is

          when IDLE =>
+            icap_ce_n <= '1';
+            icap_wr_n <= '1';
            if (iprog_i = '1') then
              state     <= DUMMY;
              icap_ce_n <= '0';

--- a/hdl/multiboot/sim/testbench.vhd
+++ b/hdl/multiboot/sim/testbench.vhd
@@ -55,7 +55,7 @@ architecture behav of testbench is
  -- Constant declarations
  --============================================================================
  constant c_clk_per   : time := 8 ns;
-  constant c_rst_width : time := 2 us;
+  constant c_rst_width : time := 130 ns;

  --============================================================================
  -- Component declarations
@@ -163,9 +163,9 @@ begin
  wbs_in.cyc <= wb_cyc;
  wbs_in.stb <= wb_stb;
  wbs_in.we  <= wb_we;
-  wbs_out.ack <= wb_ack;
-  wbs_out.err <= '0';
-  wbs_out.stall <= wb_stall;
+  wb_ack     <= wbs_out.ack;
+  wb_dat_in  <= wbs_out.dat;
+  wb_stall   <= wbs_out.stall;

  --============================================================================
  -- Clock and reset processes
@@ -196,8 +196,10 @@ begin
    write <= '0';
    transfer <= '0';

+    wait for 1500ns;
+
    -- Write to CR
-    wait for 3 us;
+    wait for 200 ns;
    str <= "wr-cr   ";
    adr <= x"00000000";
    dat <= x"00000008";
@@ -206,74 +208,74 @@ begin
    wait for c_clk_per;
    transfer <= '0';

-    -- Read from CR
-    wait for 30 ns;
-    str <= "rd-cr   ";
-    adr <= x"00000000";
-    write <= '0';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- Read from SR
-    wait for 30 ns;
-    str <= "rd-sr   ";
-    valid <= '1';
-    bootsts_img <= x"f3f3";
-    adr <= x"00000004";
-    write <= '0';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- write to GBBAR
-    wait for 30 ns;
-    str <= "wr-gbbar";
-    adr <= x"00000008";
-    dat <= x"0b012345";
-    write <= '1';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- read from GBBAR
-    wait for 30 ns;
-    str <= "rd-gbbar";
-    adr <= x"00000008";
-    write <= '0';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- write to MBBAR
-    wait for 30 ns;
-    str <= "wr-mbbar";
-    adr <= x"0000000C";
-    dat <= x"0b024321";
-    write <= '1';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- read from MBBAR
-    wait for 30 ns;
-    str <= "rd-mbbar";
-    adr <= x"0000000C";
-    write <= '0';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
-
-    -- Read from SR
-    wait for 30 ns;
-    str <= "rd-sr   ";
-    valid <= '1';
-    bootsts_img <= x"3f3f";
-    adr <= x"00000004";
-    write <= '0';
-    transfer <= '1';
-    wait for c_clk_per;
-    transfer <= '0';
+    ---- Read from CR
+    --wait for 30 ns;
+    --str <= "rd-cr   ";
+    --adr <= x"00000000";
+    --write <= '0';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- Read from SR
+    --wait for 30 ns;
+    --str <= "rd-sr   ";
+    --valid <= '1';
+    --bootsts_img <= x"f3f3";
+    --adr <= x"00000004";
+    --write <= '0';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- write to GBBAR
+    --wait for 30 ns;
+    --str <= "wr-gbbar";
+    --adr <= x"00000008";
+    --dat <= x"0b012345";
+    --write <= '1';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- read from GBBAR
+    --wait for 30 ns;
+    --str <= "rd-gbbar";
+    --adr <= x"00000008";
+    --write <= '0';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- write to MBBAR
+    --wait for 30 ns;
+    --str <= "wr-mbbar";
+    --adr <= x"0000000C";
+    --dat <= x"0b024321";
+    --write <= '1';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- read from MBBAR
+    --wait for 30 ns;
+    --str <= "rd-mbbar";
+    --adr <= x"0000000C";
+    --write <= '0';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';
+
+    ---- Read from SR
+    --wait for 30 ns;
+    --str <= "rd-sr   ";
+    --valid <= '1';
+    --bootsts_img <= x"3f3f";
+    --adr <= x"00000004";
+    --write <= '0';
+    --transfer <= '1';
+    --wait for c_clk_per;
+    --transfer <= '0';

    -- wait indefinitely
    wait;

--- a/hdl/multiboot/sim/transcript
+++ b/hdl/multiboot/sim/transcript
--- a/hdl/multiboot/sim/vsim.dbg
+++ b/hdl/multiboot/sim/vsim.dbg
--- a/hdl/multiboot/sim/wave.do
+++ b/hdl/multiboot/sim/wave.do
@@ -24,9 +24,24 @@ add wave -noupdate -radix hexadecimal /testbench/valid
 add wave -noupdate -radix hexadecimal /testbench/mbbar
 add wave -noupdate -radix hexadecimal /testbench/gbbar
 add wave -noupdate /testbench/str
+add wave -noupdate -divider FSM
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/gbbar_i
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/mbbar_i
+add wave -noupdate /testbench/UUT/cmp_fsm/bootsts_img_o
+add wave -noupdate /testbench/UUT/cmp_fsm/bootsts_valid_o
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/icap_dat_i
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/icap_dat_o
+add wave -noupdate /testbench/UUT/cmp_fsm/icap_ce_n_o
+add wave -noupdate /testbench/UUT/cmp_fsm/icap_wr_n_o
+add wave -noupdate /testbench/UUT/cmp_fsm/state
+add wave -noupdate -divider ICAP
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_icap/I
+add wave -noupdate /testbench/UUT/cmp_icap/prog_b
+add wave -noupdate /testbench/UUT/cmp_icap/init_b
+add wave -noupdate /testbench/UUT/cmp_icap/done_o
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3034 ns} 0}
-configure wave -namecolwidth 188
+WaveRestoreCursors {{Cursor 1} {2075 ns} 0}
+configure wave -namecolwidth 276
 configure wave -valuecolwidth 99
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
@@ -40,4 +55,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {3718 ns}
+WaveRestoreZoom {0 ns} {7720 ns}
--- a/hdl/multiboot/syn/Makefile
+++ b/hdl/multiboot/syn/Makefile
--- a/hdl/multiboot/syn/Manifest.py
+++ b/hdl/multiboot/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "conv_ttl_blo"
+syn_project = "conv_ttl_blo.xise"
+
+modules = {
+    "local" : [
+        "../top"
+      ]
+    }
--- a/hdl/multiboot/syn/conv_ttl_blo.bit
+++ b/hdl/multiboot/syn/conv_ttl_blo.bit
--- a/hdl/multiboot/syn/conv_ttl_blo.gise
+++ b/hdl/multiboot/syn/conv_ttl_blo.gise
--- a/hdl/multiboot/syn/conv_ttl_blo.xise
+++ b/hdl/multiboot/syn/conv_ttl_blo.xise
--- a/hdl/multiboot/syn/run.tcl
+++ b/hdl/multiboot/syn/run.tcl
+project open conv_ttl_blo.xise
+process run {Generate Programming File} -force rerun_all
--- a/hdl/multiboot/top/Manifest.py
+++ b/hdl/multiboot/top/Manifest.py
+files = [
+      "conv_regs.vhd",
+      "conv_ttl_blo.ucf",
+      "conv_ttl_blo.vhd"
+    ]
+
+modules = {
+      "local" : [
+          "../../rtm_detector",
+          "../../reset_gen",
+          "../../bicolor_led_ctrl",
+          "../../vbcp_wb",
+          "../rtl"
+        ],
+      "git" : [
+          "git://ohwr.org/hdl-core-lib/general-cores.git"
+        ]
+    }
+
+fetchto = "../../../../../ip_cores"
--- a/hdl/multiboot/top/conv_regs.vhd
+++ b/hdl/multiboot/top/conv_regs.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Converter board registers
+---------------------------------------------------------------------------------------
+-- File           : conv_regs.vhd
+-- Author         : auto-generated by wbgen2 from conv_regs.wb
+-- Created        : Fri Aug  2 16:02:13 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity conv_regs is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(1 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+    conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
+    conv_regs_sr_fwvers_i                    : in     std_logic_vector(15 downto 0);
+-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
+    conv_regs_sr_switches_i                  : in     std_logic_vector(7 downto 0);
+-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
+    conv_regs_sr_rtm_i                       : in     std_logic_vector(5 downto 0);
+-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+    conv_regs_cr_rst_unlock_o                : out    std_logic;
+-- Port for BIT field: 'Reset bit' in reg: 'Control register'
+    conv_regs_cr_rst_o                       : out    std_logic
+  );
+end conv_regs;
+
+architecture syn of conv_regs is
+
+signal conv_regs_id_bits_int                    : std_logic_vector(31 downto 0);
+signal conv_regs_cr_rst_unlock_int              : std_logic      ;
+signal conv_regs_cr_rst_int                     : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(1 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      conv_regs_id_bits_int <= x"424c4f32";
+      conv_regs_cr_rst_unlock_int <= '0';
+      conv_regs_cr_rst_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(1 downto 0) is
+          when "00" => 
+            if (wb_we_i = '1') then
+              conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
+            rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
+            rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
+            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10" => 
+            if (wb_we_i = '1') then
+              conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
+              conv_regs_cr_rst_int <= wrdata_reg(31);
+            end if;
+            rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
+            rddata_reg(31) <= conv_regs_cr_rst_int;
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            rddata_reg(30) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- bits
+  conv_regs_id_bits_o <= conv_regs_id_bits_int;
+-- fwvers
+-- switches
+-- RTM detection
+-- Reset unlock bit
+  conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
+-- Reset bit
+  conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/hdl/multiboot/top/conv_ttl_blo.ucf
+++ b/hdl/multiboot/top/conv_ttl_blo.ucf
--- a/hdl/multiboot/top/conv_ttl_blo.vhd
+++ b/hdl/multiboot/top/conv_ttl_blo.vhd