Commit 23cf4ac4 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Added reject stage to ctb_pulse_gen, modified in top-level

parent 8aaf2d8f
This diff is collapsed.
vlib work
# vcom -explicit -93 "../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
# vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/genram_pkg.vhd"
vcom -explicit -93 "../../pulse_gen_gp/rtl/pulse_gen_gp.vhd"
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/ctb_pulse_gen.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
glitch_filt_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component ctb_pulse_gen;
component pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen_gp;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal gf_en : std_logic;
signal gf_en_n : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
DUT: ctb_pulse_gen
generic map
(
g_pulse_width => 150,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
glitch_filt_en_n_i => gf_en_n,
en_i => '1',
trig_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- SECOND CLOCK GENERATION
p_clk2: process
begin
clk2 <= not clk2;
wait for 2 ns;
end process p_clk2;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen: pulse_gen_gp
generic map
(
g_pwidth => 5,
g_freq => 751
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => trig
);
actual_trig <= trig;
actual_pulse <= pulse;
cmp_pulse_gen_gp: pulse_gen_gp
generic map
(
g_pwidth => 1033,
g_freq => 2066
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => gf_en
);
gf_en_n <= '1'; --not gf_en;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-51-generic-pae
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity glitch_filt
# -- Compiling architecture behav of glitch_filt
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity ctb_pulse_gen
# -- Compiling architecture behav of ctb_pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.ctb_pulse_gen(behav)#1
# Loading work.glitch_filt(behav)#1
# Loading work.pulse_gen_gp(behav)#1
# Loading work.pulse_gen_gp(behav)#2
# hexadecimal
# 0 ps
# 105 us
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/actual_pulse
add wave -noupdate /testbench/gf_en
add wave -noupdate /testbench/gf_en_n
add wave -noupdate -divider ctb_pulse_gen
add wave -noupdate /testbench/DUT/trig_i
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/trig_degl
add wave -noupdate /testbench/DUT/trig_degl_d0
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse_gf_off
add wave -noupdate /testbench/DUT/pulse_gf_off_d0
add wave -noupdate /testbench/DUT/pulse_gf_off_d1
add wave -noupdate /testbench/DUT/pulse_gf_off_d2
add wave -noupdate /testbench/DUT/pulse_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {16056000 ps} 0}
configure wave -namecolwidth 182
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {9493496 ps} {22618504 ps}
......@@ -39,7 +39,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctb_pulse_gen_gp is
entity pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
......@@ -53,10 +53,10 @@ entity ctb_pulse_gen_gp is
en_i : in std_logic;
pulse_o : out std_logic
);
end entity ctb_pulse_gen_gp;
end entity pulse_gen_gp;
architecture behav of ctb_pulse_gen_gp is
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Thu Jun 20 15:54:31 2013
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
......@@ -91,6 +91,7 @@ begin
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
......
......@@ -50,6 +50,48 @@ peripheral {
name = "Control register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
......
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738664" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452218" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738681" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1371738664">
<transform xil_pn:end_ts="1375452236" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1375452218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1371738681" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1371738681">
<transform xil_pn:end_ts="1375452236" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1375452236">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1371738690" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1371738681">
<transform xil_pn:end_ts="1375452245" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1375452236">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1371738728" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1371738690">
<transform xil_pn:end_ts="1375452333" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1375452245">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1371738765" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1371738728">
<transform xil_pn:end_ts="1375452372" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1375452333">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1371738787" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1371738765">
<transform xil_pn:end_ts="1375452394" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1375452372">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1371738765" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1371738754">
<transform xil_pn:end_ts="1375452372" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375452361">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
......@@ -348,19 +348,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../rtl/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
......@@ -369,16 +369,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../elma_i2c/rtl/elma_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -399,7 +399,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -645,7 +645,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
</files>
......
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-trig-blo
-- http://www.ohwr.org/projects/conv-trig_a-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo_v2.vhd
......@@ -40,6 +40,7 @@ use UNISIM.VCOMPONENTS.ALL;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
entity conv_ttl_blo_v2 is
generic
......@@ -113,6 +114,7 @@ architecture behav of conv_ttl_blo_v2 is
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (1 to g_nr_ttl_chan) of unsigned(13 downto 0);
type t_pulse_led_cnt is array (1 to g_nr_ttl_chan) of unsigned(22 downto 0);
--============================================================================
-- Constant declarations
......@@ -176,37 +178,36 @@ architecture behav of conv_ttl_blo_v2 is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
g_pwidth : natural := 15;
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
g_gf_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse type input
-- '1' - TYPE 1 (glitch-sensitive, without output jitter)
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- TYPE 1 pulse: none
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+3 clk_i cycles
pulse_o : out std_logic
);
end component ctb_pulse_gen;
......@@ -222,7 +223,7 @@ architecture behav of conv_ttl_blo_v2 is
);
end component rtm_detector;
component ctb_pulse_gen_gp is
component pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
......@@ -236,7 +237,7 @@ architecture behav of conv_ttl_blo_v2 is
en_i : in std_logic;
pulse_o : out std_logic
);
end component ctb_pulse_gen_gp;
end component pulse_gen_gp;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
......@@ -325,9 +326,11 @@ architecture behav of conv_ttl_blo_v2 is
signal switches_n : std_logic_vector(7 downto 0);
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_ttl_a, trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
......@@ -335,6 +338,8 @@ architecture behav of conv_ttl_blo_v2 is
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
signal blo_ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
......@@ -343,6 +348,7 @@ architecture behav of conv_ttl_blo_v2 is
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_cnt;
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
......@@ -587,16 +593,27 @@ begin
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i and ttlbar_nosig_n;
-- Then, the blocking trigger
trig_blo <= fpga_blo_in_i;
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig <= trig_ttl or trig_blo;
trig_a <= trig_ttl_a or trig_blo_a;
gen_ttl_pulse_generators : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk125 domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk125,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Process to detect lack of signal on TTL line
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
......@@ -621,54 +638,62 @@ begin
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 150,
g_glitch_filt_len => 4
g_pwidth => 150,
g_gf_len => 4
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => '1',
pulse_type_i => extra_switch_n_i(1),
trig_i => trig(i),
pulse_o => pulse_outputs(i)
clk_i => clk125,
rst_n_i => rst_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_i => trig_a(i),
pulse_o => pulse_outputs(i)
);
-- Status LED pulse generators
cmp_led_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 12*(10**6),
g_glitch_filt_len => 4
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => '1',
pulse_type_i => extra_switch_n_i(1),
trig_i => trig(i),
pulse_o => pulse_leds(i)
);
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse_outputs when (ttl_switch_n_i = '0') else
not pulse_outputs;
fpga_trig_blo_o <= pulse_outputs;
-- Process to flash pulse LED on pulse reception
p_pulse_led : process (clk125, rst_n) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (trig_synced_edge(i) = '1') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process;
end generate gen_ttl_pulse_generators;
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse_outputs when (ttl_switch_n_i = '0') else
not pulse_outputs;
fpga_trig_blo_o <= pulse_outputs;
-- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else
(others => '0');
(others => '1');
pulse_rear_led_n_o <= (not pulse_leds) when (blo_oe = '1') else
(others => '0');
(others => '1');
--============================================================================
-- General-purpose INV TTL outputs
--============================================================================
inv_out_o <= inv_in_n_i;
-- cmp_tmp_pulse_gen : ctb_pulse_gen_gp
-- cmp_tmp_pulse_gen : pulse_gen_gp
-- generic map
-- (
-- g_pwidth => 100,
......
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