Commit 2710324a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Checking something on i2c-test branch

parent 8760fc48
......@@ -14,7 +14,7 @@ NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
#TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
......
......@@ -17,23 +17,23 @@
<files>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
......@@ -41,7 +41,7 @@
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
......@@ -81,7 +81,7 @@
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
......@@ -141,7 +141,7 @@
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
......@@ -149,7 +149,7 @@
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
......@@ -186,7 +186,7 @@
</file>
<file xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
This diff is collapsed.
......@@ -65,60 +65,11 @@ package image1_pkg is
constant c_WB_CLK_PERIOD : TIME := (c_CLKOUTA_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_CLKB_PERIOD : TIME := (c_CLKOUTB_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_RST_TIME : TIME := 250 ns;
constant c_RST_TIME : TIME := 250 ns;
constant c_RST_PLL_CLKS : NATURAL := c_RST_TIME/c_PLL_IN_PERIOD;
constant c_RST_A_CLKS : NATURAL := c_RST_TIME/c_WB_CLK_PERIOD;
constant c_RST_B_CLKS : NATURAL := c_RST_TIME/c_CLKB_PERIOD;
constant c_NUM_MASTERS : NATURAL := 1;
constant c_NUM_SLAVES : NATURAL := 2;
constant c_MASTER_I2C_SLAVE : NATURAL := 0;
constant c_SLAVE_I2C_SLAVE : NATURAL := 0;
-- !!!!!!!!!!!!!!!!
constant c_slave_trigleds_wb : natural := 1;
-- !!!!!!!!!!!!!!!!
constant c_SLAVE_MULTIBOOT : NATURAL := 1;
constant c_SLAVE_M25P32 : NATURAL := 2;
--! ==================================
--! MEMORY MAPPINGS
--! ==================================
--! Byte aligned
--! It should be noted that all internal modules are word aligned.
--! Thus, access to byte 1,2 or 3 within an internal word register
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
-- !!
constant c_addr_trigleds_wb : t_wishbone_address := X"00000080";
--! 64 words per page: 6 + 1 bits
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFE00";
constant c_MASK_MULTIBOOT : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
-- !!!!!!!
constant c_mask_trigleds_wb : t_wishbone_address := X"FFFFFFC0";
constant c_addresses : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (--c_ADDR_M25P32,
--c_ADDR_MULTIBOOT,
c_addr_trigleds_wb,
c_ADDR_I2C_SLAVE);
constant c_masks : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (--c_MASK_M25P32,
-- c_MASK_MULTIBOOT,
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
-- component basic_trigger_top
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
-- g_CLK_PERIOD : TIME := 20 ns;
......@@ -194,53 +145,53 @@ package image1_pkg is
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port(wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC);
end component;
component multiboot_top
generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr);
--! This is a vendor-dependant SPI opcode.
--! Pleasem take a look to the flash memory manual and put here
--! the op-code/instruction-code for a read operation over SPI
--! i.e. for m25p32 memory that corresponds to X"03"
--! Set it up accordingly.
g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
port(wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end component;
-- component m25p32_top
-- generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
-- port(wb_rst_i : in STD_LOGIC;
-- wb_clk_i : in STD_LOGIC;
--
-- wb_we_i : in STD_LOGIC;
-- wb_stb_i : in STD_LOGIC;
-- wb_cyc_i : in STD_LOGIC;
-- wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
-- wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
-- wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
-- wb_ack_o : out STD_LOGIC;
-- wb_rty_o : out STD_LOGIC;
-- wb_err_o : out STD_LOGIC;
--
-- miso_word_rcv : out STD_LOGIC;
-- op_finished_o : out STD_LOGIC;
--
-- prom_mosi_o : out STD_LOGIC;
-- prom_cclk_o : out STD_LOGIC;
-- prom_cs0_b_n_o : out STD_LOGIC;
-- prom_din_i : in STD_LOGIC);
-- end component;
--
-- component multiboot_top
-- generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
-- g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr);
-- --! This is a vendor-dependant SPI opcode.
-- --! Pleasem take a look to the flash memory manual and put here
-- --! the op-code/instruction-code for a read operation over SPI
-- --! i.e. for m25p32 memory that corresponds to X"03"
-- --! Set it up accordingly.
-- g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
-- port(wb_rst_i : in STD_LOGIC;
-- wb_clk_i : in STD_LOGIC;
-- wb_we_i : in STD_LOGIC;
-- wb_stb_i : in STD_LOGIC;
-- wb_cyc_i : in STD_LOGIC;
-- wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
-- wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
-- wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_ack_o : out STD_LOGIC;
-- wb_rty_o : out STD_LOGIC;
-- wb_err_o : out STD_LOGIC);
-- end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
......
peripheral {
name = "Wishbone interface for CONV-TTL-BLO status register";
hdl_entity = "statregs";
prefix = "sr";
-- lower 32 bits of SR corresponding to IDENT_L
reg {
name = "SR_L";
prefix = "l";
field {
name = "IDENT_L";
description = "Lower 32 bits of IDENT register";
prefix = "ident_l";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Upper 32 bits of SR
reg {
name = "SR_H";
prefix = "h";
field {
name = "IDENT_H";
description = "Upper 16 bits of IDENT register";
prefix = "ident_h";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTMM";
description = "RTMM identification bits";
prefix = "rtmm";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTMP";
description = "RTMP identification bits";
prefix = "rtmp";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone interface for CONV-TTL-BLO status register
---------------------------------------------------------------------------------------
-- File : statregs.vhd
-- Author : auto-generated by wbgen2 from sr.wb
-- Created : Fri Feb 22 17:54:47 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity statregs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'IDENT_L' in reg: 'SR_L'
sr_l_ident_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'IDENT_H' in reg: 'SR_H'
sr_h_ident_h_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'RTMM' in reg: 'SR_H'
sr_h_rtmm_i : in std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'RTMP' in reg: 'SR_H'
sr_h_rtmp_i : in std_logic_vector(2 downto 0)
);
end statregs;
architecture syn of statregs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= sr_l_ident_l_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= sr_h_ident_h_i;
rddata_reg(18 downto 16) <= sr_h_rtmm_i;
rddata_reg(21 downto 19) <= sr_h_rtmp_i;
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- IDENT_L
-- IDENT_H
-- RTMM
-- RTMP
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
......@@ -42,10 +42,6 @@ use work.wishbone_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
);
port
(
RST : in std_logic;
......@@ -66,12 +62,12 @@ entity image1_top is
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
PULSE_FRONT_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED_N : out std_logic_vector(6 downto 1);
PULSE_REAR_LED_N : out std_logic_vector(6 downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(6 downto 1);
FPGA_OUT_TTL : out std_logic_vector(6 downto 1);
FPGA_BLO_IN : in std_logic_vector(6 downto 1);
FPGA_TRIG_BLO : out std_logic_vector(6 downto 1);
INV_IN_N : in std_logic_vector(4 downto 1);
INV_OUT : out std_logic_vector(4 downto 1);
......@@ -95,10 +91,16 @@ entity image1_top is
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
LEVEL : in std_logic;--TTL/INV_TTL_N
EXTRA_SWITCH : in std_logic_vector(1 downto 1);--! General enable
MR_N : out std_logic;-- It allows power sequencing of the
-- 24V rail after a security given delay
--TTL/INV_TTL_N
LEVEL : in std_logic;
EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
MR_N : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
......@@ -148,7 +150,7 @@ architecture Behavioral of image1_top is
-- Enable signals
fpga_en_o : out std_logic;
fpga_out_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
......@@ -175,7 +177,7 @@ architecture Behavioral of image1_top is
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal switch : std_logic_vector(1 downto 1);
signal switch : std_logic_vector(7 downto 1);
signal rtmm, rtmp : std_logic_vector(2 downto 0);
......@@ -223,7 +225,10 @@ begin
switch <= EXTRA_SWITCH;
cmp_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
generic map
(
g_number_of_channels => 6
)
port map
(
rst_i => RST,
......@@ -244,7 +249,7 @@ begin
fpga_gap_i => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_en_o => FPGA_OE,
fpga_out_en_o => FPGA_OE,
fpga_blo_en_o => FPGA_BLO_OE,
fpga_ttl_en_o => FPGA_TRIG_TTL_OE,
fpga_inv_en_o => FPGA_INV_OE,
......
......@@ -43,7 +43,7 @@ entity basic_trigger_top is
led_ttl_o : out std_logic;
-- Enable signals
fpga_en_o : out std_logic;
fpga_out_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
......@@ -124,27 +124,27 @@ begin
-- +---------+-----------------+
-- | level_i | Switch | Level |
-- +---------+---------+-------+
-- | 0 TTL | UP | TTL |
-- | 1 TTL_N | DOWN | TTL_N |
-- | 0 | UP | TTL |
-- | 1 | DOWN | TTL_N |
-- +---------+---------+-------+
level <= level_i;
led_ttl_o <= level;
-- pulse signal assignments
pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_front_i;
pulse_in <= pulse_in_front or pulse_rear_i;
pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_front_i;
pulse_in <= pulse_in_front or pulse_rear_i;
fpga_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_out_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_ttl_en_o <= fpga_out_ttl_en;
fpga_inv_en_o <= fpga_out_inv_en;
fpga_blo_en_o <= fpga_out_blo_en;
led_front_o <= not(led); -- No need of accurate sync, hence we place
led_rear_o <= not(led); -- some combinatorial here.
led_front_o <= led; -- No need of accurate sync, hence we place
led_rear_o <= led; -- some combinatorial here.
pulse_front_o <= pulse_out when level = '0' else
not pulse_out;
pulse_front_o <= pulse_out when level = '0' else
pulse_out_n;
pulse_rear_o <= pulse_out;
-- As we have one Schmitt inverter in the input,
......@@ -153,7 +153,7 @@ begin
inv_o <= inv_i;
gen_trig_cores: for i in 1 to g_number_of_channels generate
trigger: basic_trigger_core
cmp_repeater: basic_trigger_core
generic map
(
g_clk_period => g_clk_period,
......
......@@ -237,17 +237,22 @@ begin
when others =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
when c_CTR0_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr =>
when c_LT_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr =>
when c_DTX_addr =>
wb_slave_dat_o <= s_DTX;
when c_DRXA_addr =>
when c_DRXA_addr =>
wb_slave_dat_o <= DRXA_i;
when c_DRXB_addr =>
when c_DRXB_addr =>
wb_slave_dat_o <= DRXB_i;
when others =>
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
......@@ -260,7 +265,6 @@ begin
-- This is the process that controls the wishbone master interface
-- which bridges the i2c interface with the wishbone interface.
-- wb_clk_i Main clock
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
......
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