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Conv TTL Blocking - Gateware
Commit 46f990ca authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Work towards lower pulse duty cycle and detecting missed pulses 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 6e3c1c77
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Showing with 145 additions and 56 deletions
modules/Release/conv_regs.vhd
View file @ 46f990ca
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Mon Mar 24 09:06:14 2014
-- Created : Fri Mar 28 18:31:00 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
......@@ -41,6 +41,10 @@ entity conv_regs is
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Missed pulse error bit' in reg: 'SR'
reg_sr_pmiss_o : out std_logic;
reg_sr_pmiss_i : in std_logic;
reg_sr_pmiss_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -139,6 +143,7 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -159,6 +164,7 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -175,6 +181,7 @@ begin
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -201,13 +208,14 @@ begin
when "0001" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
reg_sr_pmiss_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= 'X';
rddata_reg(24) <= reg_sr_pmiss_i;
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -468,6 +476,8 @@ begin
-- Communication watchdog timer status
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present
-- Missed pulse error bit
reg_sr_pmiss_o <= wrdata_reg(24);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
......
modules/Release/conv_regs.wb
View file @ 46f990ca
......@@ -87,6 +87,16 @@ peripheral {
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Missed pulse error bit";
description = "1 -- pulse arrived during pulse rejection phase \
0 -- idle";
prefix = "pmiss";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
......
modules/Release/ctblo_pulse_gen.vhd
View file @ 46f990ca
......@@ -72,26 +72,30 @@ entity ctblo_pulse_gen is
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_a_i : in std_logic;
-- Pulse error output, active-high when a pulse arrives during the
-- pulse rejection phase
pulse_err_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
pulse_o : out std_logic
);
end entity ctblo_pulse_gen;
......@@ -151,26 +155,28 @@ architecture behav of ctblo_pulse_gen is
-- Signal declarations
--============================================================================
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
-- Inhibit first pulse
signal inh_fp_gf_on : std_logic;
signal inh_fp_gf_on : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
signal state : t_state;
--==============================================================================
-- architecture begin
......@@ -203,23 +209,39 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
pulse_gf_off_r_edge_p <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
end if;
end if;
end process p_sync_pulse_gf_off;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
else
trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
end if;
end if;
end process p_trig_gf_on;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Generate the FSM logic
p_pulse_width: process(clk_i)
begin
......@@ -229,12 +251,9 @@ begin
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
trig_gf_on_d0 <= '0';
inh_fp_gf_on <= '1';
pulse_err_o <= '0';
elsif (en_i = '1') then
-- Deglitched trigger delay.
trig_gf_on_d0 <= trig_gf_on;
-- On the first cycle after the reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
-- since in this mode, an unconnected channel is HIGH for the first
......@@ -256,13 +275,13 @@ begin
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_d1 = '1') and (pulse_gf_off_d2 = '0') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
end if;
else
if (trig_gf_on = '1') and (trig_gf_on_d0 = '0') and
(inh_fp_gf_on = '0') then
if (trig_gf_on_r_edge_p = '1') and (inh_fp_gf_on = '0') then
state <= GEN_GF_ON;
end if;
end if;
......@@ -289,6 +308,9 @@ begin
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
if (pulse_gf_off_r_edge_p = '1') then
pulse_err_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
......@@ -313,6 +335,9 @@ begin
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
if (trig_gf_on_r_edge_p = '1') then
pulse_err_o <= '1';
end if;
when others =>
state <= IDLE;
......
sim/Release/Makefile
View file @ 46f990ca
......@@ -43,7 +43,7 @@ VHDL_SRC := i2c_bus_model.vhd \
testbench.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/Release/conv_pulse_gen.vhd \
../../modules/Release/ctblo_pulse_gen.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/Release/conv_ring_buf.vhd \
../../modules/Release/conv_pulse_timetag.vhd \
......@@ -154,7 +154,7 @@ VHDL_OBJ := work/i2c_bus_model/.i2c_bus_model_vhd \
work/testbench/.testbench_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/conv_regs/.conv_regs_vhd \
work/conv_pulse_gen/.conv_pulse_gen_vhd \
work/ctblo_pulse_gen/.ctblo_pulse_gen_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/conv_ring_buf/.conv_ring_buf_vhd \
work/conv_pulse_timetag/.conv_pulse_timetag_vhd \
......@@ -363,7 +363,7 @@ work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
@mkdir -p $(dir $@) && touch $@
work/conv_pulse_gen/.conv_pulse_gen_vhd: ../../modules/Release/conv_pulse_gen.vhd
work/ctblo_pulse_gen/.ctblo_pulse_gen_vhd: ../../modules/Release/ctblo_pulse_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
sim/Release/testbench.vhd
View file @ 46f990ca
......@@ -444,9 +444,9 @@ begin
--============================================================================
-- Pulse outputs assignment based on OE signals
--============================================================================
ttl_pulse <= ttl_outp when oe = '1' and ttl_oe = '1' else (others => '0');
blo_pulse <= blo_outp when oe = '1' and blo_oe = '1' else (others => '0');
inv_pulse <= blo_outp when oe = '1' and inv_oe = '1' else (others => '0');
ttl_pulse <= ttl_outp when (oe = '1') and (ttl_oe = '1') else (others => '0');
blo_pulse <= blo_outp when (oe = '1') and (blo_oe = '1') else (others => '0');
inv_pulse <= blo_outp when (oe = '1') and (inv_oe = '1') else (others => '0');
--============================================================================
-- Switches
......@@ -478,7 +478,7 @@ begin
ttl_inp_n(6) <= '1';
wait until t = true;
while (t = true) loop
wait for 5.561 us;
wait for 240 us;
ttl_inp_n(6) <= '0';
wait for 500 ns;
ttl_inp_n(6) <= '1';
......
top/Release/conv_ttl_blo.vhd
View file @ 46f990ca
......@@ -205,7 +205,7 @@ architecture behav of conv_ttl_blo is
------------------------------------------------------------------------------
-- CONV_REGS [000-020]
-- MULTIBOOT [040-050]
-- ONEWIRE [080-]
-- ONEWIRE [080-084]
------------------------------------------------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
......@@ -242,7 +242,7 @@ architecture behav of conv_ttl_blo is
-- Pulse generator glitch filter length
------------------------------------------------------------------------------
constant c_pulse_gen_pwidth : positive := 24;
constant c_pulse_gen_duty_cycle_div : positive := 500;
constant c_pulse_gen_duty_cycle_div : positive := 200;
constant c_pulse_gen_gf_len : positive := 1;
------------------------------------------------------------------------------
......@@ -299,26 +299,30 @@ architecture behav of conv_ttl_blo is
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_a_i : in std_logic;
-- Pulse error output, active-high when a pulse arrives during the
-- pulse rejection phase
pulse_err_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
pulse_o : out std_logic
);
end component ctblo_pulse_gen;
......@@ -366,6 +370,10 @@ architecture behav of conv_ttl_blo is
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Missed pulse error bit' in reg: 'SR'
reg_sr_pmiss_o : out std_logic;
reg_sr_pmiss_i : in std_logic;
reg_sr_pmiss_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -591,6 +599,9 @@ architecture behav of conv_ttl_blo is
signal wdto_bit : std_logic;
signal wdto_bit_rst : std_logic;
signal wdto_bit_rst_ld : std_logic;
signal pmiss_bit : std_logic;
signal pmiss_bit_rst : std_logic;
signal pmiss_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -612,6 +623,7 @@ architecture behav of conv_ttl_blo is
signal trig_man : std_logic_vector(g_nr_ttl_chan downto 1);
signal pgen_trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal pcnt_trig_p : std_logic_vector(g_nr_ttl_chan downto 1);
signal pmiss : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
......@@ -729,7 +741,18 @@ begin
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge : wb_i2c_bridge
generic map
(
g_fsm_wdt => 480000
)
port map
(
-- Clock, reset
......@@ -834,6 +857,21 @@ begin
end if;
end process p_sr_wdto_bit;
-- Register for the PMISS bit in the SR, set by ANY channel missing a pulse,
-- cleared by writing a '1' to it
p_sr_pmiss_bit : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
pmiss_bit <= '0';
elsif not (pmiss = (pmiss'range => '0')) then
pmiss_bit <= '1';
elsif (pmiss_bit_rst_ld = '1') and (pmiss_bit_rst = '1') then
pmiss_bit <= '0';
end if;
end if;
end process p_sr_pmiss_bit;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
......@@ -880,6 +918,7 @@ begin
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_bidr_i => c_board_id,
reg_sr_gwvers_i => c_gwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
......@@ -887,6 +926,10 @@ begin
reg_sr_i2c_wdto_i => wdto_bit,
reg_sr_i2c_wdto_load_o => wdto_bit_rst_ld,
reg_sr_wrpres_i => wrpres,
reg_sr_pmiss_o => pmiss_bit_rst,
reg_sr_pmiss_i => pmiss_bit,
reg_sr_pmiss_load_o => pmiss_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
......@@ -1222,12 +1265,13 @@ begin
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_a_i => pgen_trig(i),
pulse_o => pulse_outp(i)
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_a_i => pgen_trig(i),
pulse_err_o => pmiss(i),
pulse_o => pulse_outp(i)
);
-- Process to flash pulse LED when a pulse is output
......
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