Commit 4e0ed399 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Added constraints for 125 MHz clock net

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 12d56e6a
......@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......@@ -310,7 +314,7 @@
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
......
......@@ -13,9 +13,9 @@
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
......@@ -28,7 +28,7 @@
##-- dependencies:
##--
##-- references:
##--
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
......@@ -45,7 +45,7 @@
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
......@@ -67,7 +67,8 @@ NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
##=============================================================================
##-- FRONT PANEL TTLs
......
......@@ -67,7 +67,8 @@ NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
##=============================================================================
##-- FRONT PANEL TTLs
......
......@@ -67,7 +67,8 @@ NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
##=============================================================================
##-- FRONT PANEL TTLs
......
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