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Conv TTL Blocking - Gateware
Commit 74c8b19b authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Doc: Updated hdl guide with additional note on inverter channel output LEDs.… 

Doc: Updated hdl guide with additional note on inverter channel output LEDs. fixed a typo on conv-regs.
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doc/hdlg/conv-regs.tex
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......@@ -59,7 +59,7 @@ Base address: 0x000
0x9c& 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0xa0& 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0xa4& Note(2) & LSR & Line Status Register\\
0xa8& 0x00000000 & OSWR & Other switch resistor\\
0xa8& 0x00000000 & OSWR & Other switch register\\
0xac& Unique ID & UIDLR & Thermometer ID Low register\\
0xb0& Unique ID & UIDHR & Thermometer ID High register\\
0xb4& 0x00000000 & TEMPR & Board Temperature Register\\
......
doc/hdlg/fig/block-diagram.svg
View file @ 74c8b19b
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doc/hdlg/hdlg-conv-ttl-blo.tex
View file @ 74c8b19b
......@@ -307,7 +307,7 @@ when it is OFF.
%==============================================================================
\subsection{Pulse LED output logic}
\label{sec:pulse-led}
\textit {Note that this very same logic has been moved inside conv-common-gw submodule for release 4 of the gateware.}\\
\textit {Note that this very same logic has been replicated inside conv-common-gw submodule for inverted channels. This functionality is available on release 4 of the gateware for PCBs v3 onwards.}\\
Since in the CONV-TTL-BLO schematics the pulse LEDs are driven from inverting
Schmitt triggers to ground, the active-high pulse LED output from \textit{conv\_common\_gw}
......@@ -387,34 +387,34 @@ $reg. index = \frac{addr}{4} + 1$
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x200
\vspace*{11pt}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%\subsection{Thermometer module}
%\label{app:memmap-thermo}
%
%\indent Base address: 0x200
%
%\vspace*{11pt}
%
%\centerline
%{
%\rowcolors{2}{white}{gray!25}
%\begin{tabular}{l l l p{.5\textwidth}}
%\hline
%\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
%\hline
%0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
%0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
%\hline
%\end{tabular}
%}
%
%\vspace*{11pt}
%
%For details on the bits of the thermometer module access registers, see the
%OneWire Master module's documentation~\cite{onewire-core}.
%
%Note that the OWCDR should be set accordingly for proper functioning of the
%one-wire timings. The value for the current version of the gateware is
%\verb-OWCDR = 0x00130063-.
%==============================================================================
\end{appendices}
......
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