Pulsetest firmware: changed conv_regs component and made necessary

changes at top-level Signed-off-by: Theodor Stana <t.stana@cern.ch>

Pulsetest firmware: changed conv_regs component and made necessary
changes at top-level Signed-off-by: Theodor Stana <t.stana@cern.ch>
78769118 · Theodor-Adrian Stana · eb348ac7 · 78769118 · 78769118 · 78769118
Commit 78769118 authored Dec 08, 2013 by Theodor-Adrian Stana
5 changed files
--- a/modules/pulsetest/conv_regs.vhd
+++ b/modules/pulsetest/conv_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : conv_regs.vhd
 -- Author         : auto-generated by wbgen2 from conv_regs.wb
-- Created        : Fri Aug  2 16:02:13 2013
+-- Created        : Sat Dec  7 14:11:02 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
@@ -27,26 +27,31 @@ entity conv_regs is
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
-    conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+    reg_id_bits_i                            : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
+-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
-    conv_regs_sr_fwvers_i                    : in     std_logic_vector(15 downto 0);
+    reg_sr_fwvers_i                          : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
+-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
-    conv_regs_sr_switches_i                  : in     std_logic_vector(7 downto 0);
+    reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
+-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
-    conv_regs_sr_rtm_i                       : in     std_logic_vector(5 downto 0);
+    reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
-    conv_regs_cr_rst_unlock_o                : out    std_logic;
+    reg_sr_i2c_wdto_o                        : out    std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
+    reg_sr_i2c_wdto_i                        : in     std_logic;
-    conv_regs_cr_rst_o                       : out    std_logic
+    reg_sr_i2c_wdto_load_o                   : out    std_logic;
+-- Ports for BIT field: 'Reset unlock bit' in reg: 'Control Register'
+    reg_cr_rst_unlock_o                      : out    std_logic;
+    reg_cr_rst_unlock_i                      : in     std_logic;
+    reg_cr_rst_unlock_load_o                 : out    std_logic;
+-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
+    reg_cr_rst_o                             : out    std_logic;
+    reg_cr_rst_i                             : in     std_logic;
+    reg_cr_rst_load_o                        : out    std_logic
  );
 end conv_regs;
 architecture syn of conv_regs is
-signal conv_regs_id_bits_int                    : std_logic_vector(31 downto 0);
-signal conv_regs_cr_rst_unlock_int              : std_logic      ;
-signal conv_regs_cr_rst_int                     : std_logic      ;
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -74,46 +79,59 @@ begin
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
-      conv_regs_id_bits_int <= x"424c4f32";
+      reg_sr_i2c_wdto_load_o <= '0';
-      conv_regs_cr_rst_unlock_int <= '0';
+      reg_cr_rst_unlock_load_o <= '0';
-      conv_regs_cr_rst_int <= '0';
+      reg_cr_rst_load_o <= '0';
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
+          reg_sr_i2c_wdto_load_o <= '0';
+          reg_cr_rst_unlock_load_o <= '0';
+          reg_cr_rst_load_o <= '0';
          ack_in_progress <= '0';
        else
+          reg_sr_i2c_wdto_load_o <= '0';
+          reg_cr_rst_unlock_load_o <= '0';
+          reg_cr_rst_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(1 downto 0) is
          when "00" => 
            if (wb_we_i = '1') then
-              conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
            end if;
-            rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
+            rddata_reg(31 downto 0) <= reg_id_bits_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01" => 
            if (wb_we_i = '1') then
+              reg_sr_i2c_wdto_load_o <= '1';
            end if;
-            rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
+            rddata_reg(7 downto 0) <= reg_sr_fwvers_i;
-            rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
+            rddata_reg(15 downto 8) <= reg_sr_switches_i;
-            rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
+            rddata_reg(21 downto 16) <= reg_sr_rtm_i;
+            rddata_reg(22) <= reg_sr_i2c_wdto_i;
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10" => 
            if (wb_we_i = '1') then
-              conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
+              reg_cr_rst_unlock_load_o <= '1';
-              conv_regs_cr_rst_int <= wrdata_reg(31);
+              reg_cr_rst_load_o <= '1';
            end if;
-            rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
+            rddata_reg(0) <= reg_cr_rst_unlock_i;
-            rddata_reg(31) <= conv_regs_cr_rst_int;
+            rddata_reg(1) <= reg_cr_rst_i;
-            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
@@ -143,6 +161,7 @@ begin
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
@@ -159,14 +178,15 @@ begin
 -- Drive the data output bus
  wb_dat_o <= rddata_reg;
 -- bits
-  conv_regs_id_bits_o <= conv_regs_id_bits_int;
 -- fwvers
 -- switches
 -- RTM detection
+-- I2C Watchdog Timeout
+  reg_sr_i2c_wdto_o <= wrdata_reg(22);
 -- Reset unlock bit
-  conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
+  reg_cr_rst_unlock_o <= wrdata_reg(0);
 -- Reset bit
-  conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
+  reg_cr_rst_o <= wrdata_reg(1);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/modules/pulsetest/conv_regs.wb
+++ b/modules/pulsetest/conv_regs.wb
+peripheral {
+  name = "Converter board registers";
+  hdl_entity = "conv_regs";
+  prefix = "reg";
+  reg {
+    name = "Board ID Register";
+    description = "Bits of ID register, defaulting to ASCII string TBLO";
+    prefix = "id";
+    field {
+      name = "bits";
+      prefix = "bits";
+      type = SLV;
+      size = 32;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+  reg {
+    name = "Status Register";
+    description = "Contains various board status information";
+    prefix = "sr";
+    field {
+      name = "fwvers";
+      prefix = "fwvers";
+      type = SLV;
+      size = 8;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "switches";
+      prefix = "switches";
+      type = SLV;
+      size = 8;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "RTM detection";
+      prefix = "rtm";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name       = "I2C Watchdog Timeout";
+      prefix     = "i2c_wdto";
+      type       = BIT;
+      size       = 1;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load       = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "Control Register";
+    description = "Contains bits that control operation of the converter modules";
+    prefix = "cr";
+--    field {
+--      name = "blocking chan 1 enable";
+--      prefix = "bch1_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 2 enable";
+--      prefix = "bch2_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 3 enable";
+--      prefix = "bch3_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 4 enable";
+--      prefix = "bch4_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 5 enable";
+--      prefix = "bch5_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 6 enable";
+--      prefix = "bch6_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+    field {
+      name = "Reset unlock bit";
+      prefix = "rst_unlock";
+      description = "1 - Reset bit unlocked\
+                     0 - Reset bit locked";
+      type = BIT;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load = LOAD_EXT;
+    };
+    field {
+      name = "Reset bit";
+      prefix = "rst";
+      description = "1 - initiate logic reset\
+                     0 - no reset";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+};
--- a/syn/pulsetest/Makefile
+++ b/syn/pulsetest/Makefile
@@ -43,7 +43,6 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../modules/pulsetest/pgen_ctrl_regs.vhd \
 ../../modules/pulsetest/pulse_gen_gp.vhd \
 ../../modules/ctb_pulse_gen.vhd \
-../../modules/glitch_filt.vhd \
 ../../modules/reset_gen.vhd \
 ../../modules/rtm_detector.vhd \
 ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
@@ -61,6 +60,9 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
 ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
 ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
 ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
 ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
 ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
@@ -136,6 +138,7 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
@@ -145,15 +148,12 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
 ../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
 ../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
-../../modules/vbcp_wb/i2c_slave_pkg.vhd \
-../../modules/vbcp_wb/i2c_slave.vhd \
-../../modules/vbcp_wb/vbcp_wb.vhd \
-../../modules/xil_multiboot/spi_master.vhd \
-../../modules/xil_multiboot/multiboot_fsm.vhd \
-../../modules/xil_multiboot/multiboot_regs.vhd \
-../../modules/xil_multiboot/xil_multiboot.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
 ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
 ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \

--- a/syn/pulsetest/pulsetest.xise
+++ b/syn/pulsetest/pulsetest.xise
@@ -56,7 +56,7 @@
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -243,7 +243,7 @@
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -313,7 +313,7 @@
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
@@ -361,337 +361,337 @@
    <file xil_pn:name="../../modules/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
-    <file xil_pn:name="../../modules/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
-    <file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
-    <file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
    </file>
-    <file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
    </file>
-    <file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
    </file>
-    <file xil_pn:name="../../modules/vbcp_wb/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
    </file>
-    <file xil_pn:name="../../modules/vbcp_wb/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
    </file>
-    <file xil_pn:name="../../modules/vbcp_wb/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
    </file>
-    <file xil_pn:name="../../modules/xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
    </file>
-    <file xil_pn:name="../../modules/xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
    </file>
-    <file xil_pn:name="../../modules/xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
    </file>
-    <file xil_pn:name="../../modules/xil_multiboot/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
    </file>
  </files>

--- a/top/pulsetest/pulsetest.vhd
+++ b/top/pulsetest/pulsetest.vhd
--------------------------------------------------------------------------------
+--==============================================================================
 -- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
+-- Long-term pulse test for CONV-TTL-* boards
-- http://www.ohwr.org/projects/conv-ttl-blo
+--==============================================================================
--------------------------------------------------------------------------------
 --
-- unit name: pulsetest.vhd
+-- author: Theodor Stana (t.stana@cern.ch)
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
 --
 -- version: 1.0
 --
-- description: Top entity of CONV-TTL-BLO
+-- description:
+--    This is the top-level file for the long-term pulse repetition test for TTL
+--    pulse converter boards. All the top-level logic generation and component
+--    instantiation is done here.
+--
+--    A general-purpose pulse generator component (pulse_gen_gp) is used to
+--    generate the output pulses on the converter board output channels. One
+--    such pulse generator is instantiated per channel and external logic is
+--    used to adapt these pulses for TTL or TTL-BAR signals.
+--
+--    The characteristics of pulses generated by the generators can be
+--    controlled by means of registers accessible over the I2C bus on the
+--    VME backplanes. To access the registers, the protocol defined together
+--    with ELMA [2] is used and the wb_i2c_bridge component handles translating
+--    this protocol into the Wishbone protocol, which is then used to access
+--    the registers controlling the pulse generators.
+--
+--    An example test script can be used to run the long-term pulse repetition
+--    test. The test script can be found in the software/pulsetest/ folder in
+--    the conv-ttl-blo repository [3]. More information on what the script does
+--    can be found on the CONV-TTL-BLO Testing webpage [4].
 --
 -- dependencies:
+--    general-cores repository [1]
 --
 -- references:
--   [1] ELMA, Access to board data using SNMP and I2C
+--    [1] Platform-independent core collection webpage on OHWR,
--       http://www.ohwr.org/documents/227
+--        http://www.ohwr.org/projects/general-cores/repository
+--    [2] ELMA, Access to board data using SNMP and I2C
+--        http://www.ohwr.org/documents/227
+--    [3] CONV-TTL-BLO project repository on OHWR,
+--        http://www.ohwr.org/projects/conv-ttl-blo/repository
+--    [4] CONV-TTL-BLO Test page on OHWR,
+--        http://www.ohwr.org/projects/conv-ttl-blo/wiki/Testing
 --
--------------------------------------------------------------------------------
+--==============================================================================
 -- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
+--==============================================================================
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
 -- Free Software Foundation; either version 2.1 of the License, or (at your
@@ -30,7 +54,12 @@
 -- See the GNU Lesser General Public License for more details. You should have
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
+--==============================================================================
+-- last changes:
+--   26-11-2013   Theodor Stana       Changed file header
+--==============================================================================
+-- TODO: -
+--==============================================================================
 library ieee;
 library unisim;
@@ -151,8 +180,21 @@ architecture behav of pulsetest is
  --============================================================================
  -- Constant declarations
  --============================================================================
+  -- Board ID - ASCII string "TBLO"
+  constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
  -- Firmware version
-  constant c_fwvers          : std_logic_vector(15 downto 0) := x"9999";
+  --    - format: M.m
+  --    - M: major version hex number (e.g.  1)
+  --    - m: minor version hex number (e.g. 13)
+  --    - example: first major release      v1.0  c_fwvers = x"10";
+  --               next minor release       v1.1  c_fwvers = x"11";
+  --               13 minor releases later  v1.12 c_fwvers = x"1e";
+  --               next major release       v2.0  c_fwvers = x"20";
+  -- Test firmware gets numbered from v9.9 downward
+  -- The pulse test firmware is v9.9
+  constant c_fwvers          : std_logic_vector(7 downto 0) := x"99";
  -- Number of Wishbone masters and slaves, for wb_crossbar
  constant c_nr_masters      : natural :=  1;
@@ -213,7 +255,7 @@ architecture behav of pulsetest is
    generic
    (
      -- Reset time in number of clk_i cycles
-      g_reset_time : positive := 5_000_000
+      g_reset_time : positive := 2_000_000
    );
    port
    (
@@ -223,27 +265,6 @@ architecture behav of pulsetest is
    );
  end component reset_gen;
-  -- Xilinx MultiBoot component
-  -- (use: remote reprogramming of the FPGA)
-  component wb_xil_multiboot is
-    port
-    (
-      -- Clock and reset input ports
-      clk_i   : in  std_logic;
-      rst_n_i : in  std_logic;
-      -- Wishbone ports
-      wbs_i   : in  t_wishbone_slave_in;
-      wbs_o   : out t_wishbone_slave_out;
-      -- SPI ports
-      spi_cs_n_o : out std_logic;
-      spi_sclk_o : out std_logic;
-      spi_mosi_o : out std_logic;
-      spi_miso_i : in  std_logic
-    );
-  end component wb_xil_multiboot;
  -- Converter registers
  -- (use: ID, firmware version)
  component conv_regs is
@@ -259,18 +280,26 @@ architecture behav of pulsetest is
      wb_we_i                                  : in     std_logic;
      wb_ack_o                                 : out    std_logic;
      wb_stall_o                               : out    std_logic;
-    -- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+    -- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
-      conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+      reg_id_bits_i                            : in     std_logic_vector(31 downto 0);
-    -- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
+    -- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
-      conv_regs_sr_fwvers_i                    : in     std_logic_vector(15 downto 0);
+      reg_sr_fwvers_i                          : in     std_logic_vector(7 downto 0);
-    -- Port for std_logic_vector field: 'switches' in reg: 'Status register'
+    -- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
-      conv_regs_sr_switches_i                  : in     std_logic_vector(7 downto 0);
+      reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-    -- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
+    -- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
-      conv_regs_sr_rtm_i                       : in     std_logic_vector(5 downto 0);
+      reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-    -- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+    -- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
-      conv_regs_cr_rst_unlock_o                : out    std_logic;
+      reg_sr_i2c_wdto_o                        : out    std_logic;
-    -- Port for BIT field: 'Reset bit' in reg: 'Control register'
+      reg_sr_i2c_wdto_i                        : in     std_logic;
-      conv_regs_cr_rst_o                       : out    std_logic
+      reg_sr_i2c_wdto_load_o                   : out    std_logic;
+    -- Port for BIT field: 'Reset unlock bit' in reg: 'Control Register'
+      reg_cr_rst_unlock_o                      : out    std_logic;
+      reg_cr_rst_unlock_i                      : in     std_logic;
+      reg_cr_rst_unlock_load_o                 : out    std_logic;
+    -- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
+      reg_cr_rst_o                             : out    std_logic;
+      reg_cr_rst_i                             : in     std_logic;
+      reg_cr_rst_load_o                        : out    std_logic
    );
  end component conv_regs;
@@ -389,11 +418,54 @@ architecture behav of pulsetest is
    );
  end component pulse_cnt_regs;
+  -- MultiBoot component
+  -- use: remotely reprogram the FPGA
+  component wb_xil_multiboot is
+    port
+    (
+      -- Clock and reset input ports
+      clk_i   : in  std_logic;
+      rst_n_i : in  std_logic;
+      -- Wishbone ports
+      wbs_i   : in  t_wishbone_slave_in;
+      wbs_o   : out t_wishbone_slave_out;
+      -- SPI ports
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
+    );
+  end component wb_xil_multiboot;
+  -- RTM detector component
+  -- (use: detect the presence of an RTM/P module)
+  component rtm_detector is
+    port
+    (
+      rtmm_i    : in std_logic_vector(2 downto 0);
+      rtmp_i    : in std_logic_vector(2 downto 0);
+      rtmm_ok_o : out std_logic;
+      rtmp_ok_o : out std_logic
+    );
+  end component rtm_detector;
  --============================================================================
  -- Signal declarations
  --============================================================================
  -- Reset signals
  signal rst_n             : std_logic;
+  signal rst_unlock        : std_logic;
+  signal rst_unlock_bit    : std_logic;
+  signal rst_unlock_bit_ld : std_logic;
+  signal rst_bit           : std_logic;
+  signal rst_bit_ld        : std_logic;
+  signal rst_fr_reg        : std_logic;
+  -- RTM detection signals
+  signal rtmm, rtmp        : std_logic_vector(2 downto 0);
+  signal rtmm_ok, rtmp_ok  : std_logic;
  -- Wishbone crossbar signals
  signal xbar_slave_in     : t_wishbone_slave_in_array  (c_nr_masters - 1 downto 0);
@@ -401,19 +473,26 @@ architecture behav of pulsetest is
  signal xbar_master_in    : t_wishbone_master_in_array (c_nr_slaves  - 1 downto 0);
  signal xbar_master_out   : t_wishbone_master_out_array(c_nr_slaves  - 1 downto 0);
+  -- Signals to/from converter system registers component
+  signal rtm_lines         : std_logic_vector(5 downto 0);
+  signal switches_n        : std_logic_vector(7 downto 0);
+  signal wdto_bit          : std_logic;
+  signal wdto_bit_rst      : std_logic;
+  signal wdto_bit_rst_ld   : std_logic;
  -- Signal for controlling the bicolor LED matrix
  signal bicolor_led_state : std_logic_vector(23 downto 0);
  -- VBCP bridge signals
  signal i2c_tip           : std_logic;
-  signal i2c_err           : std_logic;
+  signal i2c_err_p         : std_logic;
-  signal i2c_err_led       : std_logic;
+  signal i2c_wdto_p        : std_logic;
-  signal i2c_up            : std_logic;
  signal i2c_addr          : std_logic_vector(6 downto 0);
  signal led_i2c           : std_logic;
  signal led_i2c_clkdiv    : unsigned(18 downto 0);
  signal led_i2c_cnt       : unsigned( 2 downto 0);
-  signal blink_state       : std_logic;
+  signal led_i2c_blink     : std_logic;
+  signal led_i2c_err       : std_logic;
  -- Pulse enable signals
  signal oe, ttl_oe        : std_logic;
@@ -427,6 +506,7 @@ architecture behav of pulsetest is
  signal trig_synced       : std_logic_vector(g_nr_ttl_chan downto 1);
  signal trig_synced_edge  : std_logic_vector(g_nr_ttl_chan downto 1);
  signal pulse, pulse_d0   : std_logic_vector(g_nr_ttl_chan downto 1);
+  signal pulse_r_edge_p    : std_logic_vector(g_nr_ttl_chan downto 1);
  -- Pulse LED signals
  signal pulse_leds        : std_logic_vector(g_nr_ttl_chan downto 1);
@@ -439,6 +519,9 @@ architecture behav of pulsetest is
  signal pwidth_reg        : t_pgen_ctrl_reg;
  signal freq_reg          : t_pgen_ctrl_reg;
+--==============================================================================
+--  architecture begin
+--==============================================================================
 begin
  --============================================================================
@@ -454,7 +537,7 @@ begin
    port map
    (
      clk_i   => clk20_vcxo_i,
-      rst_i   => '0',
+      rst_i   => rst_fr_reg,
      rst_n_o => rst_n
    );
@@ -475,17 +558,18 @@ begin
      rst_n_i    => rst_n,
      -- I2C lines
-      sda_en_o   => sda_oe_o,
-      sda_i      => sda_i,
-      sda_o      => sda_o,
-      scl_en_o   => scl_oe_o,
      scl_i      => scl_i,
      scl_o      => scl_o,
+      scl_en_o   => scl_oe_o,
+      sda_i      => sda_i,
+      sda_o      => sda_o,
+      sda_en_o   => sda_oe_o,
      -- I2C address and status
      i2c_addr_i => i2c_addr,
      tip_o      => i2c_tip,
-      err_o      => i2c_err,
+      err_p_o    => i2c_err_p,
+      wdto_p_o   => i2c_wdto_p,
      -- Wishbone master signals
      wbm_stb_o  => xbar_slave_in(0).stb,
@@ -509,16 +593,16 @@ begin
    if rising_edge(clk20_vcxo_i) then
      if (rst_n = '0') then
        led_i2c_clkdiv <= (others => '0');
-        led_i2c_cnt      <= (others => '0');
+        led_i2c_cnt    <= (others => '0');
-        led_i2c          <= '0';
+        led_i2c        <= '0';
-        blink_state      <= '0';
+        led_i2c_blink  <= '0';
      else
-        case blink_state is
+        case led_i2c_blink is
          when '0' =>
            led_i2c <= '0';
            if (i2c_tip = '1') then
-              blink_state <= '1';
+              led_i2c_blink <= '1';
            end if;
          when '1' =>
@@ -529,12 +613,12 @@ begin
              led_i2c        <= not led_i2c;
              if (led_i2c_cnt = 7) then
                led_i2c_cnt <= (others => '0');
-                blink_state <= '0';
+                led_i2c_blink <= '0';
              end if;
            end if;
          when others =>
-            blink_state <= '0';
+            led_i2c_blink <= '0';
        end case;
      end if;
@@ -548,13 +632,27 @@ begin
  begin
  if rising_edge(clk20_vcxo_i) then
    if (rst_n = '0') then
-      i2c_err_led <= '0';
+      led_i2c_err <= '0';
-    elsif (i2c_err = '1') then
+    elsif (i2c_err_p = '1') then
-      i2c_err_led <= '1';
+      led_i2c_err <= '1';
    end if;
  end if;
  end process p_i2c_err_led;
+  -- Register for the WDTO bit in the SR, cleared by writing a '1'
+  p_sr_wdto_bit : process (clk20_vcxo_i)
+  begin
+    if rising_edge(clk20_vcxo_i) then
+      if (rst_n = '0') then
+        wdto_bit <= '0';
+      elsif (i2c_wdto_p = '1') then
+        wdto_bit <= '1';
+      elsif (wdto_bit_rst_ld = '1') and (wdto_bit_rst = '1') then
+        wdto_bit <= '0';
+      end if;
+    end if;
+  end process p_sr_wdto_bit;
  --============================================================================
  -- Instantiation and connection of the main Wishbone crossbar
  --============================================================================
@@ -580,28 +678,72 @@ begin
    master_o  => xbar_master_out
  );
+  --============================================================================
+  -- Converter board registers
+  --============================================================================
+  -- Set SWITCH and RTM fields
+  switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
+  rtm_lines  <= rtmp & rtmm;
+  -- Then, instantiate the component
  cmp_conv_regs : conv_regs
    port map (
-      rst_n_i                   => rst_n,
+      rst_n_i                  => rst_n,
-      clk_sys_i                 => clk20_vcxo_i,
+      clk_sys_i                => clk20_vcxo_i,
-      wb_adr_i                  => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
+      wb_adr_i                 => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
-      wb_dat_i                  => xbar_master_out(c_slv_conv_regs).dat,
+      wb_dat_i                 => xbar_master_out(c_slv_conv_regs).dat,
-      wb_dat_o                  => xbar_master_in (c_slv_conv_regs).dat,
+      wb_dat_o                 => xbar_master_in (c_slv_conv_regs).dat,
-      wb_cyc_i                  => xbar_master_out(c_slv_conv_regs).cyc,
+      wb_cyc_i                 => xbar_master_out(c_slv_conv_regs).cyc,
-      wb_sel_i                  => xbar_master_out(c_slv_conv_regs).sel,
+      wb_sel_i                 => xbar_master_out(c_slv_conv_regs).sel,
-      wb_stb_i                  => xbar_master_out(c_slv_conv_regs).stb,
+      wb_stb_i                 => xbar_master_out(c_slv_conv_regs).stb,
-      wb_we_i                   => xbar_master_out(c_slv_conv_regs).we,
+      wb_we_i                  => xbar_master_out(c_slv_conv_regs).we,
-      wb_ack_o                  => xbar_master_in (c_slv_conv_regs).ack,
+      wb_ack_o                 => xbar_master_in (c_slv_conv_regs).ack,
-      wb_stall_o                => xbar_master_in (c_slv_conv_regs).stall,
+      wb_stall_o               => xbar_master_in (c_slv_conv_regs).stall,
-      conv_regs_id_bits_o       => open,
+      reg_id_bits_i            => c_board_id,
-      conv_regs_sr_fwvers_i     => c_fwvers,
+      reg_sr_fwvers_i          => c_fwvers,
-      conv_regs_sr_switches_i   => (others => '0'),
+      reg_sr_switches_i        => switches_n,
-      conv_regs_sr_rtm_i        => (others => '0'),
+      reg_sr_rtm_i             => rtm_lines,
-      conv_regs_cr_rst_unlock_o => open,
+      reg_sr_i2c_wdto_o        => wdto_bit_rst,
-      conv_regs_cr_rst_o        => open
+      reg_sr_i2c_wdto_i        => wdto_bit,
+      reg_sr_i2c_wdto_load_o   => wdto_bit_rst_ld,
+      reg_cr_rst_unlock_o      => rst_unlock_bit,
+      reg_cr_rst_unlock_i      => rst_unlock,
+      reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
+      reg_cr_rst_o             => rst_bit,
+      reg_cr_rst_i             => rst_fr_reg,
+      reg_cr_rst_load_o        => rst_bit_ld
    );
+  -- Implement the RST_UNLOCK bit
+  p_rst_unlock : process (clk20_vcxo_i)
+  begin
+    if rising_edge(clk20_vcxo_i) then
+      if (rst_n = '0') then
+        rst_unlock <= '0';
+      elsif (rst_unlock_bit_ld = '1') then
+        if (rst_unlock_bit = '1') then
+          rst_unlock <= '1';
+        else
+          rst_unlock <= '0';
+        end if;
+      end if;
+    end if;
+  end process p_rst_unlock;
+  -- And implement the reset bit register
+  p_rst_fr_reg : process (clk20_vcxo_i)
+  begin
+    if rising_edge(clk20_vcxo_i) then
+      if (rst_n = '0') then
+        rst_fr_reg <= '0';
+      elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
+        rst_fr_reg <= '1';
+      end if;
+    end if;
+  end process p_rst_fr_reg;
  --============================================================================
  -- Pulse generation control registers instantiation
  --============================================================================
@@ -683,7 +825,9 @@ begin
  -- And now the OR gate at the inputs of the pulse generator blocks
  trig_a     <= trig_ttl_a or trig_blo_a;
+  -----------------------------------------------------------------------------
  -- Generate logic for each channel
+  -----------------------------------------------------------------------------
  gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
    -- First, resync the trigger signal into clk20_vcxo_i domain
@@ -715,9 +859,11 @@ begin
    begin
      if rising_edge(clk20_vcxo_i) then
        if (rst_n = '0') then
-          pulse_d0(i) <= '0';
+          pulse_d0(i)       <= '0';
+          pulse_r_edge_p(i) <= '0';
        else
-          pulse_d0(i) <= pulse(i);
+          pulse_d0(i)       <= pulse(i);
+          pulse_r_edge_p(i) <= pulse(i) and (not pulse_d0(i));
        end if;
      end if;
    end process p_delay_pulse;
@@ -730,7 +876,7 @@ begin
          cnt_in(i)  <= (others => '0');
          cnt_out(i) <= (others => '0');
        else
-          if (pulse(i) = '1') and (pulse_d0(i) = '0') then
+          if (pulse_r_edge_p(i) = '1') then
            cnt_out(i) <= cnt_out(i) + 1;
          end if;
@@ -752,7 +898,7 @@ begin
        else
          case pulse_leds(i) is
            when '0' =>
-              if (trig_synced_edge(i) = '1') then
+              if (pulse_r_edge_p(i) = '1') then
                pulse_leds(i) <= '1';
              end if;
            when '1' =>
@@ -772,6 +918,7 @@ begin
    pulse_rear_led_n_o(i)  <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
  end generate gen_chan_logic;
+  -----------------------------------------------------------------------------
  -- Pulse outputs assignment
  fpga_out_ttl_o  <= pulse when (ttl_switch_n_i = '0') else
@@ -864,7 +1011,7 @@ begin
  -- I2C
  bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
-                                     c_LED_RED   when (i2c_err_led = '1') else
+                                     c_LED_RED   when (led_i2c_err = '1') else
                                     c_LED_OFF;
  -- State of TTL/TTL_N switch
@@ -872,7 +1019,8 @@ begin
                                     c_LED_OFF;
  -- System error
-  bicolor_led_state(17 downto 16) <= c_LED_OFF;
+  bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
+                                     c_LED_OFF;
  -- System power
  bicolor_led_state(19 downto 18) <= c_LED_GREEN;
@@ -909,6 +1057,21 @@ begin
      line_oen_o(1)   => led_ctrl1_oen_o
    );
+  --============================================================================
+  -- RTM detection logic
+  --============================================================================
+  rtmm <= not fpga_rtmm_n_i;
+  rtmp <= not fpga_rtmp_n_i;
+  cmp_rtm_detector : rtm_detector
+    port map
+    (
+      rtmm_i    => rtmm,
+      rtmp_i    => rtmp,
+      rtmm_ok_o => rtmm_ok,
+      rtmp_ok_o => rtmp_ok
+    );
  --============================================================================
  -- Drive unused outputs with safe values
  --============================================================================
@@ -930,3 +1093,6 @@ begin
  fpga_sfp_tx_disable_o  <= 'Z';
 end behav;
+--==============================================================================
+--  architecture end
+--==============================================================================