Pulsetest firmware: changed conv_regs component and made necessary

changes at top-level Signed-off-by: Theodor Stana <t.stana@cern.ch>

Pulsetest firmware: changed conv_regs component and made necessary
changes at top-level Signed-off-by: Theodor Stana <t.stana@cern.ch>
78769118 · Theodor-Adrian Stana · eb348ac7 · 78769118 · 78769118 · 78769118
Commit 78769118 authored Dec 08, 2013 by Theodor-Adrian Stana
5 changed files
--- a/modules/pulsetest/conv_regs.vhd
+++ b/modules/pulsetest/conv_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : conv_regs.vhd
 -- Author         : auto-generated by wbgen2 from conv_regs.wb
-- Created        : Fri Aug  2 16:02:13 2013
+-- Created        : Sat Dec  7 14:11:02 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
@@ -27,26 +27,31 @@ entity conv_regs is
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
-    conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+    reg_id_bits_i                            : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
+-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
-    conv_regs_sr_fwvers_i                    : in     std_logic_vector(15 downto 0);
+    reg_sr_fwvers_i                          : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
+-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
-    conv_regs_sr_switches_i                  : in     std_logic_vector(7 downto 0);
+    reg_sr_switches_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
+-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
-    conv_regs_sr_rtm_i                       : in     std_logic_vector(5 downto 0);
+    reg_sr_rtm_i                             : in     std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
-    conv_regs_cr_rst_unlock_o                : out    std_logic;
+    reg_sr_i2c_wdto_o                        : out    std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
+    reg_sr_i2c_wdto_i                        : in     std_logic;
-    conv_regs_cr_rst_o                       : out    std_logic
+    reg_sr_i2c_wdto_load_o                   : out    std_logic;
+-- Ports for BIT field: 'Reset unlock bit' in reg: 'Control Register'
+    reg_cr_rst_unlock_o                      : out    std_logic;
+    reg_cr_rst_unlock_i                      : in     std_logic;
+    reg_cr_rst_unlock_load_o                 : out    std_logic;
+-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
+    reg_cr_rst_o                             : out    std_logic;
+    reg_cr_rst_i                             : in     std_logic;
+    reg_cr_rst_load_o                        : out    std_logic
  );
 end conv_regs;
 architecture syn of conv_regs is
-signal conv_regs_id_bits_int                    : std_logic_vector(31 downto 0);
-signal conv_regs_cr_rst_unlock_int              : std_logic      ;
-signal conv_regs_cr_rst_int                     : std_logic      ;
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -74,46 +79,59 @@ begin
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
-      conv_regs_id_bits_int <= x"424c4f32";
+      reg_sr_i2c_wdto_load_o <= '0';
-      conv_regs_cr_rst_unlock_int <= '0';
+      reg_cr_rst_unlock_load_o <= '0';
-      conv_regs_cr_rst_int <= '0';
+      reg_cr_rst_load_o <= '0';
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
+          reg_sr_i2c_wdto_load_o <= '0';
+          reg_cr_rst_unlock_load_o <= '0';
+          reg_cr_rst_load_o <= '0';
          ack_in_progress <= '0';
        else
+          reg_sr_i2c_wdto_load_o <= '0';
+          reg_cr_rst_unlock_load_o <= '0';
+          reg_cr_rst_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(1 downto 0) is
          when "00" => 
            if (wb_we_i = '1') then
-              conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
            end if;
-            rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
+            rddata_reg(31 downto 0) <= reg_id_bits_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01" => 
            if (wb_we_i = '1') then
+              reg_sr_i2c_wdto_load_o <= '1';
            end if;
-            rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
+            rddata_reg(7 downto 0) <= reg_sr_fwvers_i;
-            rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
+            rddata_reg(15 downto 8) <= reg_sr_switches_i;
-            rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
+            rddata_reg(21 downto 16) <= reg_sr_rtm_i;
+            rddata_reg(22) <= reg_sr_i2c_wdto_i;
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10" => 
            if (wb_we_i = '1') then
-              conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
+              reg_cr_rst_unlock_load_o <= '1';
-              conv_regs_cr_rst_int <= wrdata_reg(31);
+              reg_cr_rst_load_o <= '1';
            end if;
-            rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
+            rddata_reg(0) <= reg_cr_rst_unlock_i;
-            rddata_reg(31) <= conv_regs_cr_rst_int;
+            rddata_reg(1) <= reg_cr_rst_i;
-            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
@@ -143,6 +161,7 @@ begin
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
+            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
@@ -159,14 +178,15 @@ begin
 -- Drive the data output bus
  wb_dat_o <= rddata_reg;
 -- bits
-  conv_regs_id_bits_o <= conv_regs_id_bits_int;
 -- fwvers
 -- switches
 -- RTM detection
+-- I2C Watchdog Timeout
+  reg_sr_i2c_wdto_o <= wrdata_reg(22);
 -- Reset unlock bit
-  conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
+  reg_cr_rst_unlock_o <= wrdata_reg(0);
 -- Reset bit
-  conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
+  reg_cr_rst_o <= wrdata_reg(1);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/modules/pulsetest/conv_regs.wb
+++ b/modules/pulsetest/conv_regs.wb
+peripheral {
+  name = "Converter board registers";
+  hdl_entity = "conv_regs";
+  prefix = "reg";
+  reg {
+    name = "Board ID Register";
+    description = "Bits of ID register, defaulting to ASCII string TBLO";
+    prefix = "id";
+    field {
+      name = "bits";
+      prefix = "bits";
+      type = SLV;
+      size = 32;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+  reg {
+    name = "Status Register";
+    description = "Contains various board status information";
+    prefix = "sr";
+    field {
+      name = "fwvers";
+      prefix = "fwvers";
+      type = SLV;
+      size = 8;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "switches";
+      prefix = "switches";
+      type = SLV;
+      size = 8;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "RTM detection";
+      prefix = "rtm";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name       = "I2C Watchdog Timeout";
+      prefix     = "i2c_wdto";
+      type       = BIT;
+      size       = 1;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load       = LOAD_EXT;
+    };
+  };
+  reg {
+    name = "Control Register";
+    description = "Contains bits that control operation of the converter modules";
+    prefix = "cr";
+--    field {
+--      name = "blocking chan 1 enable";
+--      prefix = "bch1_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 2 enable";
+--      prefix = "bch2_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 3 enable";
+--      prefix = "bch3_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 4 enable";
+--      prefix = "bch4_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 5 enable";
+--      prefix = "bch5_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+--    field {
+--      name = "blocking chan 6 enable";
+--      prefix = "bch6_en";
+--      type = BIT;
+--      access_bus = READ_WRITE;
+--      access_dev = READ_ONLY;
+--    };
+    field {
+      name = "Reset unlock bit";
+      prefix = "rst_unlock";
+      description = "1 - Reset bit unlocked\
+                     0 - Reset bit locked";
+      type = BIT;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load = LOAD_EXT;
+    };
+    field {
+      name = "Reset bit";
+      prefix = "rst";
+      description = "1 - initiate logic reset\
+                     0 - no reset";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+};
--- a/syn/pulsetest/Makefile
+++ b/syn/pulsetest/Makefile
@@ -43,7 +43,6 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../modules/pulsetest/pgen_ctrl_regs.vhd \
 ../../modules/pulsetest/pulse_gen_gp.vhd \
 ../../modules/ctb_pulse_gen.vhd \
-../../modules/glitch_filt.vhd \
 ../../modules/reset_gen.vhd \
 ../../modules/rtm_detector.vhd \
 ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
@@ -61,6 +60,9 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
 ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
 ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
 ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
 ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
 ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
@@ -136,6 +138,7 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
@@ -145,15 +148,12 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
 ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
 ../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
 ../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
-../../modules/vbcp_wb/i2c_slave_pkg.vhd \
-../../modules/vbcp_wb/i2c_slave.vhd \
-../../modules/vbcp_wb/vbcp_wb.vhd \
-../../modules/xil_multiboot/spi_master.vhd \
-../../modules/xil_multiboot/multiboot_fsm.vhd \
-../../modules/xil_multiboot/multiboot_regs.vhd \
-../../modules/xil_multiboot/xil_multiboot.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
 ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
 ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \

--- a/syn/pulsetest/pulsetest.xise
+++ b/syn/pulsetest/pulsetest.xise
--- a/top/pulsetest/pulsetest.vhd
+++ b/top/pulsetest/pulsetest.vhd