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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
7b173ccf
Commit
7b173ccf
authored
May 03, 2014
by
Theodor-Adrian Stana
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Add (for GPL reasons) and update file headers to various files
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
d6a206c7
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6 changed files
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148 additions
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4 deletions
+148
-4
conv_pulse_timetag.vhd
modules/Release/conv_pulse_timetag.vhd
+4
-2
conv_regs.wb
modules/Release/conv_regs.wb
+35
-0
conv_ring_buf.vhd
modules/Release/conv_ring_buf.vhd
+4
-2
conv_regs.wb
modules/pulsetest/conv_regs.wb
+35
-0
pgen_ctrl_regs.wb
modules/pulsetest/pgen_ctrl_regs.wb
+35
-0
pulse_cnt_regs.wb
modules/pulsetest/pulse_cnt_regs.wb
+35
-0
No files found.
modules/Release/conv_pulse_timetag.vhd
View file @
7b173ccf
...
@@ -10,10 +10,12 @@
...
@@ -10,10 +10,12 @@
-- version: 1.0
-- version: 1.0
--
--
-- description:
-- description:
-- This module contains the internal timetag counter, counting on an 8 ns
-- clock. When a pulse arrives on the input, it triggers the writing of a
-- timetag to a FIFO memory external to the module.
--
--
-- dependencies:
-- dependencies:
--
-- gencores_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
-- references:
--
--
--==============================================================================
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
-- GNU LESSER GENERAL PUBLIC LICENSE
...
...
modules/Release/conv_regs.wb
View file @
7b173ccf
--==============================================================================
-- CERN (BE-CO-HT)
-- Converter board registers wbgen2 description file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the converter board
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
peripheral {
name = "Converter board registers";
name = "Converter board registers";
hdl_entity = "conv_regs";
hdl_entity = "conv_regs";
...
...
modules/Release/conv_ring_buf.vhd
View file @
7b173ccf
...
@@ -10,10 +10,12 @@
...
@@ -10,10 +10,12 @@
-- version: 1.0
-- version: 1.0
--
--
-- description:
-- description:
-- Ring buffer memory with configurable (at synthesis time) data width and
-- size. Although created for the converter board design, it can be used in
-- any desing.
--
--
-- dependencies:
-- dependencies:
--
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
-- references:
--
--
--==============================================================================
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
-- GNU LESSER GENERAL PUBLIC LICENSE
...
...
modules/pulsetest/conv_regs.wb
View file @
7b173ccf
--==============================================================================
-- CERN (BE-CO-HT)
-- Converter board registers wbgen2 description file (pulsetest gateware)
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the converter board
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
peripheral {
name = "Converter board registers";
name = "Converter board registers";
hdl_entity = "conv_regs";
hdl_entity = "conv_regs";
...
...
modules/pulsetest/pgen_ctrl_regs.wb
View file @
7b173ccf
--==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator registers wbgen2 description file (pulsetest gateware)
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the pulse generator
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
peripheral {
name = "Pulse generation control registers";
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
...
...
modules/pulsetest/pulse_cnt_regs.wb
View file @
7b173ccf
--==============================================================================
-- CERN (BE-CO-HT)
-- Pulse counter registers wbgen2 description file (pulsetest gateware)
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the pulse counter
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
peripheral {
name = "Pulse counter registers";
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
description = "Registers containing the values for input and output generated pulses";
...
...
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