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Conv TTL Blocking - Gateware
Commit 8760fc48 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Merged with code-cleanup branch

parents b04ec5d6 acb22d4f
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 8760fc48
......@@ -7,8 +7,8 @@
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = LVTTL;
NET "RST" LOC = N20;
NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
......
hdl/IMAGES/image1/project/image1.gise deleted 100644 → 0
View file @ b04ec5d6
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hdl/IMAGES/image1/project/image1.xise
View file @ 8760fc48
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/i2c_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 8760fc48
......@@ -119,80 +119,80 @@ package image1_pkg is
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
-- component basic_trigger_top
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
-- g_CLK_PERIOD : TIME := 20 ns;
-- g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
-- g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
-- port (clk_i : in STD_LOGIC;
-- rst_i : in STD_LOGIC;
--
-- led_ttl_o : out STD_LOGIC;
--
-- fpga_o_en : out STD_LOGIC;
-- fpga_o_ttl_en : out STD_LOGIC;
-- fpga_o_inv_en : out STD_LOGIC;
-- fpga_o_blo_en : out STD_LOGIC;
--
-- level_i : in STD_LOGIC;
-- switch_i : in STD_LOGIC; --! General enable
-- manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
-- --! 24V rail after a security given
-- --! delay
-- pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- inv_i : in STD_LOGIC_VECTOR(4 downto 1);
-- inv_o : out STD_LOGIC_VECTOR(4 downto 1));
-- end component;
-- component i2c_slave_top
-- generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
-- port(sda_oen : out STD_LOGIC;
-- sda_i : in STD_LOGIC;
-- sda_o : out STD_LOGIC;
-- scl_oen : out STD_LOGIC;
-- scl_i : in STD_LOGIC;
-- scl_o : out STD_LOGIC;
--
-- wb_clk_i : in STD_LOGIC;
-- wb_rst_i : in STD_LOGIC;
--
-- wb_master_stb_o : out STD_LOGIC;
-- wb_master_cyc_o : out STD_LOGIC;
-- wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
-- wb_master_we_o : out STD_LOGIC;
-- wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
-- wb_master_ack_i : in STD_LOGIC;
-- wb_master_rty_i : in STD_LOGIC;
-- wb_master_err_i : in STD_LOGIC;
--
-- wb_slave_stb_i : in STD_LOGIC;
-- wb_slave_cyc_i : in STD_LOGIC;
-- wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_we_i : in STD_LOGIC;
-- wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_ack_o : out STD_LOGIC;
-- wb_slave_rty_o : out STD_LOGIC;
-- wb_slave_err_o : out STD_LOGIC;
--
-- pf_wb_addr_o : out STD_LOGIC;
-- rd_done_o : out STD_LOGIC;
-- wr_done_o : out STD_LOGIC;
-- i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -242,14 +242,14 @@ package image1_pkg is
wb_err_o : out STD_LOGIC);
end component;
component rtm_detector
generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
-- g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
-- port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
-- RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
-- ok_RTMM_o : out STD_LOGIC;
-- ok_RTMP_o : out STD_LOGIC);
-- end component;
-- function check_sys_cfg return BOOLEAN;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 8760fc48
......@@ -56,6 +56,7 @@ architecture behavior of image1_top_tb is
signal switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
signal rtmp, rtmm : std_logic_vector(2 downto 0);
--! ========================================================================
--! Signals for the i2c_master_driver (Renesasa alike)
......@@ -215,6 +216,8 @@ begin
write_done_o => s_i2c_driver_ctrl_done.WRITE,
read_done_o => s_i2c_driver_ctrl_done.READ);
rtmm <= "001";
rtmp <= "000";
uut: image1_top
-- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N,
......@@ -258,8 +261,9 @@ begin
LEVEL => level,
EXTRA_SWITCH => switch_i,
MR_N => manual_rst_n_o,
FPGA_RTMM_N => s_RTM_id_i.RTMM,
FPGA_RTMP_N => s_RTM_id_i.RTMP);
fpga_rtmm_n_i => rtmm,
fpga_rtmp_n_i => rtmp
);
--! Stimulus process
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 8760fc48
......@@ -70,8 +70,8 @@ package image1_top_tb_pkg is
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_RTMM_N_i : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N_i : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ 8760fc48
......@@ -24,10 +24,15 @@ use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;
entity basic_trigger_core is
generic(g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME);
port (wb_rst_i : in STD_LOGIC;
generic
(
g_clk_period : TIME;
g_output_pulse_length : TIME;
g_led_blinking_length : TIME
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
......@@ -36,7 +41,8 @@ entity basic_trigger_core is
crop_o : out STD_LOGIC;
led_o : out STD_LOGIC);
led_o : out STD_LOGIC
);
end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
......@@ -45,7 +51,7 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
-- v := g_output_pulse_length/g_clk_period;
-- report "pulse length: " & integer'image(v);
-- return v;
-- end pulselen;
......@@ -54,15 +60,13 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
-- v := g_led_blinking_length/g_clk_period;
-- report "LED length: " & integer'image(v);
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
constant c_PULSE_LENGTH : NATURAL := g_output_pulse_length/g_clk_period;
constant c_LED_LENGTH : NATURAL := g_led_blinking_length/g_clk_period;
signal s_pulse : STD_LOGIC;
......@@ -75,28 +79,46 @@ begin
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
cmp_debouncer: gc_debouncer
generic map
(
g_LENGTH => 2
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_PULSE_LENGTH)
port map (rst => wb_rst_i,
glitch_mask => "11"
);
cmp_pulse_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_PULSE_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_LED_LENGTH)
port map (rst => wb_rst_i,
output_n => pulse_n_o
);
cmp_led_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_LED_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open);
output_n => open
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 8760fc48
......@@ -41,15 +41,17 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
generic
(
g_DATA_WIDTH: NATURAL
);
port (
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
);
end gc_counter;
architecture Behavioral of gc_counter is
......@@ -57,24 +59,17 @@ architecture Behavioral of gc_counter is
begin
main_proc: process(clk_i, rst_i)
p_main: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
end if;
cnt_o <= std_logic_vector(cnt_s);
end process;
end process p_main;
end Behavioral;
hdl/ctdah_lib/rtl/gc_debouncer.vhd
View file @ 8760fc48
......@@ -35,25 +35,25 @@ entity gc_debouncer is
end gc_debouncer;
architecture Behavioral of gc_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
component gc_ff
port (
component gc_ff
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
end component;
begin
ff1: gc_ff
port map(
port map
(
Q => meta_ff1,
C => clk,
CLR => rst,
......@@ -61,7 +61,8 @@ begin
);
ff2: gc_ff
port map(
port map
(
Q => delay_s(0),
C => clk,
CLR => rst,
......@@ -69,15 +70,16 @@ begin
);
-- Metastability solved here
delay_line: for i in 1 to g_LENGTH-1 generate
gen_delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff
port map (
port map
(
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
D => delay_s(i-1)
);
end generate gen_delay_line;
process (clk)
begin
......
hdl/ctdah_lib/rtl/gc_ff.vhd
View file @ 8760fc48
......@@ -23,7 +23,8 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
......@@ -43,7 +44,6 @@ begin
else
Q <= D;
end if;
else
end if;
end process;
......
hdl/ctdah_lib/rtl/gc_simple_monostable.vhd
View file @ 8760fc48
......@@ -23,19 +23,23 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_simple_monostable is
generic(g_PULSE_LENGTH : NATURAL := 20);
port (
generic
(
g_PULSE_LENGTH : NATURAL := 20
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
output_n : out STD_LOGIC);
output_n : out STD_LOGIC
);
end gc_simple_monostable;
architecture Behavioral of gc_simple_monostable is
constant c_count_max : UNSIGNED (63 downto 0) :=
to_unsigned(g_PULSE_LENGTH, 64);
constant c_count_max : UNSIGNED (63 downto 0) := to_unsigned(g_PULSE_LENGTH, 64);
signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64);
......@@ -69,14 +73,13 @@ begin
s_count <= to_unsigned(0, 64);
s_running <= '0';
if (s_input = '1')
and (s_input_d0 = '0') then
if (s_input = '1') and (s_input_d0 = '0') then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
elsif s_running = '1' then
if s_count < c_count_max then
elsif (s_running = '1') then
if (s_count < c_count_max) then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
View file @ 8760fc48
......@@ -29,7 +29,9 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_bit is
port (rst_i : in STD_LOGIC;
port
(
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
......@@ -38,13 +40,14 @@ entity i2c_bit is
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC);
done_o : out STD_LOGIC
);
end i2c_bit;
architecture Behavioral of i2c_bit is
type bit_fsm is (R0_RESET,
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
......@@ -53,14 +56,15 @@ architecture Behavioral of i2c_bit is
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR);
Q1_ERROR
);
--! It specifies the maximum number of stages that will be employed for
--! deglitching. Clocked with wb_clk_i
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with wb_clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
--! Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal s_sda_deglitched : STD_LOGIC;
signal s_sda_deglitched_d1 : STD_LOGIC;
......@@ -68,54 +72,67 @@ architecture Behavioral of i2c_bit is
signal s_scl_deglitched : STD_LOGIC;
signal s_scl_deglitched_d1 : STD_LOGIC;
signal i2c_bit_fsm : bit_fsm;
signal state : t_state;
signal s_scl_rising : STD_LOGIC;
signal s_scl_falling : STD_LOGIC;
begin
debouncer_scl_i: i2c_debouncer
generic map(g_LENGTH => 6)
port map(rst => rst_i,
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => wb_clk_i,
input => scl_i,
output => s_scl_deglitched,
glitch_mask => c_GLITCH_MASK);
--! Probably safer operation if we add one extra delay to the scl line.
--! However, we increase the glitch time while placing an ACK.
--! We have not implemented a counter to foresee the glitch due to the
--! strange behaviour in Renesas I2C which rescales dinamically (that
--! means in the middle of an I2C transaction) the scl line.
--! Due to the variability of the scl period when an I2C transaction is
--! in progress, it is better not to add a "guesser" of the scl period.
ff1_scl : gc_ff
port map(Q => s_scl_deglitched_d1,
glitch_mask => c_GLITCH_MASK
);
-- Probably safer operation if we add one extra delay to the scl line.
-- However, we increase the glitch time while placing an ACK.
-- We have not implemented a counter to foresee the glitch due to the
-- strange behaviour in Renesas I2C which rescales dinamically (that
-- means in the middle of an I2C transaction) the scl line.
-- Due to the variability of the scl period when an I2C transaction is
cmp_scl_ff: gc_ff
port map
(
Q => s_scl_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_scl_deglitched);
D => s_scl_deglitched
);
debouncer_sda_i: i2c_debouncer
generic map(g_LENGTH => 6)
port map(rst => rst_i,
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => wb_clk_i,
input => sda_i,
output => s_sda_deglitched,
glitch_mask => c_GLITCH_MASK);
glitch_mask => c_GLITCH_MASK
);
ff1_sda : gc_ff
port map(Q => s_sda_deglitched_d1,
cmp_sda_ff: gc_ff
port map
(
Q => s_sda_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_sda_deglitched);
D => s_sda_deglitched
);
--! This is the process that samples the scl for detecting
--! rise and falling edges
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
......@@ -129,120 +146,129 @@ begin
s_scl_rising <= '0';
s_scl_falling <= '0';
end if;
else
end if;
end process;
--! @brief Combiantion process to update the outputs.
--! @param i2c_bit_fsm Finite state machine for the SDA bit detection.
p_comb_output: process(i2c_bit_fsm)
-- Combinatorial process to update the outputs.
p_comb_output: process(state)
begin
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
--! done_o is a one-clock signal
done_o <= '0';
case i2c_bit_fsm is
case state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1A_HIGH =>
rcved_o <= '1';
done_o <= '1';
when S1B_LOW =>
rcved_o <= '0';
done_o <= '1';
when S2A_START =>
start_o <= '1';
done_o <= '1';
when S2B_STOP_DETECT =>
pause_o <= '1';
done_o <= '1';
when Q1_ERROR =>
null;
when others =>
null;
end case;
end process;
end process p_comb_output;
--! @brief The fsm of this module, later on the sda sampled line is
--! validated in the falling edge of scl.
--! @bparam wb_clk_i
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if rst_i = '1' then
i2c_bit_fsm <= R0_RESET;
--! After a detection of a falling edge we update the
--! detection of a '0', a '1' and a start condition.
elsif s_scl_falling = '1' then
case i2c_bit_fsm is
if (rst_i = '1') then
state <= R0_RESET;
elsif (s_scl_falling = '1') then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
when S1A_HIGH_TMP =>
i2c_bit_fsm <= S1A_HIGH;
state <= S1A_HIGH;
when S1B_LOW_TMP =>
i2c_bit_fsm <= S1B_LOW;
state <= S1B_LOW;
when S2A_START_TMP =>
i2c_bit_fsm <= S2A_START;
state <= S2A_START;
when others =>
i2c_bit_fsm <= S0_IDLE;
state <= S0_IDLE;
end case;
--! When a rising edge is detected we annotate the first value
--! in SDA: either a temporary '0' or '1'
elsif s_scl_rising = '1' then
if s_sda_deglitched_d1 = '1' then
i2c_bit_fsm <= S1A_HIGH_TMP;
elsif (s_scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (s_sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
i2c_bit_fsm <= S1B_LOW_TMP;
state <= S1B_LOW_TMP;
end if;
else
--! When we are in high level of a scl cycle, we keep on updating
--! the fsm
if s_scl_deglitched = '1' then
case i2c_bit_fsm is
--! Just for random bit swapped coverage.
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (s_scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if s_sda_deglitched = '1' then
i2c_bit_fsm <= S1A_HIGH_TMP;
if (s_sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
i2c_bit_fsm <= S1B_LOW_TMP;
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if s_sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
i2c_bit_fsm <= S2A_START_TMP;
else
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if s_sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
i2c_bit_fsm <= S2B_STOP_DETECT;
else
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if s_sda_deglitched = '1' then
if (s_sda_deglitched = '1') then
--! This happens if the deglitching is not enough
i2c_bit_fsm <= Q1_ERROR;
else
state <= Q1_ERROR;
end if;
when others =>
i2c_bit_fsm <= S0_IDLE;
state <= S0_IDLE;
end case;
else
if s_scl_deglitched_d1 = '0' then
i2c_bit_fsm <= S0_IDLE;
else
if (s_scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
end if;
else
end if;
end process;
end process p_fsm;
end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd
View file @ 8760fc48
......@@ -30,57 +30,69 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_debouncer is
generic (g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH);
port (rst : in STD_LOGIC;
generic
(
g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0));
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC;
--! The first of this signal is already stable (ff'ed two times at [0])
-- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
ff1: gc_ff
port map(
cmp_ff1: gc_ff
port map
(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input);
D => input
);
ff2: gc_ff
port map(
cmp_ff2: gc_ff
port map
(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0);
D => s_input_d0
);
sync_delay_line: for i in 1 to g_LENGTH - 1 generate
D_Flip_Flop : gc_ff
port map (
gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
cmp_ff: gc_ff
port map
(
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1));
end generate sync_delay_line;
D => s_delay(i-1)
);
end generate gen_sync_delay_line;
p_output : process (clk)
p_output: process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
if (rst = '1') then
output <= '1';
else
--! We can deglitch either zeros or ones
-- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay)and glitch_mask) = glitch_mask) then
or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0);
else
--! Internall pull-up of the pin
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 8760fc48
......@@ -163,10 +163,10 @@ package i2c_slave_pkg is
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
......@@ -189,9 +189,9 @@ package i2c_slave_pkg is
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -200,9 +200,9 @@ package i2c_slave_pkg is
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 8760fc48
......@@ -26,13 +26,16 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_slave_top is
generic (g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
);
port
(
sda_oen : out STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
......@@ -43,9 +46,9 @@ entity i2c_slave_top is
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -54,9 +57,9 @@ entity i2c_slave_top is
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......@@ -70,56 +73,58 @@ end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
signal s_CTR0_slv : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0;
signal s_LT_slv : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal ctr0 : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal lt : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal s_DRXA : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_DRXB : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxa : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxb : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_pf_wb_addr : STD_LOGIC;
signal s_pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal s_rd_done : STD_LOGIC;
signal s_wr_done : STD_LOGIC;
signal pf_wb_addr : STD_LOGIC;
signal pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal rd_done : STD_LOGIC;
signal wr_done : STD_LOGIC;
signal s_clk_i2c : STD_LOGIC;
signal s_rst_i2c : STD_LOGIC;
signal s_reset_extensor : STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1
downto 0) := (others => '1');
signal rst_i2c : STD_LOGIC;
signal reset_extender: STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1 downto 0) := (others => '1');
begin
pf_wb_addr_o <= s_pf_wb_addr;
rd_done_o <= s_rd_done;
wr_done_o <= s_wr_done;
--! Added for simulation
s_CTR0 <= f_CTR0(s_CTR0_slv);
pf_wb_addr_o <= pf_wb_addr;
rd_done_o <= rd_done;
wr_done_o <= wr_done;
inst_i2c_slave_core: i2c_slave_core
port map(clk_i => wb_clk_i,
cmp_i2c_slave_core: i2c_slave_core
port map
(
clk_i => wb_clk_i,
rst_i => wb_rst_i,
sda_oen => sda_oen,
sda_en_o => sda_en_o,
sda_i => sda_i,
sda_o => sda_o,
scl_oen => scl_oen,
scl_en_o => scl_en_o,
scl_i => scl_i,
scl_o => scl_o,
CTR0_i => s_CTR0_slv,
LT_o => s_LT_slv,
DRXA_o => s_DRXA,
DRXB_o => s_DRXB,
CTR0_i => ctr0,
LT_o => lt,
DRXA_o => drxa,
DRXB_o => drxb,
pf_wb_addr_o => s_pf_wb_addr,
pf_wb_data_i => s_pf_wb_data,
rd_done_o => s_rd_done,
wr_done_o => s_wr_done);
pf_wb_addr_o => pf_wb_addr,
pf_wb_data_i => pf_wb_data,
rd_done_o => rd_done,
wr_done_o => wr_done
);
inst_i2c_regs: i2c_regs
port map(pf_wb_addr_i => s_pf_wb_addr,
pf_wb_data_o => s_pf_wb_data,
rd_done_i => s_rd_done,
wr_done_i => s_wr_done,
cmp_i2c_regs: i2c_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
pf_wb_data_o => pf_wb_data,
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
......@@ -128,9 +133,9 @@ begin
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_dat_i => wb_master_dat_i,
wb_master_dat_o => wb_master_dat_o,
wb_master_adr_o => wb_master_adr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
......@@ -139,32 +144,32 @@ begin
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i,
wb_slave_data_i => wb_slave_data_i,
wb_slave_data_o => wb_slave_data_o,
wb_slave_addr_i => wb_slave_addr_i,
wb_slave_dat_i => wb_slave_dat_i,
wb_slave_dat_o => wb_slave_dat_o,
wb_slave_adr_i => wb_slave_adr_i,
wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
CTR0_o => s_CTR0_slv,
LT_i => s_LT_slv,
DRXA_i => s_DRXA,
DRXB_i => s_DRXB,
i2c_addr_i => i2c_addr_i);
CTR0_o => ctr0,
LT_i => lt,
DRXA_i => drxa,
DRXB_i => drxb,
i2c_addr_i => i2c_addr_i
);
s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1);
rst_i2c <= reset_extender(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_reset_extensor <= (others => '1');
reset_extender <= (others => '1');
else
s_reset_extensor(0) <= '0';
reset_extender(0) <= '0';
for i in 1 to 2**c_RST_EXTENSOR -1 loop
s_reset_extensor(i) <= s_reset_extensor(i-1);
reset_extender(i) <= reset_extender(i-1);
end loop;
end if;
end if;
......
hdl/rtm_detector/rtl/rtm_detector.vhd
View file @ 8760fc48
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.rtm_detector_pkg.ALL;
--use work.rtm_detector_pkg.ALL;
entity rtm_detector is
generic(g_identifier_RTMM : t_RTMM;
g_identifier_RTMP : t_RTMP);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end rtm_detector;
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture Behavioral of rtm_detector is
signal s_identifier_RTMM : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMM);
signal s_identifier_RTMP : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMP);
signal s_RTMM : UNSIGNED(2 downto 0);
signal s_RTMP : UNSIGNED(2 downto 0);
-- signal s_identifier_rtmm : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmm);
-- signal s_identifier_rtmp : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmp);
-- signal s_rtmm : unsigned(2 downto 0);
-- signal s_rtmp : unsigned(2 downto 0);
begin
s_RTMM <= UNSIGNED(RTMM_i);
s_RTMP <= UNSIGNED(RTMP_i);
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
ok_RTMM_o <= '1' when s_RTMM = s_identifier_RTMM
else '0';
ok_RTMP_o <= '1' when s_RTMP = s_identifier_RTMP
else '0';
-- s_rtmm <= unsigned(rtmm_i);
-- s_rtmp <= unsigned(rtmp_i);
--
-- ok_rtmm_o <= '1' when s_rtmm = s_identifier_rtmm else '0';
-- ok_rtmp_o <= '1' when s_rtmp = s_identifier_rtmp else '0';
end Behavioral;
hdl/rtm_detector/rtl/rtm_detector_pkg.vhd
View file @ 8760fc48
......@@ -4,44 +4,6 @@ use IEEE.NUMERIC_STD.ALL;
package rtm_detector_pkg is
--! Please refer to:
--! http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--! to see conventions used to guarantee consistency between front board
--! and read transition modules
--! It should be noted that the RTMM, and RTMP pins are pulled up in
--! all the Front boards.
--! On 27/Nov/2012 the correspondencies are:
--!
--! __________________________________________
--! | Board | RTMM[2] | RTMM[1] | RTMM[0] |
--! +-----------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | RTMM_V1 | '1' | '1' | '0' |
--! | Reserved0 | '1' | '0' | '1' |
--! | Reserved1 | '1' | '0' | '0' |
--! | Reserved2 | '0' | '1' | '1' |
--! | Reserved3 | '0' | '1' | '0' |
--! | Reserved4 | '0' | '0' | '1' |
--! | Reserved5 | '0' | '0' | '0' |
--! +-----------+---------+---------+---------+
--!
--! _____________________________________________
--! | Board | RTMP[2] | RTMP[1] | RTMP[0] |
--! +-------------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | Blocking_V1 | '1' | '1' | '0' |
--! | RS485_V1 | '1' | '0' | '1' |
--! | Reserved0 | '1' | '0' | '0' |
--! | Reserved1 | '0' | '1' | '1' |
--! | Reserved2 | '0' | '1' | '0' |
--! | Reserved3 | '0' | '0' | '1' |
--! | Reserved4 | '0' | '0' | '0' |
--! +-------------+---------+---------+---------+
--!
--! It should be noted that there is an inverter before the FPGA,
--! so the signals/constant will be negated in rtm_detector.vhd
type t_RTMM is (RTMM_ERROR,
RTMM_V1,
RESERVED0,
......
installation/V2/dummy/constraints/BloV2.ucf
View file @ 8760fc48
......@@ -7,8 +7,8 @@
###----------------------------------------
#
#
#NET "RST_N" LOC = N20;
# NET "RST_N" IOSTANDARD = "LVCMOS33";
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SYSRESET_N" LOC = L20;
# NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
#NET "MR_N" LOC = T22;
......
installation/V2/dummy/project/dummy.gise
View file @ 8760fc48
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installation/V2/dummy/project/dummy.xise
View file @ 8760fc48
......@@ -318,6 +318,7 @@
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
......
installation/V2/dummy/project/iseconfig/dummy_top.xreport
View file @ 8760fc48
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-02-01T16:31:39</DateModified>
<DateModified>2013-02-22T10:48:53</DateModified>
<ModuleName>dummy_top</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/iseconfig/dummy_top.xreport</SavedFilePath>
......
installation/V2/dummy/top/dummy_top.vhd
View file @ 8760fc48
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