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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
8e820682
Commit
8e820682
authored
Jan 26, 2017
by
Denia Bouhired-Ferrag
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syn/Release/conv_ttl_blo.xise
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8e820682
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@@ -16,43 +16,43 @@
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...
...
@@ -723,6 +737,9 @@
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...
...
@@ -748,6 +765,7 @@
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"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
...
...
@@ -788,7 +806,8 @@
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/testbench"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.testbench"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -798,22 +817,28 @@
<property
xil_pn:name=
"Shift Register Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Shift Register Minimum Size spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Show All Models"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Signal window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Resolution"
xil_pn:value=
"Default (1 ps)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time ISim"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Map"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Modelsim"
xil_pn:value=
"1100ms"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Simulation Run Time Par"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Translate"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulator"
xil_pn:value=
"
ISim (VHDL/Verilog)"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Simulator"
xil_pn:value=
"
Modelsim-SE Mixed"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Slice Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Source window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.testbench"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Speed Grade"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Structure window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Synthesis Tool"
xil_pn:value=
"XST (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Target Simulator"
xil_pn:value=
"
Please Specify
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Target Simulator"
xil_pn:value=
"
Modelsim-SE Mixed
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Map"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Par"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Top-Level Module Name in Output Netlist"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -822,7 +847,13 @@
<property
xil_pn:name=
"Tristate On Configuration Pulse Width"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Unused IOB Pins"
xil_pn:value=
"Pull Down"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use 64-bit PlanAhead on 64-bit Systems"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Automatic Do File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Clock Enable"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Configuration Name"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Route"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -836,6 +867,7 @@
<property
xil_pn:name=
"Use Custom Waveform Configuration File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use DSP Block spartan6"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Explicit Declarations Only"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use LOC Constraints"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use RLOC Constraints"
xil_pn:value=
"Yes"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Smart Guide"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -846,17 +878,20 @@
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Syntax"
xil_pn:value=
"93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Value Range Check"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Variables window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Verilog Macros"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0x1FFF"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Wave window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
"
"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
"
Architecture|testbench|behav"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"PROP_DesignName"
xil_pn:value=
"conv_ttl_blo"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DevFamilyPMName"
xil_pn:value=
"spartan6"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_FPGAConfiguration"
xil_pn:value=
"FPGAConfiguration"
xil_pn:valueState=
"default"
/>
...
...
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