Added I2C bridge to firmware, updated pulse & reset gens with enable inp

8f476bcc · Theodor-Adrian Stana · 6e85dbda · 8f476bcc · 8f476bcc · 8f476bcc
Commit 8f476bcc authored May 17, 2013 by Theodor-Adrian Stana
14 changed files
--- a/hdl/pulse_gen/rtl/pulse_gen.vhd
+++ b/hdl/pulse_gen/rtl/pulse_gen.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Test module for old repeater boards
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity pulse_gen is
+  generic
+  (
+    g_pwidth : natural := 200;
+    g_freq   : natural := 400;
+    g_delay  : natural := 0
+  );
+  port
+  (
+    clk_i   : in  std_logic;
+    rst_n_i : in  std_logic;
+    en_i    : in  std_logic;
+    pulse_o : out std_logic
+  );
+end entity pulse_gen;
+
+
+architecture behav of pulse_gen is
+
+  --============================================================================
+  -- Function and procedure declarations
+  --============================================================================
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal freq_cnt  : unsigned(f_log2_size(g_freq)-1 downto 0);
+  signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
+  signal delay_en  : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Delay logic
+  --============================================================================
+  gen_nodelay: if (g_delay = 0) generate
+    delay_en <= '0';
+  end generate gen_nodelay;
+
+  gen_delay: if (g_delay > 0) generate
+    p_delay: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if (rst_n_i = '0') then
+          delay_en  <= '1';
+          delay_cnt <= (others => '0');
+        elsif (en_i = '1') and (delay_en = '1') then
+          delay_cnt <= delay_cnt + 1;
+          if (delay_cnt = g_delay-1) then
+            delay_en  <= '0';
+            delay_cnt <= (others => '0'); 
+          end if;
+        end if;
+      end if;
+    end process p_delay;
+  end generate gen_delay;
+
+  --============================================================================
+  -- Pulse generation logic
+  --============================================================================
+  p_gen_pulse: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+        freq_cnt  <= (others => '0');
+        pulse_o   <= '0';
+      elsif (en_i = '1') and (delay_en = '0') then
+        freq_cnt <= freq_cnt + 1;
+        pulse_o  <= '0';
+        if (freq_cnt < g_pwidth) then
+          pulse_o  <= '1';
+        elsif (freq_cnt = g_freq-1) then
+          freq_cnt <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process p_gen_pulse;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/pulse_generator/rtl/pulse_generator.vhd
+++ b/hdl/pulse_generator/rtl/pulse_generator.vhd
@@ -79,6 +79,9 @@ entity pulse_generator is
    -- '0' - TYPE 2 (glitch-insensitive, with output jitter)
    pulse_type_i : in  std_logic;

+    -- Enable input, pulse generation is enabled when '1'
+    en_i         : in  std_logic;
+
    -- Trigger input, has to be '1' to assure pulse output with delay no greater
    -- than internal gate delays.
    trig_i       : in  std_logic;
@@ -180,7 +183,9 @@ begin
    if (pulse_rst = '1') then
      pulse_type1 <= '0';
    elsif rising_edge(trig_i) then
-      pulse_type1 <= '1';
+      if (en_i = '1') then
+        pulse_type1 <= '1';
+      end if;
    end if;
  end process p_pulse_type1;

@@ -192,7 +197,7 @@ begin
        pulse_type1_d0 <= '0';
        pulse_type1_d1 <= '0';
        pulse_type1_d2 <= '0';
-      else
+      elsif (en_i = '1') then
        pulse_type1_d0 <= pulse_type1;
        pulse_type1_d1 <= pulse_type1_d0;
        pulse_type1_d2 <= pulse_type1_d1;
@@ -206,10 +211,11 @@ begin
    if rising_edge(clk_i) then
      if (rst_n_i = '0') then
        pulse_type2 <= '0';
-      elsif (state = ST_PULSE_TYPE2) then
-        pulse_type2 <= '1';
-      else
+      elsif (en_i = '1') then
        pulse_type2 <= '0';
+        if (state = ST_PULSE_TYPE2) then
+          pulse_type2 <= '1';
+        end if;
      end if;
    end if;
  end process p_pulse_type2;
@@ -241,7 +247,7 @@ begin
        pulse_rst    <= '1';
        width_cnt    <= (others => '0');
        trig_degl_d0 <= '0';
-      else
+      elsif (en_i = '1') then
        -- Deglitched trigger delay
        trig_degl_d0 <= trig_degl;


--- a/hdl/release/rtl/Manifest.py
+++ b/hdl/release/rtl/Manifest.py
+files = [
+      "conv_regs.vhd"
+    ];
--- a/hdl/release/rtl/conv_regs.vhd
+++ b/hdl/release/rtl/conv_regs.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Converter board registers
+---------------------------------------------------------------------------------------
+-- File           : conv_regs.vhd
+-- Author         : auto-generated by wbgen2 from conv_regs.wb
+-- Created        : Thu May 16 16:11:38 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity conv_regs is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(0 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+    conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+    conv_regs_cr_rst_unlock_o                : out    std_logic;
+-- Port for BIT field: 'Reset bit' in reg: 'Control register'
+    conv_regs_cr_rst_o                       : out    std_logic
+  );
+end conv_regs;
+
+architecture syn of conv_regs is
+
+signal conv_regs_id_bits_int                    : std_logic_vector(31 downto 0);
+signal conv_regs_cr_rst_unlock_int              : std_logic      ;
+signal conv_regs_cr_rst_int                     : std_logic      ;
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(0 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      conv_regs_id_bits_int <= x"424C4F32";
+      conv_regs_cr_rst_unlock_int <= '0';
+      conv_regs_cr_rst_int <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(0) is
+          when '0' => 
+            if (wb_we_i = '1') then
+              conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when '1' => 
+            if (wb_we_i = '1') then
+              conv_regs_cr_rst_unlock_int <= wrdata_reg(30);
+              if (conv_regs_cr_rst_unlock_int = '1') then
+                conv_regs_cr_rst_int <= wrdata_reg(31);
+              end if;
+            end if;
+            rddata_reg(30) <= conv_regs_cr_rst_unlock_int;
+            rddata_reg(31) <= conv_regs_cr_rst_int;
+            rddata_reg(0) <= 'X';
+            rddata_reg(1) <= 'X';
+            rddata_reg(2) <= 'X';
+            rddata_reg(3) <= 'X';
+            rddata_reg(4) <= 'X';
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- bits
+  conv_regs_id_bits_o <= conv_regs_id_bits_int;
+-- Reset unlock bit
+  conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
+-- Reset bit
+  conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/hdl/release/rtl/conv_regs.wb
+++ b/hdl/release/rtl/conv_regs.wb
+peripheral {
+  name = "Converter board registers";
+  hdl_entity = "conv_regs";
+  prefix = "conv_regs";
+
+  reg {
+    name = "Board ID register";
+    description = "Bits of ID register, defaulting to ASCII string of BLO2";
+    prefix = "id";
+    field {
+      name = "bits";
+      prefix = "bits";
+      type = SLV;
+      size = 32;
+    };
+  };
+
+  reg {
+    name = "Control register";
+    description = "Contains bits that control operation of the converter modules";
+    prefix = "cr";
+    field {
+      name = "Reset unlock bit";
+      prefix = "rst_unlock";
+      description = "1 - unlock reset bit\
+      0 - lock reset bit";
+      type = BIT;
+      align = 30;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+    field {
+      name = "Reset bit";
+      prefix = "rst";
+      description = "1 - initiate logic reset\
+      0 - no reset";
+      type = BIT;
+      align = 31;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+};
--- a/hdl/release/syn/Makefile
+++ b/hdl/release/syn/Makefile
@@ -38,11 +38,14 @@ CWD := $(shell pwd)

 FILES := ../top/conv_ttl_blo_v2.ucf \
 ../top/conv_ttl_blo_v2.vhd \
+../rtl/conv_regs.vhd \
 ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
 ../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
 ../../reset_gen/rtl/reset_gen.vhd \
-../../pulse_generator/rtl/pulse_generator.vhd \
+../../vme64x_i2c/rtl/i2c_slave.vhd \
+../../vme64x_i2c/rtl/vme64x_i2c.vhd \
 ../../glitch_filt/rtl/glitch_filt.vhd \
+../../pulse_generator/rtl/pulse_generator.vhd \
 ../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
 ../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
 ../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \

--- a/hdl/release/syn/conv_ttl_blo_v2.bit
+++ b/hdl/release/syn/conv_ttl_blo_v2.bit
--- a/hdl/release/syn/conv_ttl_blo_v2.gise
+++ b/hdl/release/syn/conv_ttl_blo_v2.gise
@@ -72,36 +72,37 @@
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993366" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366993353">
+    <transform xil_pn:end_ts="1368794227" xil_pn:in_ck="6309703152952971517" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1368794212">
      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
@@ -117,11 +118,11 @@
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
-    <transform xil_pn:end_ts="1366993366" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366993366">
+    <transform xil_pn:end_ts="1368794227" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1368794227">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1366993375" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366993366">
+    <transform xil_pn:end_ts="1368794236" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1368794227">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_ngo"/>
@@ -130,7 +131,7 @@
      <outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
      <outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1366993409" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366993375">
+    <transform xil_pn:end_ts="1368794274" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1368794236">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@@ -143,7 +144,7 @@
      <outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
      <outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
    </transform>
-    <transform xil_pn:end_ts="1366993444" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366993409">
+    <transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1368794274">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -157,7 +158,7 @@
      <outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
      <outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1366993465" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366993444">
+    <transform xil_pn:end_ts="1368794333" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1368794312">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@@ -169,7 +170,7 @@
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
-    <transform xil_pn:end_ts="1366993444" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366993434">
+    <transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1368794301">
      <status xil_pn:value="FailedRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

--- a/hdl/release/syn/conv_ttl_blo_v2.xise
+++ b/hdl/release/syn/conv_ttl_blo_v2.xise
@@ -19,6 +19,9 @@
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
  </autoManagedFiles>

  <properties>
@@ -344,49 +347,301 @@
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="../rtl/conv_regs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
-    <file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    <file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
-    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
    <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
  </files>


--- a/hdl/release/top/Manifest.py
+++ b/hdl/release/top/Manifest.py
@@ -6,6 +6,8 @@ files = [
 modules = {
      "local" : [
          "../../reset_gen",
+          "../rtl",
+          "../../vme64x_i2c",
          "../../pulse_generator",
          "../../rtm_detector",
          "../../bicolor_led_ctrl",

--- a/hdl/release/top/conv_ttl_blo_v2.ucf
+++ b/hdl/release/top/conv_ttl_blo_v2.ucf
@@ -253,49 +253,50 @@ NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
 NET "fpga_trig_blo_o[6]" LOC = R9;
 NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";

-###=============================================================================
-###--       VME CONNECTOR SIGNALS
-###=============================================================================
-###-----------------------------------------------------------------------------
-###-- I2C lines
-###-----------------------------------------------------------------------------
-#NET "scl_i" LOC = F19;
-#NET "scl_i" IOSTANDARD = LVCMOS33;
-#NET "scl_o" LOC = E20;
-#NET "scl_o" IOSTANDARD = LVCMOS33;
-#NET "scl_o" DRIVE = 4;
-#NET "scl_oe_o" LOC = H18;
-#NET "scl_oe_o" IOSTANDARD = LVCMOS33;
-#NET "scl_oe_o" DRIVE = 4;
-##  NET "scl_oe_o"                 PULLDOWN;
-#NET "sda_i" LOC = G20;
-#NET "sda_i" IOSTANDARD = LVCMOS33;
-#NET "sda_o" LOC = F20;
-#NET "sda_o" IOSTANDARD = LVCMOS33;
-#NET "sda_o" SLEW = FAST;
-#NET "sda_o" DRIVE = 4;
-##  NET "sda_o"                  PULLUP;
-#NET "sda_oe_o" LOC = J19;
-#NET "sda_oe_o" IOSTANDARD = LVCMOS33;
-#NET "sda_oe_o" SLEW = FAST;
-#NET "sda_oe_o" DRIVE = 4;
-##  NET "sda_oe_o"                 PULLDOWN;
+##=============================================================================
+##--       VME CONNECTOR SIGNALS
+##=============================================================================
+##-----------------------------------------------------------------------------
+##-- I2C lines
+##-----------------------------------------------------------------------------
+NET "scl_i" LOC = F19;
+NET "scl_i" IOSTANDARD = LVCMOS33;
+NET "scl_o" LOC = E20;
+NET "scl_o" IOSTANDARD = LVCMOS33;
+NET "scl_o" DRIVE = 4;
+NET "scl_oe_o" LOC = H18;
+NET "scl_oe_o" IOSTANDARD = LVCMOS33;
+NET "scl_oe_o" DRIVE = 4;
+#  NET "scl_oe_o"                 PULLDOWN;
+NET "sda_i" LOC = G20;
+NET "sda_i" IOSTANDARD = LVCMOS33;
+NET "sda_o" LOC = F20;
+NET "sda_o" IOSTANDARD = LVCMOS33;
+NET "sda_o" SLEW = FAST;
+NET "sda_o" DRIVE = 4;
+#  NET "sda_o"                  PULLUP;
+NET "sda_oe_o" LOC = J19;
+NET "sda_oe_o" IOSTANDARD = LVCMOS33;
+NET "sda_oe_o" SLEW = FAST;
+NET "sda_oe_o" DRIVE = 4;
+#  NET "sda_oe_o"                 PULLDOWN;
+
+##-----------------------------------------------------------------------------
+##-- Geographical Address
+##-----------------------------------------------------------------------------
+NET "fpga_ga_i[0]" LOC = H20;
+NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
+NET "fpga_ga_i[1]" LOC = J20;
+NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
+NET "fpga_ga_i[2]" LOC = K19;
+NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
+NET "fpga_ga_i[3]" LOC = K20;
+NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
+NET "fpga_ga_i[4]" LOC = L19;
+NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
+NET "fpga_gap_i" LOC = H19;
+NET "fpga_gap_i" IOSTANDARD = LVCMOS33;

-###-----------------------------------------------------------------------------
-###-- Geographical Address
-###-----------------------------------------------------------------------------
-#NET "fpga_ga_i[0]" LOC = H20;
-#NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
-#NET "fpga_ga_i[1]" LOC = J20;
-#NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
-#NET "fpga_ga_i[2]" LOC = K19;
-#NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
-#NET "fpga_ga_i[3]" LOC = K20;
-#NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
-#NET "fpga_ga_i[4]" LOC = L19;
-#NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
-#NET "fpga_gap_i" LOC = H19;
-#NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
 ###-----------------------------------------------------------------------------
 ###-- ROM memory
 ###-----------------------------------------------------------------------------

--- a/hdl/release/top/conv_ttl_blo_v2.vhd
+++ b/hdl/release/top/conv_ttl_blo_v2.vhd
@@ -35,6 +35,7 @@ use IEEE.NUMERIC_STD.ALL;
 use UNISIM.VCOMPONENTS.ALL;

 use work.bicolor_led_ctrl_pkg.all;
+use work.wishbone_pkg.all;

 entity conv_ttl_blo_v2 is
  generic
@@ -81,8 +82,17 @@ entity conv_ttl_blo_v2 is
    
    extra_switch_n_i         : in  std_logic_vector(7 downto 1);
    
-    -- It allows power sequencing of the
-    -- 24V rail after a security given delay
+    -- Lines for the i2c_slave
+    scl_i                  : in  std_logic;
+    scl_o                  : out std_logic;
+    scl_oe_o               : out std_logic;
+    sda_i                  : in  std_logic;
+    sda_o                  : out std_logic;
+    sda_oe_o               : out std_logic;
+    fpga_ga_i              : in  std_logic_vector(4 downto 0);
+    fpga_gap_i             : in  std_logic;
+
+    -- It allows power sequencing of the 24V rail after a security delay
    mr_n_o                 : out std_logic;

    -- RTM identifiers, should match with the expected values
@@ -96,6 +106,41 @@ end conv_ttl_blo_v2;
 architecture behav of conv_ttl_blo_v2 is


+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  -- Number of Wishbone masters and slaves, for wb_crossbar
+  constant c_nr_masters      : natural :=  1;
+  constant c_nr_slaves       : natural :=  1;
+
+  -----------------------------------------
+  -- Memory map
+  -- * all registers are word-addressable
+  -- * all registers are word-aligned
+  -----------------------------------------
+  --    CONV_REGS       [000-040]
+  -----------------------------------------
+  -- slave order definitions
+  constant c_slv_conv_regs : natural := 0;
+
+  -- base address definitions
+  constant c_addr_conv_regs : t_wishbone_address := x"00000000";
+
+  -- address mask definitions
+  constant c_mask_conv_regs : t_wishbone_address := x"00000FC0";
+
+  -- addresses constant for Wishbone crossbar
+  constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
+                  := (
+                       c_slv_conv_regs => c_addr_conv_regs
+                     );
+
+  -- masks constant for Wishbone crossbar
+  constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
+                  := (
+                       c_slv_conv_regs => c_mask_conv_regs
+                     );
+
  --============================================================================
  -- Component declarations
  --============================================================================
@@ -110,6 +155,7 @@ architecture behav of conv_ttl_blo_v2 is
    port
    (
      clk_i   : in  std_logic;
+      rst_i   : in  std_logic;
      rst_n_o : out std_logic
    );
  end component reset_gen;
@@ -139,6 +185,9 @@ architecture behav of conv_ttl_blo_v2 is
      -- '0' - TYPE 2 (glitch-insensitive, with output jitter)
      pulse_type_i : in  std_logic;

+      -- Enable input, pulse generation is enabled when '1'
+      en_i         : in  std_logic;
+
      -- Trigger input, has to be '1' to assure pulse output with delay no greater
      -- than internal gate delays.
      trig_i       : in  std_logic;
@@ -173,10 +222,68 @@ architecture behav of conv_ttl_blo_v2 is
    (
      clk_i   : in  std_logic;
      rst_n_i : in  std_logic;
+      en_i    : in  std_logic;
      pulse_o : out std_logic
    );
  end component pulse_gen;
  
+  -- I2C bridge
+  -- (use: convert I2C transfers into WB transfers on memmapped registers)  
+  component vme64x_i2c is
+    port
+    (
+      -- Clock, reset
+      clk_i      : in  std_logic;
+      rst_n_i    : in  std_logic;
+
+      -- I2C lines
+      sda_en_o   : out std_logic;
+      sda_i      : in  std_logic;
+      sda_o      : out std_logic;
+      scl_en_o   : out std_logic;
+      scl_i      : in  std_logic;
+      scl_o      : out std_logic;
+
+      -- I2C address and status
+      i2c_addr_i : in  std_logic_vector(6 downto 0);
+      i2c_done_o : out std_logic;
+
+      -- Wishbone master signals
+      wbm_stb_o  : out std_logic;
+      wbm_cyc_o  : out std_logic;
+      wbm_sel_o  : out std_logic_vector(3 downto 0);
+      wbm_we_o   : out std_logic;
+      wbm_dat_i  : in  std_logic_vector(31 downto 0);
+      wbm_dat_o  : out std_logic_vector(31 downto 0);
+      wbm_adr_o  : out std_logic_vector(31 downto 0);
+      wbm_ack_i  : in  std_logic;
+      wbm_rty_i  : in  std_logic;
+      wbm_err_i  : in  std_logic
+    );
+  end component vme64x_i2c;
+  
+  component conv_regs is
+    port (
+      rst_n_i                                  : in     std_logic;
+      clk_sys_i                                : in     std_logic;
+      wb_adr_i                                 : in     std_logic_vector(0 downto 0);
+      wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+      wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+      wb_cyc_i                                 : in     std_logic;
+      wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+      wb_stb_i                                 : in     std_logic;
+      wb_we_i                                  : in     std_logic;
+      wb_ack_o                                 : out    std_logic;
+      wb_stall_o                               : out    std_logic;
+    -- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
+      conv_regs_id_bits_o                      : out    std_logic_vector(31 downto 0);
+    -- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
+      conv_regs_cr_rst_unlock_o                : out    std_logic;
+    -- Port for BIT field: 'Reset bit' in reg: 'Control register'
+      conv_regs_cr_rst_o                       : out    std_logic
+    );
+  end component conv_regs;
+
  --============================================================================
  -- Signal declarations
  --============================================================================
@@ -219,13 +326,23 @@ architecture behav of conv_ttl_blo_v2 is

  signal tmp_pulse : std_logic;
  
+  -- Wishbone crossbar signals
+  signal xbar_slave_in       : t_wishbone_slave_in_array  (c_nr_masters - 1 downto 0);
+  signal xbar_slave_out      : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
+  signal xbar_master_in      : t_wishbone_master_in_array (c_nr_slaves  - 1 downto 0);
+  signal xbar_master_out     : t_wishbone_master_out_array(c_nr_slaves  - 1 downto 0);
+  
+  -- I2C bridge signals
+  signal i2c_done            : std_logic;
+  signal i2c_up              : std_logic;
+  signal i2c_addr            : std_logic_vector(6 downto 0);
  
 begin

  --============================================================================
  -- Generate 125 MHz global signal from differential lines
  --============================================================================
-  cmp_125_diff_buf: IBUFGDS
+  cmp_125_diff_buf : IBUFGDS
  generic map 
  (
    DIFF_TERM    => TRUE,
@@ -242,7 +359,7 @@ begin
  -- Internal and external reset generation
  --============================================================================
  -- Configure reset generator for 96ms power-on reset
-  cmp_reset_gen: reset_gen
+  cmp_reset_gen : reset_gen
    generic map
    (
      -- Reset time: 12 * 8ns * (10**6) = 96 ms
@@ -251,18 +368,118 @@ begin
    port map
    (
      clk_i   => clk125,
+      rst_i   => '0',
      rst_n_o => rst_n
    );
  
 --  rst  <= not rst_n;
  mr_n_o <= rst_n;

+  --============================================================================
+  -- I2C bridge logic
+  --============================================================================
+  i2c_addr <= "10" & fpga_ga_i;
+  
+  cmp_i2c_bridge : vme64x_i2c
+    port map
+    (
+      -- Clock, reset
+      clk_i      => clk125,
+      rst_n_i    => rst_n,
+
+      -- I2C lines
+      sda_en_o   => sda_oe_o,
+      sda_i      => sda_i,
+      sda_o      => sda_o,
+      scl_en_o   => scl_oe_o,
+      scl_i      => scl_i,
+      scl_o      => scl_o,
+
+      -- I2C address and status
+      i2c_addr_i => i2c_addr,
+      i2c_done_o => i2c_done,
+
+      -- Wishbone master signals
+      wbm_stb_o  => xbar_slave_in(0).stb,
+      wbm_cyc_o  => xbar_slave_in(0).cyc,
+      wbm_sel_o  => xbar_slave_in(0).sel,
+      wbm_we_o   => xbar_slave_in(0).we,
+      wbm_dat_i  => xbar_slave_out(0).dat,
+      wbm_dat_o  => xbar_slave_in(0).dat,
+      wbm_adr_o  => xbar_slave_in(0).adr,
+      wbm_ack_i  => xbar_slave_out(0).ack,
+      wbm_rty_i  => xbar_slave_out(0).rty,
+      wbm_err_i  => xbar_slave_out(0).err
+    );
+  
+  -- Process to set the I2C_UP signal for display on the front panel
+  -- of the front module. The I2C_UP signal is permanently set once an
+  -- I2C transfer has successfully completed, as signaled by the RD_DONE
+  -- and WR_DONE outputs of the I2C slave.
+  p_i2c_up : process (clk125) is
+  begin
+    if rising_edge(clk125) then
+      if (rst_n = '0') then
+        i2c_up <= '0';
+      elsif (i2c_done = '1') then
+        i2c_up <= '1';
+      end if;
+    end if;
+  end process p_i2c_up;
+
+  --============================================================================
+  -- Instantiation and connection of the main Wishbone crossbar
+  --============================================================================
+  xbar_master_in(0).int <= '0';
+  xbar_master_in(0).err <= '0';
+
+  cmp_wb_crossbar : xwb_crossbar
+  generic map
+  (
+    g_num_masters => c_nr_masters,
+    g_num_slaves  => c_nr_slaves,
+    g_registered  => false,
+    g_address     => c_addresses,
+    g_mask        => c_masks
+  )
+  port map
+  (
+    clk_sys_i => clk125,
+    rst_n_i   => rst_n,
+    slave_i   => xbar_slave_in,
+    slave_o   => xbar_slave_out,
+    master_i  => xbar_master_in,
+    master_o  => xbar_master_out
+  );
+
+  --============================================================================
+  -- Converter board registers
+  --============================================================================
+  cmp_conv_regs : conv_regs
+    port map (
+      rst_n_i                   => rst_n,
+      clk_sys_i                 => clk125,
+      wb_adr_i                  => xbar_master_out(c_slv_conv_regs).adr(2 downto 2),
+      wb_dat_i                  => xbar_master_out(c_slv_conv_regs).dat,
+      wb_dat_o                  => xbar_master_in (c_slv_conv_regs).dat,
+      wb_cyc_i                  => xbar_master_out(c_slv_conv_regs).cyc,
+      wb_sel_i                  => xbar_master_out(c_slv_conv_regs).sel,
+      wb_stb_i                  => xbar_master_out(c_slv_conv_regs).stb,
+      wb_we_i                   => xbar_master_out(c_slv_conv_regs).we,
+      wb_ack_o                  => xbar_master_in (c_slv_conv_regs).ack,
+      wb_stall_o                => xbar_master_in (c_slv_conv_regs).stall,
+
+      conv_regs_id_bits_o       => open,
+      conv_regs_cr_rst_unlock_o => open,
+      conv_regs_cr_rst_o        => open
+    );
+
  --============================================================================
  -- Output enable logic
  --============================================================================
  -- The general output enable is set first and the blocking, TTL
  -- and INV output enable signals are set one clock cycle later.
-  p_oe: process(clk125)
+  p_oe : process(clk125)
  begin
    if rising_edge(clk125) then
      if (rst_n = '0') then
@@ -296,7 +513,7 @@ begin

  gen_ttl_pulse_generators: for i in 1 to g_nr_ttl_chan generate
    -- Output pulse generators
-    cmp_ttl_pulse_gen: pulse_generator
+    cmp_ttl_pulse_gen : pulse_generator
      generic map
      (
        g_pulse_width     => 125,
@@ -306,13 +523,14 @@ begin
      (
        clk_i        => clk125,
        rst_n_i      => rst_n,
+        en_i         => '1',
        pulse_type_i => extra_switch_n_i(1),
        trig_i       => trig(i),
        pulse_o      => pulse_outputs(i)
      );

    -- Status LED pulse generators
-    cmp_led_pulse_gen: pulse_generator
+    cmp_led_pulse_gen : pulse_generator
      generic map
      (
        g_pulse_width     => 12*(10**6),
@@ -322,6 +540,7 @@ begin
      (
        clk_i        => clk125,
        rst_n_i      => rst_n,
+        en_i         => '1',
        pulse_type_i => extra_switch_n_i(1),
        trig_i       => trig(i),
        pulse_o      => pulse_leds(i)
@@ -334,9 +553,9 @@ begin
  
  -- Pulse status LED output assignments
  pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else 
-                       (others => '0');
+                         (others => '0');
  pulse_rear_led_n_o  <= (not pulse_leds) when (blo_oe = '1') else 
-                       (others => '0');
+                         (others => '0');

  --============================================================================
  -- Inverted TTL pulse generation logic
@@ -346,8 +565,8 @@ begin
              inv_in_n_i;
  
  -- Instantiate the necessary number of pulse generator components  
-  gen_inv_pulse_generators: for i in 1 to g_nr_inv_chan generate
-    cmp_inv_pulse_gen: pulse_generator
+  gen_inv_pulse_generators : for i in 1 to g_nr_inv_chan generate
+    cmp_inv_pulse_gen : pulse_generator
      generic map
      (
        g_pulse_width     => 125,
@@ -358,6 +577,7 @@ begin
        clk_i        => clk125,
        rst_n_i      => rst_n,
        pulse_type_i => extra_switch_n_i(1),
+        en_i         => '1',
        trig_i       => trig_inv(i),
        pulse_o      => inv_outputs(i)
      );
@@ -366,7 +586,7 @@ begin
  -- Output assignment
  inv_out_o <= not inv_outputs;
  
--  cmp_tmp_pulse_gen: pulse_gen
+--  cmp_tmp_pulse_gen : pulse_gen
 --    generic map
 --    (
 --      g_pwidth => 100,
@@ -405,7 +625,8 @@ begin


  -- I2C valid
-  bicolor_led_state(13 downto 12) <= c_LED_OFF;
+  bicolor_led_state(13 downto 12) <= c_LED_GREEN when (i2c_up = '1') else
+                                     c_LED_RED;

  -- State of TTL/TTL_N switch
  bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
@@ -424,7 +645,7 @@ begin
  -- MULTICAST 3
  bicolor_led_state(23 downto 22) <= c_LED_OFF;

-  cmp_bicolor_led_ctrl: bicolor_led_ctrl
+  cmp_bicolor_led_ctrli : bicolor_led_ctrl
    generic map
    (
      g_NB_COLUMN    => 6,
@@ -436,7 +657,7 @@ begin
    (
      clk_i           => clk125,
      rst_n_i         => rst_n,
-      led_intensity_i => "0011111",
+      led_intensity_i => "1111111",
      led_state_i     => bicolor_led_state,
      column_o(0)     => led_wr_ownaddr_i2c_o,
      column_o(1)     => led_wr_gmt_ttl_ttln_o,
@@ -456,7 +677,7 @@ begin
  rtmm <= not fpga_rtmm_n_i;
  rtmp <= not fpga_rtmp_n_i;

-  cmp_rtm_detector: rtm_detector
+  cmp_rtm_detector : rtm_detector
    port map
    (
      rtmm_i    => rtmm,

--- a/hdl/reset_gen/rtl/reset_gen.vhd
+++ b/hdl/reset_gen/rtl/reset_gen.vhd
@@ -54,6 +54,7 @@ entity reset_gen is
  port
  (
    clk_i   : in  std_logic;
+    rst_i   : in  std_logic;
    rst_n_o : out std_logic
  );
 end entity reset_gen;
@@ -91,7 +92,10 @@ begin
  p_rst_gen: process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if (cnt_en = '1') then
+      if (rst_i = '1') then
+        cnt_en  <= '1';
+        cnt     <= (others => '0');
+      elsif (cnt_en = '1') then
        rst_n_o <= '0';
        cnt     <= cnt + 1;
        if (cnt = g_reset_time) then

--- a/hdl/vme64x_i2c/Manifest.py
+++ b/hdl/vme64x_i2c/Manifest.py
+modules = {"local" : "rtl" }