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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
a485a730
Commit
a485a730
authored
Sep 27, 2018
by
Denia Bouhired-Ferrag
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minor stylistic changes. Commits golden and release projects
parent
ccc33882
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2 changed files
with
105 additions
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106 deletions
+105
-106
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+15
-17
conv_ttl_blo.vhd
top/Golden/conv_ttl_blo.vhd
+90
-89
No files found.
syn/Release/conv_ttl_blo.xise
View file @
a485a730
...
...
@@ -115,7 +115,7 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"19"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
@@ -123,11 +123,11 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
@@ -513,7 +513,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"22"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"36"
/>
...
...
@@ -541,10 +541,7 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"37"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"21"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
xil_pn:type=
"FILE_VHDL"
/>
<file
xil_pn:name=
"../../sim/Release/fastevent_counter_tb.vhd"
xil_pn:type=
"FILE_VHDL"
/>
<file
xil_pn:name=
"chipscope_ila.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -649,9 +646,9 @@
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Filter Files From Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Flatten Output Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language ArchWiz"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Coregen"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Schematic"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language ArchWiz"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Coregen"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Schematic"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GTS Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GWE Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"5"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Architecture Only (No Entity Declaration)"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -692,7 +689,7 @@
<property
xil_pn:name=
"Include sdf_annotate task in Verilog File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Incremental Compilation"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Insert Buffers to Prevent Pulse Swallowing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Instantiation Template Target Language Xps"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Instantiation Template Target Language Xps"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TCK"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDI"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDO"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
...
...
@@ -779,10 +776,11 @@
<property
xil_pn:name=
"Power Reduction Map spartan6"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Xst"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"V
HDL"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"V
erilog"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Process window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Generator"
xil_pn:value=
"ProjNav"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
...
...
@@ -821,8 +819,8 @@
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/
conv_burst_ctrl
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
conv_burst_ctrl
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/
testbench
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
testbench
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -833,7 +831,7 @@
<property
xil_pn:name=
"Shift Register Minimum Size spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Show All Models"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Signal window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Simulation Resolution"
xil_pn:value=
"Default (1 ps)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time ISim"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Map"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
...
...
@@ -845,7 +843,7 @@
<property
xil_pn:name=
"Source window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
conv_burst_ctrl
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
testbench
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
...
...
top/Golden/conv_ttl_blo.vhd
View file @
a485a730
...
...
@@ -156,7 +156,7 @@ architecture arch of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Number of repetition channels
constant
c_
nr_chans
:
integer
:
=
6
;
constant
c_
NR_CHANS
:
integer
:
=
6
;
constant
c_nr_inv_chans
:
integer
:
=
4
;
-- Number of bicolor LED lines & columns
...
...
@@ -176,7 +176,7 @@ architecture arch of conv_ttl_blo is
type
t_ttlbar_nosig_cnt
is
array
(
c_nr_chans
-1
downto
0
)
of
unsigned
(
10
downto
0
);
--
Array of constants for temperature model implemented for long long mode
--
Array of constants for temperature model implemented for long long mode
type
t_temp_decre_step_lg
is
array
(
0
to
14
)
of
integer
;
--============================================================================
...
...
@@ -197,7 +197,7 @@ architecture arch of conv_ttl_blo is
signal
inhibit_first_pulse_d0
:
std_logic
;
signal
inhibit_cnt
:
unsigned
(
10
downto
0
);
--Temperature model constantstemp_decre_step_lg
--
Temperature model constantstemp_decre_step_lg
signal
temp_decre_step_lg
:
t_temp_decre_step
;
signal
temp_decre_step_sh
:
t_temp_decre_step
;
...
...
@@ -305,10 +305,10 @@ begin
inhibit_first_pulse_d0
<=
inhibit_first_pulse
;
end
if
;
end
if
;
end
process
;
end
process
p_inhibit_first_pulse_d0
;
-- Pulse input valid only after inhibit period is over
pulse_in
<=
(
pulse_ttl
or
pulse_blo
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
pulse_in
<=
pulse_ttl
or
pulse_blo
when
(
inhibit_first_pulse_d0
=
'0'
)
else
(
others
=>
'0'
);
-- Line inputs for reflection in status register
...
...
@@ -325,14 +325,14 @@ begin
burst_en_n
<=
'0'
when
pcbrev_i
(
5
downto
0
)
>=
"010000"
else
'1'
;
--*******************************************************************************
--*******************************************************************************
--
*******************************************************************************
--
*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--
*******************************************************************************
--
*******************************************************************************
--
*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
...
...
@@ -360,6 +360,7 @@ begin
g_bicolor_led_columns
=>
c_bicolor_led_cols
,
g_bicolor_led_lines
=>
c_bicolor_led_lines
)
port
map
(
-- Clocks
...
...
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