Commit ad800f0c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Clean up of ./syn folder

parent b4f182b5
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>
#*****************************************************************
# C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg
# Tue Sep 06 17:17:54 2016
#
# Important :-
# All options/variables must start from first column
#
#*****************************************************************
#
RELEASE_VERSION:14.7
#
RELEASE_BUILD:P.20131013
#
# set current simulator name
SIMULATOR_NAME:mti_se
#
# set current language name
LANGUAGE_NAME:all
#
# set compilation execution mode
EXECUTE:on
#
# print compilation command template in log file
LOG_CMD_TEMPLATE:off
#
# Hierarchical Output Directories
HIER_OUT_DIR:off
#
# print Pre-Compiled library info
PRECOMPILED_INFO:on
#
# create backup copy of setup files
BACKUP_SETUP_FILES:on
#
# use enhanced compilation techniques for faster library compilation
# (applicable to selected libraries only)
FAST_COMPILE:on
#
# save compilation results to log file with the name specified with -log option
ADD_COMPILATION_RESULTS_TO_LOG:on
#
# abort compilation process if errors are detected in the library
ABORT_ON_ERROR:off
#
# compile library in the directory specified by the environment variable if the
# -dir option is not specified
OUTPUT_DIR_ENV:
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim SE
SET:mti_se:MODELSIM=modelsim.ini
#
# ModelSim SE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_se:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:r:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:i:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim SE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_se:verilog:u:-source -novopt
OPTION:mti_se:verilog:s:-source -novopt
OPTION:mti_se:verilog:n:-source -novopt
OPTION:mti_se:verilog:c:-source -novopt
OPTION:mti_se:verilog:r:-source -novopt
OPTION:mti_se:verilog:i:-source -novopt
OPTION:mti_se:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim PE
SET:mti_pe:MODELSIM=modelsim.ini
#
# ModelSim PE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:vhdl:u:-source -93 -explicit
OPTION:mti_pe:vhdl:s:-source -93 -explicit
OPTION:mti_pe:vhdl:c:-source -93 -explicit
OPTION:mti_pe:vhdl:r:-source -93 -explicit
OPTION:mti_pe:vhdl:i:-source -93 -explicit
OPTION:mti_pe:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim PE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:verilog:u:-source
OPTION:mti_pe:verilog:s:-source
OPTION:mti_pe:verilog:n:-source
OPTION:mti_pe:verilog:c:-source
OPTION:mti_pe:verilog:r:-source
OPTION:mti_pe:verilog:i:-source
OPTION:mti_pe:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim DE
SET:mti_de:MODELSIM=modelsim.ini
#
# ModelSim DE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_de:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:r:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:i:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim DE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_de:verilog:u:-source -novopt
OPTION:mti_de:verilog:s:-source -novopt
OPTION:mti_de:verilog:n:-source -novopt
OPTION:mti_de:verilog:c:-source -novopt
OPTION:mti_de:verilog:r:-source -novopt
OPTION:mti_de:verilog:i:-source -novopt
OPTION:mti_de:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: QuestaSim
SET:questasim:MODELSIM=modelsim.ini
#
# QuestaSim options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:questasim:vhdl:u:-source -93 -novopt -explicit
OPTION:questasim:vhdl:s:-source -93 -novopt -explicit
OPTION:questasim:vhdl:c:-source -93 -novopt -explicit
OPTION:questasim:vhdl:r:-source -93 -novopt -explicit
OPTION:questasim:vhdl:i:-source -93 -novopt -explicit
OPTION:questasim:vhdl:e:-93 -novopt -quiet -explicit
#
# QuestaSim options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:questasim:verilog:u:-source -novopt
OPTION:questasim:verilog:s:-source -novopt
OPTION:questasim:verilog:n:-source -novopt
OPTION:questasim:verilog:c:-source -novopt
OPTION:questasim:verilog:r:-source -novopt
OPTION:questasim:verilog:i:-source -novopt
OPTION:questasim:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: Aldec
SET:riviera:LIBRARY=library.cfg
#
# Aldec options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:riviera:vhdl:u:-93
OPTION:riviera:vhdl:s:-93
OPTION:riviera:vhdl:c:-93
OPTION:riviera:vhdl:r:-93
OPTION:riviera:vhdl:i:-93
OPTION:riviera:vhdl:e:-93
#
# Aldec options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:riviera:verilog:u:-v2k5
OPTION:riviera:verilog:s:-v2k5
OPTION:riviera:verilog:n:-v2k5
OPTION:riviera:verilog:c:-v2k5
OPTION:riviera:verilog:r:-v2k5
OPTION:riviera:verilog:i:-v2k5
OPTION:riviera:verilog:e:-v2k5
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: Aldec
SET:active_hdl:LIBRARY=library.cfg
#
# Aldec options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:active_hdl:vhdl:u:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:s:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:c:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:r:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:i:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:e:-93 -quiet -nowarn ELAB1_0026
#
# Aldec options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:active_hdl:verilog:u:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:s:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:n:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:c:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:r:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:i:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:e:-v2k5 -quiet -msg 0
#///////////////////////////////////////////////////////////////////////
# End
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\genrams\genram_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gencores_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gc_sync_ffs.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_burst_ctrl.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
verilog work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
######################################################################
##
## Filename: conv_dyn_burst_ctrl.udo
## Created on: Mon Oct 17 17:16:31 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
######################################################################
##
## Filename: conv_dyn_burst_ctrl_wave.fdo
## Created on: Mon Oct 17 17:16:32 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
This diff is collapsed.
This diff is collapsed.
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>conv_ttl_blo Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc7vx330t-3ffg1157</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 10/19/2016 - 15:21:53</center>
</BODY></HTML>
\ No newline at end of file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
-intstyle "ise" -incremental -rangecheck -lib "secureip" -o "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_isim_beh.exe" -prj "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_beh.prj" "work.testbench"
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######################################################################
##
## Filename: testbench.udo
## Created on: Tue Sep 06 16:30:52 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
This diff is collapsed.
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>conv_ttl_blo Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New (Failed)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\testbench_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 7. Feb 16:41:32 2017</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/13/2017 - 18:37:49</center>
</BODY></HTML>
\ No newline at end of file
######################################################################
##
## Filename: testbench_wave.fdo
## Created on: Tue Sep 06 17:26:22 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
#add wave /glbl/GSR
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