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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
ad80ca56
Commit
ad80ca56
authored
Mar 03, 2017
by
Denia Bouhired-Ferrag
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Changed top file to use periods instead of duty cycles, same changes in conv_common_gw
parent
1d502af8
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2 changed files
with
15 additions
and
11 deletions
+15
-11
conv-common-gw
ip_cores/conv-common-gw
+1
-1
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+14
-10
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conv-common-gw
@
011fbe69
Subproject commit
c2306023e6d051792806e5ac4eafa9ed05a0da53
Subproject commit
011fbe699bd86cfa0529fcef16d9c28ab61172ef
top/Release/conv_ttl_blo.vhd
View file @
ad80ca56
...
...
@@ -317,6 +317,10 @@ begin
end
if
;
end
if
;
end
process
;
-- Pulse input valid only after inhibit period is over
pulse_in
<=
(
pulse_ttl
or
pulse_blo
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
...
...
@@ -340,13 +344,13 @@ begin
-- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n
<=
'0'
when
pcbrev_i
(
5
downto
0
)
>=
"010000"
else
'1'
;
--
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
--
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
--
else '1';
burst_en_n
<=
'0'
when
sw_gp_n_i
(
6
)
=
'0'
else
'1'
;
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
...
...
@@ -363,11 +367,11 @@ begin
g_pgen_fixed_width
=>
true
,
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_sh
=>
5
,
g_pgen_
duty_cycle_div_cont
=>
2
00
,
-- Minimum
duty cycle
supported for 1.2us pulse ~ max freq 104kHz
g_pgen_
duty_cycle_div_lg
=>
8
,
-- Minimum
duty cycle supo
ported for 250ns pulse ~ max freq 2MHz
g_pgen_
duty_cycle_div_sh
=>
2
,
g_pgen_
pperiod_cont
=>
48
00
,
-- Minimum
period
supported for 1.2us pulse ~ max freq 104kHz
g_pgen_
pperiod_lg
=>
191
,
-- Minimum
period sup
ported for 250ns pulse ~ max freq 2MHz
g_pgen_
pperiod_sh
=>
9
,
g_pgen_gf_len
=>
1
,
g_temp_decre_step_lg
=>
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
2500
,
731
,
220
,
250
,
40
,
85
,
50
,
125
),
g_temp_decre_step_sh
=>
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
),
...
...
@@ -411,6 +415,8 @@ begin
-- Front panel channels
pulse_i
=>
pulse_in
,
pulse_ttl_i
=>
pulse_ttl
,
pulse_blo_i
=>
pulse_blo
,
pulse_o
=>
pulse_out
,
-- Inverted pulse I/O
...
...
@@ -511,9 +517,7 @@ begin
-----------------------------------------
-- LED outputs
led_front_n_o
<=
not
led_pulse
;
--led_front_n_o <= "101010";
led_front_inv_n_o
<=
not
led_inv_pulse
;
--led_front_inv_n_o <= "1010";
led_rear_n_o
<=
not
led_pulse
;
...
...
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