Commit cdf4abc8 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Modified design testbench and conv-common-gw repo

parent 6fb3ac09
conv-common-gw @ b935312b
Subproject commit 897b7d21886e394a27e3f90ab3c5f355614cd9f3
Subproject commit b935312b9a6c9c99aef37bc3a375f6ddb81f1d64
......@@ -333,10 +333,10 @@ begin
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for c_clk_20_per/2;
clk_20 <= '1';
wait for c_clk_20_per/2;
clk_20 <= '0';
wait for c_clk_20_per/2;
end process;
p_clk_125 : process
......@@ -354,12 +354,7 @@ begin
-- Instantiate the DUT
--============================================================================
cmp_dut : conv_ttl_blo
-- generic map
-- (
-- g_nr_ttl_chan => 6,
-- g_nr_inv_chan => 4,
-- g_sim => true
-- )
port map
(
-- Clocks
......@@ -478,10 +473,10 @@ begin
--ttl_switch_n <= '0';
switches_n(7) <= '0';
-- GF
switches_n(0) <= '0';
switches_n(0) <= '1';
--burst mode is 0 else 1 for normal operation
switches_n(1) <='0';
switches_n(1) <= '0';
-- other
......@@ -533,12 +528,13 @@ end process p_ran_gen;
blo_inp(6 downto 1) <= (others => '0'); ---DB new line to remove all blo stimulus
wait until inv_flag_n = true;
while (inv_flag_n = true) loop
interval := rand_num * 1 ns;
--interval := rand_num * 1 ns;
interval := 250 ns;
--for j in 6 downto 1 loop
ttl_inp_n(1) <= '1';
wait for interval;
ttl_inp_n(1) <= '0';
wait for 200 ns;
wait for 250 ns;
ttl_inp_n(1) <= '1';
if ttl_outp(1) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
......@@ -578,6 +574,7 @@ end process p_ran_gen;
-- end if;
end loop;
end loop;
end process p_stim_pulse;
process
......
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