small modifs to burst controller testbench

ce0a347a · Denia Bouhired-Ferrag · 89f1378b · ce0a347a
Commit ce0a347a authored Jan 16, 2017 by Denia Bouhired-Ferrag
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Showing with 7 additions and 6 deletions

burst_ctrl_tb.vhd sim/Release/burst_ctrl_tb.vhd +7 -6

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--- a/sim/Release/burst_ctrl_tb.vhd
+++ b/sim/Release/burst_ctrl_tb.vhd
@@ -89,7 +89,7 @@ architecture behav of testbench is
 	generic
 	(
 		g_pwidth : natural range 2 to 40 	:= 5; 
-		g_1_pulse_temp_rise			:in unsigned (15 downto 0);
+		g_1_pulse_temp_rise			:in unsigned (19		downto 0);
 		g_max_temp			:in unsigned (39 downto 0) 
 	);
 	port
@@ -166,8 +166,9 @@ architecture behav of testbench is
  cmp_dut_2 : conv_dyn_burst_ctrl
  generic map
  (
-  g_pwidth 					=> 5, 
-  g_1_pulse_temp_rise			=> x"1388",
+  g_pwidth 					=> 5, --
+  g_1_pulse_temp_rise			=> x"01388",
+  --g_1_pulse_temp_rise			=> x"23040", - for 1.2us pulse
  --g_1_pulse_temp_rise			=> x"7A125",
  --g_max_temp			=> x"00000F4240" --10^6
 
@@ -250,12 +251,12 @@ end process p_ran_gen;
 			interval := 250 ns;
 		end if;
 	else	
-		interval := 250 ns;
+		interval := 1600 ns;--changes pulse frequency
 	end if;
 	burst_train <= '0';
 	wait for interval;
 	burst_train <= '1';
-	wait for 250 ns;
+	wait for 250 ns;-- changes pulse width
 	burst_train <= '0';
  end loop;  
   
@@ -264,7 +265,7 @@ end process p_ran_gen;
 	if random_intervals then
 		interval := rand_num * 1 ns;
 	else	
-		interval := 5000 ns;
+		interval := 1750 ns;
 	end if;
 	burst_train <= '0';
 	wait for interval;