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Conv TTL Blocking - Gateware
Commit d30bb5f9 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Code cleanup and operational tests performed, basic pulse repetition working.

parent 26f027ea
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Showing with 81 additions and 67 deletions
hdl/IMAGES/image1/project/image1.xise
View file @ d30bb5f9
......@@ -17,31 +17,31 @@
<files>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
......@@ -69,11 +69,11 @@
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
......@@ -81,7 +81,7 @@
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
......@@ -93,7 +93,7 @@
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -125,7 +125,7 @@
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -137,15 +137,15 @@
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
......@@ -153,7 +153,7 @@
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
......@@ -186,7 +186,7 @@
</file>
<file xil_pn:name="../rtl/statregs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
</files>
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ d30bb5f9
......@@ -43,7 +43,6 @@ use work.wishbone_pkg.ALL;
use work.i2c_slave_pkg.ALL;
use work.m25p32_pkg.ALL;
use work.multiboot_pkg.ALL;
use work.rtm_detector_pkg.ALL;
package image1_pkg is
......
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ d30bb5f9
......@@ -9,12 +9,30 @@
--
-- version: 1.0
--
-- description:
-- description:
-- This module generates a variable-width pulse. The width is set using the
-- g_pulse_width generic, given in number of clk_i cycles. Assuming a clk_i
-- period of 8ns, the output pulse width is by default 8*16=128ns.
--
-- The pulse_o signal is generated by multiplexing the input trigger and
-- the internally-generated pulse. When the trigger is detected, it is
-- immediately passed to the output in order to avoid jitter.
--
-- The trigger then passes through a variable-length glitch filter consisting
-- of N flip-flops, where N is set via g_glitch_flit_len. Once the trigger
-- has settled to '1' and the glitch filter is all ones, the internal pulse
-- signal takes over, extending the input pulse up to g_pulse_width.
--
-- Selection between trigger input and internal pulse signal routing to the
-- output is done by an internal pulse rejection signal, which is set once
-- the internal pulse generation mechanism has started, and cleared when
-- the trigger input has settled to zero. This signal assures that trigger
-- signals no greater than the desired pulse width appear at the input, thus
-- safeguarding the output transformers on the blocking pulse.
--
-- dependencies:
-- none
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
......@@ -41,14 +59,23 @@ use ieee.numeric_std.all;
entity pulse_generator is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
-- Length of glitch filter; the longer the glitch filter, the
-- longer the input trigger needs to be.
g_glitch_filt_len : natural := 6
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
pulse_o : out std_logic
);
end entity pulse_generator;
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ d30bb5f9
......@@ -104,13 +104,10 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362750559" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1362750547">
<transform xil_pn:end_ts="1363002038" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363002026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.lso"/>
......@@ -128,20 +125,18 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362750565" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1362750559">
<transform xil_pn:end_ts="1363002044" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363002038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bld"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362750592" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362750565">
<transform xil_pn:end_ts="1363002072" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363002044">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -154,10 +149,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1362750623" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362750592">
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363002072">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pad"/>
......@@ -169,10 +163,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362750641" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362750623">
<transform xil_pn:end_ts="1363002118" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363002100">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bit"/>
......@@ -184,23 +177,24 @@
<transform xil_pn:end_ts="1362751327" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-4173336264699367391" xil_pn:start_ts="1362751327">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1362750641" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1362750641">
<transform xil_pn:end_ts="1363002119" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363002118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1362750623" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362750614">
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363002093">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twr"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twx"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ d30bb5f9
......@@ -346,10 +346,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
......@@ -362,7 +362,7 @@
</file>
<file xil_pn:name="../../old_rep_test/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ d30bb5f9
......@@ -360,18 +360,18 @@ begin
-- Output assignment
INV_OUT <= not inv_outputs;
cmp_tmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 100,
g_freq => 125*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_o => tmp_pulse
);
-- cmp_tmp_pulse_gen: pulse_gen
-- generic map
-- (
-- g_pwidth => 100,
-- g_freq => 125*(10**6)
-- )
-- port map
-- (
-- clk_i => clk_125,
-- rst_n_i => rst_n,
-- pulse_o => tmp_pulse
-- );
--============================================================================
-- Bicolor LED matrix logic
......
hdl/reset_gen/rtl/reset_gen.vhd
View file @ d30bb5f9
......@@ -10,10 +10,16 @@
-- version: 1.0
--
-- description:
-- This module generates a variable-width reset pulse. The width of the pulse
-- is set via the g_reset_time pulse; an internal counter counts up to this
-- value and de-asserts the active-low reset line when the value has been
-- reached. At the same time, the module is de-activated.
--
-- dependencies:
-- By default, a 125 MHz clock is assumed (8ns period), resulting in a 96ms
-- reset width.
--
-- references:
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
......
hdl/rtm_detector/rtl/rtm_detector.vhd
View file @ d30bb5f9
......@@ -80,7 +80,6 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use work.rtm_detector_pkg.ALL;
entity rtm_detector is
port
......@@ -94,20 +93,9 @@ end entity rtm_detector;
architecture Behavioral of rtm_detector is
-- signal s_identifier_rtmm : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmm);
-- signal s_identifier_rtmp : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmp);
-- signal s_rtmm : unsigned(2 downto 0);
-- signal s_rtmp : unsigned(2 downto 0);
begin
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
-- s_rtmm <= unsigned(rtmm_i);
-- s_rtmp <= unsigned(rtmp_i);
--
-- ok_rtmm_o <= '1' when s_rtmm = s_identifier_rtmm else '0';
-- ok_rtmp_o <= '1' when s_rtmp = s_identifier_rtmp else '0';
end Behavioral;
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