Added old repeater boards' test. New project folder hierarchy started, as…

Added old repeater boards' test. New project folder hierarchy started, as exemplified in old_rep_test/ folder.

Added old repeater boards' test. New project folder hierarchy started, as…
Added old repeater boards' test. New project folder hierarchy started, as exemplified in old_rep_test/ folder.
d428cec8 · Theodor-Adrian Stana · 456634b1 · d428cec8 · d428cec8 · d428cec8
Commit d428cec8 authored Feb 28, 2013 by Theodor-Adrian Stana
18 changed files
--- a/hdl/old_rep_test/README.txt
+++ b/hdl/old_rep_test/README.txt
+This project is used to generate variable-length pulses for testing the old
+repeater boards.
--- a/hdl/old_rep_test/rtl/Manifest.py
+++ b/hdl/old_rep_test/rtl/Manifest.py
+files = [
+      "pulse_gen.vhd"
+    ]
--- a/hdl/old_rep_test/rtl/pulse_gen.vhd
+++ b/hdl/old_rep_test/rtl/pulse_gen.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Test module for old repeater boards
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity pulse_gen is
+  generic
+  (
+    g_pwidth : natural := 200;
+    g_freq   : natural := 400
+  );
+  port
+  (
+    clk_i   : in  std_logic;
+    rst_i   : in  std_logic;
+    pulse_o : out std_logic
+  );
+end entity pulse_gen;
+
+
+architecture behav of pulse_gen is
+
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+
+  --============================================================================
+  -- Function and procedure declarations
+  --============================================================================
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal freq_cnt  : unsigned(f_log2_size(g_freq)-1 downto 0);
+  signal pulse     : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- I/O logic
+  --============================================================================
+  pulse_o <= pulse;
+
+  p_gen_pulse: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_i = '1') then
+        freq_cnt  <= (others => '0');
+        pulse     <= '0';
+      else
+        freq_cnt <= freq_cnt + 1;
+        pulse    <= '0';
+        if (freq_cnt < g_pwidth) then
+          pulse  <= '1';
+        elsif (freq_cnt = g_freq-1) then
+          freq_cnt <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process p_gen_pulse;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/old_rep_test/sim/Makefile
+++ b/hdl/old_rep_test/sim/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+## variables #############################
+PWD := $(shell pwd)
+
+MODELSIM_INI_PATH := /opt/modelsim_10.0d/modeltech
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini
+VSIM_FLAGS :=
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../rtl/old_rep_test.vhd \
+testbench.vhd \
+
+VHDL_OBJ := work/old_rep_test/.old_rep_test_vhd \
+work/testbench/.testbench_vhd \
+
+LIBS := work
+LIB_IND := work/.work
+## rules #################################
+sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): $(VHDL_OBJ) 
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< .
+clean:
+		rm -rf ./modelsim.ini $(LIBS)
+.PHONY: clean
+
+work/.work:
+	(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work 
+
+
+work/old_rep_test/.old_rep_test_vhd: ../rtl/old_rep_test.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/testbench/.testbench_vhd: testbench.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
--- a/hdl/old_rep_test/sim/Manifest.py
+++ b/hdl/old_rep_test/sim/Manifest.py
+target = "xilinx"
+action = "simulation"
+
+files = [
+      "../rtl/old_rep_test.vhd",
+      "testbench.vhd"
+    ];
--- a/hdl/old_rep_test/sim/run.do
+++ b/hdl/old_rep_test/sim/run.do
+vlib work
+
+vcom -explicit -93 "../rtl/old_rep_test.vhd"
+vcom -explicit -93 "testbench.vhd"
+
+vsim -voptargs="+acc" -lib work work.testbench
+
+# log -r /*
+
+radix -hexadecimal
+# add wave *
+do wave.do
+
+run 100 us
+wave zoomfull
--- a/hdl/old_rep_test/sim/testbench.vhd
+++ b/hdl/old_rep_test/sim/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for old repeater design
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 10 ns;
+  constant c_reset_width : time := 31 ns;
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+
+  component old_rep_test is
+    generic
+    (
+      g_pwidth : natural := 200;
+      g_freq   : natural := 200000000
+    );
+    port
+    (
+      clk_i   : in  std_logic;
+      rst_i   : in  std_logic;
+      pulse_o : out std_logic
+    );
+  end component old_rep_test;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk, rst, pulse : std_logic := '0';
+
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  DUT: old_rep_test
+  generic map
+  (
+    g_pwidth => 1,
+    g_freq   => 13 
+  )
+  port map
+  (
+    clk_i   => clk,
+    rst_i   => rst,
+    pulse_o => pulse
+  );
+
+  p_clk: process
+  begin
+    clk <= not clk;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+  p_rst: process
+  begin
+    rst <= '1';
+    wait for c_reset_width;
+    rst <= '0';
+    wait;
+  end process p_rst;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/old_rep_test/sim/transcript
+++ b/hdl/old_rep_test/sim/transcript
--- a/hdl/old_rep_test/sim/wave.do
+++ b/hdl/old_rep_test/sim/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/rst
+add wave -noupdate /testbench/pulse
+add wave -noupdate -divider internal
+add wave -noupdate /testbench/DUT/pulse_cnt
+add wave -noupdate /testbench/DUT/pulse
+add wave -noupdate /testbench/DUT/freq_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {40 ns} 0}
+configure wave -namecolwidth 194
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {18484 ns} {20080 ns}
--- a/hdl/old_rep_test/syn/Makefile
+++ b/hdl/old_rep_test/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := conv_ttl_blo_v2.xise
+ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+USER:=$(HDLMAKE_USER)#take the value from the environment
+SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
+R_NAME:=conv_ttl_blo_v2
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../rtl/pulse_gen.vhd \
+../top/conv_ttl_blo_v2.ucf \
+../top/conv_ttl_blo_v2.vhd \
+run.tcl \
+conv_ttl_blo_v2.xise
+
+#target for running simulation in the remote location
+remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
+
+__send_back: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
--- a/hdl/old_rep_test/syn/Manifest.py
+++ b/hdl/old_rep_test/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "conv_ttl_blo_v2"
+syn_project = "conv_ttl_blo_v2.xise"
+
+modules = {
+    "local" : [
+      "../rtl",
+      "../top"
+      ]
+    }
--- a/hdl/old_rep_test/syn/conv_ttl_blo_v2.bit
+++ b/hdl/old_rep_test/syn/conv_ttl_blo_v2.bit
--- a/hdl/old_rep_test/syn/conv_ttl_blo_v2.xise
+++ b/hdl/old_rep_test/syn/conv_ttl_blo_v2.xise
--- a/hdl/old_rep_test/syn/old_rep_test.ppr
+++ b/hdl/old_rep_test/syn/old_rep_test.ppr
+<?xml version="1.0"?>
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="bcf2b3838fb34eacb774368959fa1ec4"/>
+		<Option Name="Part" Val="xc6slx45tfgg484-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
+		<Option Name="TargetLanguage" Val="VHDL"/>
+		<Option Name="TargetSimulator" Val="ModelSim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+		<Option Name="ActiveSimSet" Val=""/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
--- a/hdl/old_rep_test/syn/run.tcl
+++ b/hdl/old_rep_test/syn/run.tcl
+project open conv_ttl_blo_v2.xise
+process run {Generate Programming File} -force rerun_all
--- a/hdl/old_rep_test/top/Manifest.py
+++ b/hdl/old_rep_test/top/Manifest.py
+files = [
+      "conv_ttl_blo_v2.ucf",
+      "conv_ttl_blo_v2.vhd"
+    ]
--- a/hdl/old_rep_test/top/conv_ttl_blo_v2.ucf
+++ b/hdl/old_rep_test/top/conv_ttl_blo_v2.ucf
--- a/hdl/old_rep_test/top/conv_ttl_blo_v2.vhd
+++ b/hdl/old_rep_test/top/conv_ttl_blo_v2.vhd