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C
Conv TTL Blocking - Gateware
Commit e7a81942 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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made vbcp accept more than one word

parent f362dfd4
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Showing with 32 additions and 21 deletions
doc/i2c_slave/i2c_slave.tex
View file @ e7a81942
...@@ -264,8 +264,8 @@ in the transfer, setting the \textit{done\_p\_o} output for one clock cycle afte ...@@ -264,8 +264,8 @@ in the transfer, setting the \textit{done\_p\_o} output for one clock cycle afte
received/sent byte. The \textit{stat\_o} output can be checked to see if the byte has been received/sent byte. The \textit{stat\_o} output can be checked to see if the byte has been
sent/received correctly. sent/received correctly.
The \textit{done\_p\_o} set high after every completed transfer can be polled periodically and When the cycle-wide \textit{done\_p\_o} output is high (after every successful transfer, or a
when high, the \textit{stat\_o} (possibly together with the \textit{op\_o}) output can be checked stop condition) the \textit{stat\_o} (possibly together with the \textit{op\_o}) output can be checked
to see the appropriate action to be taken. The various statuses possible at the to see the appropriate action to be taken. The various statuses possible at the
\textit{stat\_o} output are listed in Table~\ref{tbl:stat}. \textit{stat\_o} output are listed in Table~\ref{tbl:stat}.
...@@ -278,7 +278,8 @@ to see the appropriate action to be taken. The various statuses possible at the ...@@ -278,7 +278,8 @@ to see the appropriate action to be taken. The various statuses possible at the
\hline \hline
\multicolumn{1}{c}{\textbf{\textit{stat\_o}}} & \multicolumn{1}{c}{\textbf{Description}} \\ \multicolumn{1}{c}{\textbf{\textit{stat\_o}}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline \hline
00 & Slave idle, waiting for start condition \\ 00 & Slave idle, waiting for start condition. This is the state upon startup and after the I$^2$C stop
condition is received \\
01 & Address sent by the master matches that at \textit{i2c\_addr\_i}; \textit{op\_o} 01 & Address sent by the master matches that at \textit{i2c\_addr\_i}; \textit{op\_o}
valid \\ valid \\
10 & Read done, waiting for ACK/NACK to send to master \\ 10 & Read done, waiting for ACK/NACK to send to master \\
...@@ -318,6 +319,8 @@ The steps below should be followed when reading one or more bytes sent by the ma ...@@ -318,6 +319,8 @@ The steps below should be followed when reading one or more bytes sent by the ma
\textit{rx\_byte\_o} and write a '0' at \textit{ack\_n\_i} to send an ACK, or a \textit{rx\_byte\_o} and write a '0' at \textit{ack\_n\_i} to send an ACK, or a
'1' to send an NACK. '1' to send an NACK.
\item The transfer is repeated until the master sends a stop condition. \item The transfer is repeated until the master sends a stop condition.
\item After the stop condition is received, the \textit{done\_p\_o} goes high for one
clock cycle and the status is set to "00".
\end{enumerate} \end{enumerate}
\subsection{Write mode} \subsection{Write mode}
...@@ -345,10 +348,12 @@ The steps below should be followed when writing one or more bytes to a master: ...@@ -345,10 +348,12 @@ The steps below should be followed when writing one or more bytes to a master:
will send a stop condition, so the \textit{i2c\_slave} module is reset. will send a stop condition, so the \textit{i2c\_slave} module is reset.
\end{enumerate} \end{enumerate}
Note that if a stop condition is received from the master, the \textit{done\_p\_o} goes high for
one clock cycle and the status is set to "00".
%============================================================================== %==============================================================================
% SEC: Implementation % SEC: Implementation
%============================================================================== %==============================================================================
\pagebreak
\section{Implementation} \section{Implementation}
\label{sec:implem} \label{sec:implem}
......
hdl/test_regs/syn/conv_ttl_blo.gise
View file @ e7a81942
...@@ -72,34 +72,35 @@ ...@@ -72,34 +72,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670733" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471900" xil_pn:in_ck="9111352100311135339" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376471884"> <transform xil_pn:end_ts="1379670748" xil_pn:in_ck="9111352100311135339" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1379670733">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -117,11 +118,11 @@ ...@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471900" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376471900"> <transform xil_pn:end_ts="1379670748" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1379670748">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471911" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376471900"> <transform xil_pn:end_ts="1379670756" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1379670748">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -130,7 +131,7 @@ ...@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/> <outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1376471959" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376471911"> <transform xil_pn:end_ts="1379670803" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1379670756">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -143,7 +144,7 @@ ...@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1376472012" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376471959"> <transform xil_pn:end_ts="1379670851" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1379670803">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
...@@ -157,7 +158,7 @@ ...@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1376472048" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376472012"> <transform xil_pn:end_ts="1379670887" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1379670851">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -168,7 +169,7 @@ ...@@ -168,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1376472012" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376472000"> <transform xil_pn:end_ts="1379670851" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1379670841">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/vbcp_wb/rtl/i2c_slave.vhd
View file @ e7a81942
...@@ -294,6 +294,8 @@ begin ...@@ -294,6 +294,8 @@ begin
-- I2C stop condition -- I2C stop condition
elsif (sda_rising = '1') and (scl_degl = '1') then elsif (sda_rising = '1') and (scl_degl = '1') then
state <= ST_IDLE; state <= ST_IDLE;
done_p_o <= '1';
stat_o <= c_i2cs_idle;
-- state machine logic -- state machine logic
else else
......
hdl/vbcp_wb/rtl/vbcp_wb.vhd
View file @ e7a81942
...@@ -341,7 +341,7 @@ begin ...@@ -341,7 +341,7 @@ begin
state <= ST_SYSMON_WR_WB; state <= ST_SYSMON_WR_WB;
end if; end if;
else else
i2c_err <= '1'; --i2c_err <= '1';
state <= ST_IDLE; state <= ST_IDLE;
end if; end if;
end if; end if;
...@@ -356,10 +356,13 @@ begin ...@@ -356,10 +356,13 @@ begin
wb_cyc <= '1'; wb_cyc <= '1';
wb_stb <= '1'; wb_stb <= '1';
wb_we <= '1'; wb_we <= '1';
if (wb_ack = '1') or (wb_err = '1') then if (wb_ack = '1') then -- or (wb_err = '1') then
wb_cyc <= '0'; wb_cyc <= '0';
wb_stb <= '0'; wb_stb <= '0';
wb_we <= '0'; wb_we <= '0';
state <= ST_SYSMON_WR; --ST_IDLE;
elsif (wb_err = '1') then
i2c_err <= '1';
state <= ST_IDLE; state <= ST_IDLE;
end if; end if;
......
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