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Conv TTL Blocking - Gateware
Commit fbf25571 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Update top file with new minor release number, with minor changes to alignment… 

Update top file with new minor release number, with minor changes to alignment and port renaming. Added fascounter testbench and two svg figures to hdl guide
parent abb0a98b
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doc/gw-diff.svg 0 → 100644
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doc/hdlg/fig/ttl-inp_backup.svg 0 → 100644
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conv-common-gw @ 1fbe6c0a
Subproject commit 0bb46c7a72484bfd9ca81c4b23af9d17d04f03eb
Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
sim/Release/fastevent_counter_tb.vhd 0 → 100644
View file @ fbf25571
-- tester for fastevent counter.
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity fastevent_tb is end;
architecture test of fastevent_tb is
-- Minimum pulse width.
-- This is the shortest pulse that can be detected by a flipflop
-- Need to get real figure from device/library data sheet; look for
-- the minimum clock pulse width. NOT the same as maximum clock frequency.
-- About a nanosecond is probably in the ballpark.
constant width : time := 1 ns;
signal trig,
enable : std_logic := '0';
signal reset : std_logic := '0';
signal clk : std_logic;
signal count : std_logic_vector(7 downto 0);
signal stop : boolean;
begin
fastevent_counter_i :
entity work.fastevent_counter
port map (sysclk => clk,
rstcount => reset,
enable => enable,
trig => trig,
count => count);
clkgen : process begin
while not stop loop
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end loop;
wait;
end process;
-- process to generate some fast pulses for counter.
do_something : process
variable num : natural;
variable s1, s2: positive := 42;
impure function dist_uniform(min, max: integer) return integer is
variable r: real;
begin
uniform(s1, s2, r);
return min + integer(trunc(real(max+1-min) * r));
end;
procedure pulse (num : natural;
signal sig : out std_logic) is
variable gap : time;
begin
for I in 1 to num loop
sig <= '1';
wait for width;
sig <='0';
gap := 1 ns * dist_uniform(100, 200);
wait for gap;
end loop;
end procedure;
begin
wait for 10 ns;
enable <= '1';
wait until falling_edge(clk);
reset <= '1';
wait until falling_edge(clk);
reset <= '0';
wait until falling_edge(clk);
wait until rising_edge(clk);
num := dist_uniform(5, 10);
pulse(num, trig);
wait until falling_edge(clk);
assert (to_integer(unsigned(count)) = num) report "broken";
reset <= '1';
wait until falling_edge(clk);
reset <= '0';
wait until falling_edge(clk);
num := dist_uniform(5, 10);
pulse(num, trig);
wait until falling_edge(clk);
assert (to_integer(unsigned(count)) = num) report "broken";
pulse (1, trig);
wait until falling_edge(clk);
stop <= true;
wait;
end process;
end architecture;
\ No newline at end of file
syn/Release/conv_ttl_blo.xise
View file @ fbf25571
......@@ -115,7 +115,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -123,11 +123,11 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -513,7 +513,7 @@
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
......@@ -541,9 +541,9 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../sim/Release/fastevent_counter_tb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="chipscope_ila.vhd" xil_pn:type="FILE_VHDL">
......@@ -649,9 +649,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -692,7 +692,7 @@
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -779,7 +779,7 @@
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -821,8 +821,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -833,7 +833,7 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
......@@ -845,7 +845,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
top/Release/conv_ttl_blo.vhd
View file @ fbf25571
......@@ -177,7 +177,7 @@ architecture arch of conv_ttl_blo is
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"40";
constant c_gwvers : std_logic_vector(7 downto 0) := x"41";
--============================================================================
......@@ -415,8 +415,8 @@ begin
-- Front panel channels
pulse_i => pulse_in,
pulse_front_i => pulse_ttl,
pulse_rear_i => pulse_blo,
pulse_front_i => pulse_ttl,
pulse_rear_i => pulse_blo,
pulse_o => pulse_out,
-- Inverted pulse I/O
......@@ -467,7 +467,7 @@ begin
sfp_present_i => sfp_mod_def0_i,
sfp_rate_select_o => sfp_rate_select_o,
sfp_sda_b => sfp_mod_def1_b,
sfp_scl_i => sfp_mod_def2_b,
sfp_scl_b => sfp_mod_def2_b,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_tx_fault_i => sfp_tx_fault_i,
......@@ -475,8 +475,9 @@ begin
sw_gp_i => sw_gp,
sw_other_i => (others => '0'),
-- PCB Version information
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......@@ -508,7 +509,7 @@ begin
--============================================================================
-- Channel output logic
--============================================================================
-- TTL and RS-485 outputs
-- TTL and blocking outputs
ttl_o <= pulse_out when sw_ttl = '1' else
not pulse_out;
......@@ -517,6 +518,7 @@ begin
-----------------------------------------
-- LED outputs
led_front_n_o <= not led_pulse;
led_front_inv_n_o <= not led_inv_pulse;
led_rear_n_o <= not led_pulse;
......
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