Conv TTL Blocking - Gateware:0998df2cb2e9ecb573e8ead301f0668479d0699d commitshttps://ohwr.org/project/conv-ttl-blo-gw/commits/0998df2cb2e9ecb573e8ead301f0668479d0699d2018-09-27T11:41:28Zhttps://ohwr.org/project/conv-ttl-blo-gw/commit/0998df2cb2e9ecb573e8ead301f0668479d0699dDOC: updated memory map appendix with release 4.1 names2018-09-27T11:41:28ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/d6f11be5322f154b90320721c2b83e47abccac36Merge branch 'proposed-master'2018-09-27T10:03:29ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/a485a730b3630968cbc0b9c1a6824bcabdfaf405minor stylistic changes. Commits golden and release projects2018-09-27T09:52:21ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/ccc3388213287c7eb3a17cf6e995014744bbd4d3now on master branch of conv-common-gw2018-09-27T09:43:50ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/fc3445d6e45629a014a894f6d6b8749bf6cca3b4Adds the words golden and release to golden and release files respectively2018-01-22T13:32:22ZDenia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/683170d5f85defb5ae7d2dedd189e4d1bde0481eMerge branch 'db-release-41' into proposed-master2018-01-19T14:31:23ZDenia Bouhired-Ferragdenia.bouhired@cern.chAdded golden bitstream as subfolder, as previously was stored in
branch.https://ohwr.org/project/conv-ttl-blo-gw/commit/1403106021a416ef4cb818202a15b1e63b49957eUpdated project file for golden release2018-01-19T13:45:08ZDenia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/66c6f4bcfb0ff95b0d4dcc2707dc52ddd1ee6715Modified top module for golden gateware release2018-01-19T13:41:38ZDenia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/755d8f81e525623cf55861b94e8cbdde29fa38d7WIP: changed version number of golden top file2018-01-19T10:53:03ZDenia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/b081f7d3e7e747147ed2e6e0df3883bc60093e93Work in progress: Minor mods in Release top file, plus created Golden folder…2018-01-19T10:51:27ZDenia Bouhired-Ferragdenia.bouhired@cern.chWork in progress: Minor mods in Release top file, plus created Golden folder with dummy golden top file.
https://ohwr.org/project/conv-ttl-blo-gw/commit/fbf255714181664eb8406bc619ea02456c8f2585Update top file with new minor release number, with minor changes to alignment…2018-01-17T12:50:04ZDenia Bouhired-Ferragdenia.bouhired@cern.chUpdate top file with new minor release number, with minor changes to alignment and port renaming. Added fascounter testbench and two svg figures to hdl guide
https://ohwr.org/project/conv-ttl-blo-gw/commit/abb0a98b7468992bbbe6915e06570748b4566db1changed submodule conv-common-gw from r+w to read only2017-09-26T09:04:23ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/c25835d2faf9b349c7bf3b6589e86cf53e207d44Updated project file2017-07-14T11:47:46ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/3f03051f920ddf6a61f83f7c6bb685f085dbe25fMerged conv-common-gw dev branch to master2017-07-14T11:45:53ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/0396b6d180d93f0a93ebae6e6c22b845f26f2973Modified gw test procedure document with correct short URL to release 4 bitst...2017-04-12T15:13:06ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/949310676065bccb26548e65b3584eea769741beCommented out the hack for v3 boards, where the PCB version is not yet…2017-04-12T14:35:54ZDenia Bouhireddenia.bouhired@cern.chCommented out the hack for v3 boards, where the PCB version is not yet available. the previous top file was enabling the burst mode via a dip switch sw2.3. In final release this functionality is ONLY enabled by reading the PCB version inputs to the FPGA
https://ohwr.org/project/conv-ttl-blo-gw/commit/393015d11580ce49ad60d6d23f4bdf6700c232acUpdated .gitignore2017-03-10T10:37:07ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/4e4cee23bfa0b1e63555df625a2ed44424d8638aUpdated the gateware testing manual2017-03-10T10:34:29ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/a49147adab17903b109ad113149dd221ebc00629Added project file and manifest in ./syn folder2017-03-10T10:14:51ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/dba7f4b05402f399272c6d75cc1d87a7423b9423Use updated conv-common gateware2017-03-10T10:09:03ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/ad800f0cb79152b5c3481500e692875f4afd82fcClean up of ./syn folder2017-03-10T10:06:59ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/b4f182b50a24b64d2070994ec2582a0944325737Updated project file2017-03-10T09:57:47ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/7af50856b47fd65b50bba8d39b0d4240f346c755Correct version of the diagram2017-03-10T09:48:37ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/5613697e7986c30c26aabc5f51b60c78d5415cacChange to some of the sfp port names on con-common-gw component2017-03-08T16:03:50ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/8ad80376d60742e2ec0081c03d38745f59ec4cd1Renamed some of conv-common-gw ports to avoid references to signal types (ttl...2017-03-08T15:47:13ZDenia Bouhireddenia.bouhired@cern.chRenamed some of conv-common-gw ports to avoid references to signal types (ttl or blo) are yet to be changed. this is not a priority for release 4 of the gateware.
https://ohwr.org/project/conv-ttl-blo-gw/commit/d6dc4968ff3dc05cd4f1d88edc16d83805766500Deleted a dummy test file.2017-03-08T15:45:32ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/74c8b19b84d1567636cffa84f399dcf27661d1fdDoc: Updated hdl guide with additional note on inverter channel output LEDs.…2017-03-08T15:32:47ZDenia Bouhireddenia.bouhired@cern.chDoc: Updated hdl guide with additional note on inverter channel output LEDs. fixed a typo on conv-regs.
https://ohwr.org/project/conv-ttl-blo-gw/commit/1a34f6941b884ee0771fe335139eac8c12cfc824Small modification in p_inhibit_first_pulse process, now checks that all lines…2017-03-07T13:50:21ZDenia Bouhireddenia.bouhired@cern.chSmall modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.
https://ohwr.org/project/conv-ttl-blo-gw/commit/257f22260e6d3a7068f1a3c18c90dd543c025979Updated project file2017-03-07T12:12:17ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/00409238667589ad7deffb7e7ef51e8e06bbc16cUCF file adds some attributes to the input channel i/o to bypass the fact it is…2017-03-03T16:10:53ZDenia Bouhireddenia.bouhired@cern.chUCF file adds some attributes to the input channel i/o to bypass the fact it is not a clock despite being used as a clock in the flancter
https://ohwr.org/project/conv-ttl-blo-gw/commit/ad80ca56659db235ef619ec51ba23777dce05b5bChanged top file to use periods instead of duty cycles, same changes in conv_...2017-03-03T16:09:37ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/f7e79ef83f572ffa778b9cf0a9c06901ed02ba61doc/gw-test-procedure: modified the title page2017-02-28T13:00:45ZMaciej Suminskimaciej.suminski@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/382b1bcc40db9b9182c08e9e3f6513fb8df4f604doc/gw-test-procedure: fixed the link for v4 gw2017-02-28T12:58:18ZMaciej Suminskimaciej.suminski@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/1d502af8339d384ab3aa394dfa1210a6677b0278Doc: Updated hdl guide for release 42017-02-28T10:37:40ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/6b98bb0dae47e7a4c5eadf8e52803ce65af274b5doc/gw-test-procedure: Tests for pulse counters2017-02-20T13:27:17ZMaciej Suminskimaciej.suminski@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/97d44e56b17e82a05819a9456814809feaa2860bdoc/gw-test-procedure: add tests for both short & long pulse modes2017-02-17T17:08:58ZMaciej Suminskimaciej.suminski@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/ef46d4ee05461d58680f1648a0ea1ba264833d21doc/gw-test-procedure: updated the title page2017-02-17T17:08:58ZMaciej Suminskimaciej.suminski@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/commit/d3614b64f62daaa0e1b33bc75ac048aafe7d2df0doc/gw-test-procedure: pulse rejection testing procedure2017-02-17T17:08:58ZMaciej Suminskiorson@orson.net.plhttps://ohwr.org/project/conv-ttl-blo-gw/commit/eb3f198736fcf09dd73991932111ac36a95480bcdoc/gw-test-procedure: pulsegen description2017-02-17T17:08:58ZMaciej Suminskiorson@orson.net.plhttps://ohwr.org/project/conv-ttl-blo-gw/commit/ca007ca1c07c76a7565918ea5f5fe4528fe2cd50doc/gw-test-procedure: update version numbers in commands and sample texts2017-02-17T17:08:57ZMaciej Suminskiorson@orson.net.pl