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  17. 26 Mar, 2014 1 commit
  18. 25 Mar, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Work on release v2.1 · 0dd7106c
      Theodor-Adrian Stana authored
      hdl:
      - substitute FIFO for ring buffer
      - change pulse repetition duty cycle to 1/500
      - renamed some files to make "generic" naming
      
      sim:
      - release: add I2C simulation capabilities
      - conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle
      
      syn:
      - update project file with new files
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      0dd7106c
  19. 06 Mar, 2014 1 commit
  20. 19 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Pre-version 2.0 commit · 64f1a255
      Theodor-Adrian Stana authored
      Changes:
      
      HDL:
      
      - added pulse time tagging core (pulse_timetag.vhd)
      - added FIFO via the conv_regs.wb file
      - to make the FIFO read work properly, I needed to change the
      wb_i2c_bridge component (general-cores submodule)
      - updated top-level to connect the FIFO to conv_regs component
      - moved the pulse generator glitch filter to outside the pulse
      generator
      - changed the conv_pulse_gen block to be able to properly reject
      pulses up to only 1/5 duty cycle, not more (I realized by simulation
      that when the glitch filter was enabled, it needed one extra cycle,
      thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
      - updated synthesis files for the Release project to add the new files,
      and the regtest and pulsetest due to the I2C bridge changes
      
      Simulation files:
      - conv_pulse_gen: changes for the aforementioned change test
      - added pulse_timetag sim files
      - added release top-level simulation, which at the moment does
      not contain a lot of stuff (only pulse rep test), but can be used as a
      starter to verify the design works appropriately
      
      Doc:
      - updated memory map with cute wbgen-ized memory map
      - added time-tagging core information
      - updated the Getting Around the Code section
      - added and updated figures
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      64f1a255
  21. 30 Jan, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Made manual pulse trigger work properly · c74ddcd8
      Theodor-Adrian Stana authored
      Prior to this commit, manual pulse triggering did not work when the glitch
      filter was enabled. Now, this was fixed by extending the trigger pulse the
      conv_man_trig module generates. This accounts for the situation where the
      pulse generator has the glitch filter enabled.
      
      I also fixed a bug in conv_pulse_gen; this fix was commited two commits ago.
      The bug consisted of the gf_off part of the pulse generator triggering even
      when the glitch filter was enabled. This resulted in a continuous high pulse
      generated on the output when the glitch filter was switched from on to off.
      Granted, such a situation should not occur in operation, since a board needs
      to be removed from the crate in order to flip a switch. Nonetheless, it was a
      but, so I've fixed it by making sure the gf_off part of the design only triggers
      when the glitch filter is disabled:
      
      if (en_i = '1') and (gf_en_n_i = '1') then
        pulse_gf_off <= '1';
      end if;
      
      A warning will be placed in the docs for release versions 1.0 and 0.0 (golden).
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      c74ddcd8
  22. 29 Jan, 2014 1 commit
  23. 07 Jan, 2014 3 commits
  24. 19 Dec, 2013 1 commit
  25. 08 Dec, 2013 3 commits
  26. 20 Nov, 2013 1 commit
  27. 19 Nov, 2013 4 commits