Gateware v2.2

Fixes the issue about the first pulse inhibit mechanism not working.

When the first pulse inhibit mechanism was first implemented, the
FSM of the ctblo_pulse_gen module was triggering one clock cycle earlier
than it actually is, due to the trig_gf_on_r_edge_p signal now triggering
said FSM. This meant that the inhibit signal was "de-inhibiting" one clock
cycle too early, thus yielding in a pulse still being generated after reset.

This issue was fixed by introducing a delay into the inhibit signal and checking
for the state of this delayed signal before triggering.