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Theodor-Adrian Stana authored
hdl: - substitute FIFO for ring buffer - change pulse repetition duty cycle to 1/500 - renamed some files to make "generic" naming sim: - release: add I2C simulation capabilities - conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle syn: - update project file with new files Signed-off-by: Theodor Stana <t.stana@cern.ch>
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