Gateware for CONV-TTL-BLO boards
Project description
Gateware implemented in VHDL for the Xilinx Spartan-6 FPGA ensures most of the functionalities for the CONV-TTL-BLO board:
- Pulse regeneration based on input trigger for each of the six input channels
- Communication via I2C and ELMA
protocol
- Retrieve board status and firmware version
- Remote reprogramming (work in progress)
- Pulse logging (work in progress)
- Controlling pulse and system status LEDs
- RTM detection
Releases
Status
Date | Event |
05-08-2013 | Gateware v1.02 released |
Theodor-Adrian Stana, Erik van der Bij, 2013