CONV-TTL-BLO gateware version 3.0
Release notes
-
CHANGES IN MEMORY MAP FROM PREVIOUS VERSIONS
- the Multiboot module is now at address 0x100
- the one-wire master module is now at address 0x200
- see the HDL guide for details
- Uses the converter board common gateware
- Pulse repetition with max. frequency of 4150 Hz
- 1.2us pulse on output
- duty cycle of 1/200
- input pulses with duty cycle of more than 1/200 are rejected
- I2C to Wishbone bridge following the protocol defined together with ELMA
- Diagnostics support
- converter board ID
- unique board ID via DS18B20 thermometer chip
- gateware version
- state of on-board switches
- state of RTM detection lines
- state of I2C watchdog timer
- input pulse counters
- time-tagging of last 128 received pulses, stored in rolling ring buffer
- remote logic reset
- manual pulse triggering
- system errors (also light ERR LED)
- per-channel latest timestamp readout from dedicated registers
- line status readout from dedicated register
- Pulse and status LED control
- Remote reprogramming
- Connects VME SYSRESET signal to reset the FPGA logic
Binary files
- Binary files for remote reprogramming
- Binary files for direct programming into the flash
Sources
Documentation
- Block diagram
* For the implementation of each block, consult the HDL guide
-
compile from source
git clone git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git cd conv-ttl-blo-gw git checkout v3.0 cd doc/hdlg/ make
Theodor-Adrian Stana, Sept. 2014