CONV-TTL-BLO gateware version 4.0
Release notes
- CHANGES IN MEMORY MAP FROM PREVIOUS VERSIONS
- Enables high-frequency operation and support for burst mode in hardware v4 boards.
- Remains backwards compatible with v3 boards and earlier, while bringing in some additional features.
Features available in all hardware versions of the board:*
- PCB version recognition available at the FPGA as 6 bits (4 bits for the version number and 2 bits for the revision) and for diagnostics via the status register SR.
- Changes in memory map:
- One-wire thermometer no longer accessible via one-wire master,
instead:
- Temperature is available in single register as 16-bit value. Temperature = 0d(TEMP)/16.
- One-wire chip unique 64-bit ID stored in two 32-bit registers, readable from registers.
- Separate pulse counters for TTL and for BLOCKING inputs, therefore two pulse counters per channel.
- Error data moved from SR (status register) to own ERR register.
- One-wire thermometer no longer accessible via one-wire master,
instead:
Features available in v4 only of the board:*
- Pulse width selection switch, assigned to dip switch SW1.1.
- LONG: Pulses are 1.2us long.
- SHORT: Pulses are 250ns long.
- Continuous repetition:
- LONG pulses: maximum continuous repetition frequency 52kHz corresponds to 1/16 duty cycle (19.2us period).
- SHORT pulses: maximum continuous repetition frequency 571kHz corresponds to 1/7 duty cycle (1.75us period).
- High frequency Burst repetition: Higher frequencies can be accepted,
but for a limited amount of time.
- LONG pulses: maximum burst frequency 104kHz corresponds to 1/8 duty cycle (8.6us period). Sustained for 1s maximum.
- SHORT pulses: maximum burst frequency 2MHZ corresponds to 1/2 duty cycle (0.5us period). Sustained for 1s maximum.