Golden release gateware, version 0.0
This firmware is the same as for the v1.0 release gateware, except that the FWVERS field reads out as 0x00*. It is kept here for "historic" purposes.
Release notes
- Pulse repetition with max. duty cycle of 1/5; input pulses with duty cycle >1/5 are rejected
- I2C to Wishbone bridge following the protocol defined together with ELMA
- Dedicated CONV-TTL-BLO registers (see full memory map in the HDL
guide):
- Board ID register
- CSR
- remote logic reset
- firmware version
- state of on-board switches
- state of RTM detection lines
- state of I2C watchdog timer
- Pulse and status LED control
- Remote reprogramming
Binary files
- Raw binary files of golden bitstream:
- Binaries containing golden and gateware v1.0 bitstreams, downloaded by default to the flash of the first 100 produced CONV-TTL-BLO
Sources
Documentation
- The block diagram of the logic is shown below.
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* For information on the implementation of each block, consult the HDL guide:
git clone -b golden git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
cd doc/hdlguide/
make
Theodor-Adrian Stana, Jan. 2014