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\include{cern-title}

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% Licensing info
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\addcontentsline{toc}{section}{Licensing information}
\section*{Licensing information}

\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see \\
\url{http://creativecommons.org/licenses/by-sa/4.0/}

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% Revision history
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\section*{Revision history}
\addcontentsline{toc}{section}{Revision history}

\centerline
{
  \rowcolors{2}{white}{gray!25}
  \begin{tabular}{l c p{.6\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
  \hline
  04-07-2013 & 0.1 & \textit{T.Stana} First draft \\
  26-07-2013 & 0.2 & \textit{T.Stana}  Second draft \\
  21-01-2015 & 1.0 & \textit{T.Stana}  First release, adding blocking output max. pulse duty cycle calculation and several extra information
                     about the blocking output stage \\
  27-01-2015 & 1.1 & \textit{T.Stana}  Added (in Appendix~\ref{app:blo-max-freq}) a specification of why the pulse period was selected as it
                     is in the user guide \\
  06-02-2017 & 2.0 & \textit{D.Bouhired} Second release, for PCB version 4.0. Added description of blocking output circuit protection and PCB version circuit\\
  \hline
  \end{tabular}
}
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% Table of contents, list of figs, tables
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\listoffigures
\listoftables

%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
RTM & Rear-Transition Module \\
IC  & Integrated Circuit \\
I$^2$C  & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
RTM & Rear Transition Module \\
SFP & Small-Form-factor Pluggable (transceiver) \\
TVS & Transient Voltage Suppressor (diode) \\
SVEC & Simple VME FMC Carrier \\
SPEC & Simple PCIe FMC Carrier \\
VME & Versa Module Eurocard \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}

%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}

This document explains in detail the hardware of the TTL to blocking converter
system (Figure~\ref{fig:conv-sys-bd}). A full pulse conversion system consists of
three distinct boards:
\begin{itemize}
  \item CONV-TTL-BLO -- active front module, containing the circuits necessary
  to achieve all functionality of the system
  \item CONV-TTL-RTM -- passive rear-transition module (RTM) motherboard, providing the
  connections   from the CONV-TTL-BLO VME P2 connector to the rear panel
  \item CONV-TTL-RTM-BLO -- piggyback board on the RTM, providing the LEMO connectors,
  pulse LEDs, and the screws to fix the rear panel
\end{itemize}

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/conv-sys-bd}}
  \caption{TTL to blocking pulse conversion system}
  \label{fig:conv-sys-bd}
\end{figure}

The CONV-TTL-BLO can be used standalone without any RTM, if no blocking pulse replication
is needed. This board contains all active circuitry needed to implement the functionalty of
the system, from blocking pulse detection and generation, to communication over I$^2$C and
time-tagging via White Rabbit \cite{white-rabbit}.

An RTM system usually consists of both motherboard and piggyback and provide the
connections to input blocking pulses to the CONV-TTL-BLO.

%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\pagebreak
\subsection{Additional documentation}

\begin{itemize}
  \item CONV-TTL-BLO OHWR Project Page \cite{ctb-proj}
  \item CONV-TTL-BLO Schematics on CERN EDMS \cite{sch}
  \item CONV-TTL-BLO User Guide \cite{ctb-ug}
  \item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}

%==============================================================================
% SEC: CONV-TTL-BLO
%==============================================================================
\section{Front module}
\label{sec:ctb}

A block diagram of the CONV-TTL-BLO front module is shown in Figure~\ref{fig:conv-ttl-blo-bd}.
The board contains all active circuitry needed within a converter system. The various blocks in
Figure~\ref{fig:conv-ttl-blo-bd} are presented in subsections that follow.

The schematics of the CONV-TTL-BLO board can be found at \cite{sch}.

\begin{figure}[h]
  \centerline{\includegraphics[width=.65\textwidth]{fig/conv-ttl-blo-bd}}
  \caption{Block diagram of CONV-TTL-BLO board}
  \label{fig:conv-ttl-blo-bd}
\end{figure}

%------------------------------------------------------------------------------
% SEC: VME conn
%------------------------------------------------------------------------------
\subsection{VME connector}
\label{sec:vme}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent

The VME backplane consists in two connectors, P1 and P2. The following connections
provided by the P1 connector are used on the CONV-TTL-BLO:
\begin{itemize}
  \item the VME power supply pins (3.3~V, 5~V and 12~V)
  \item \textit{SERCLK} and \textit{SERDAT} pins, for I$^2$C communication
  \item the geographical addressing pins, also necessary for I$^2$C communication
  \item the active-low system reset line, connected to the FPGA for resetting the
  logic implemented therein
\end{itemize}

Serial communication lines, geographical addressing lines and the system reset line
are isolated from the FPGA by means of a Texas Instruments SN74VMEH22501DGGR bus
transceiver. Their use is based on the SVEC design \cite{svec} and is due to their
compatibility to the VME standard.

Apart from the bus grant and IACK lines, which are daisy-chained, the rest of the
VME signals are not used on the CONV-TTL-BLO board.

The user-defined part of the P2 connector is used for carrying signals from the
CONV-TTL-BLO to the RTM and ultimately the piggyback. The following signals are
routed via the VME P2 connector:

\begin{itemize}
  \item blocking input signals (Section~\ref{sec:blo-inp})
  \item blocking output signals (Section~\ref{sec:blo-outp})
  \item RTM detection and rear panel pulse LED signals (Section~\ref{sec:rmtdet})
\end{itemize}

%------------------------------------------------------------------------------
% SUBSEC: Power
%------------------------------------------------------------------------------
\subsection{Power supplies}
\label{sec:ctb-power}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 2, 3 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent Various power levels are needed on the CONV-TTL-BLO board. They are listed in
Table~\ref{tbl:voltage-levels}. All power supplies on the board are derived
in some way from the 3.3~V, 5~V and 12~V VME power supplies.

\begin{table}[h]
\caption{Voltage levels on CONV-TTL-BLO}
\label{tbl:voltage-levels}
\centerline{
  \rowcolors{2}{white}{gray!25}
  \begin{tabular}{l p{.5\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Level}} & \multicolumn{1}{c}{\textbf{Description}} \\
  \hline
  1.2~V & Low-voltage power supply for the FPGA logic \\
  3.3~V & V$_{CC}$ for most of the devices on the board \\
  5~V   & Power supply for some circuits on-board (blocking input optocouplers, blocking
          output buffers, etc.) \\
  24~V  & Blocking-level power supply \\
  \hline
  \end{tabular}
}
\end{table}

First, the 5~V and 3.3~V VME supplies arriving on the VME connectors are filtered using
two PI filters (schematic page 2). These filters assure noise immunity in the 50~MHz to
150~MHz band. The filtered power supplies are used throughout the logic.

The 1.2~V logic power supply is generated by a Texas Instruments TPS54312PWP Buck converter.
This circuit can be found in page 2 of the schematics.

Finally, the 24~V blocking power supply (schematics page 3) uses a Texas Instruments
TPS40210DGQR boost converter. The values various components around the converter were calculated
using the first design example in the datasheet of the device.

%------------------------------------------------------------------------------
% SUBSEC: Clocks
%------------------------------------------------------------------------------
\subsection{Clock circuits}
\label{sec:clocks}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 5 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent There are multiple clock signals on the CONV-TTL-BLO (Table~\ref{tbl:clocks}).
A 20~MHz clock for the FPGA is generated directly from a tunable VCXO (OSC3). The
second FPGA clock is a 125~MHz signal generated from a 25~MHz VCXO by means of a Texas
Instruments CDCM61004RHBT PLL IC. Two of the other PLL's output channels are used
to output dedicated 125~MHz dedicated clocks to the SFP and FPGA transceiver.

\begin{table}[h]
\caption{Clocks on CONV-TTL-BLO}
\label{tbl:clocks}
\centerline
{
  \rowcolors{2}{white}{gray!25}
  \begin{tabular}{l r l}
  \hline
  \multicolumn{1}{c}{\textbf{Clock}} & \multicolumn{1}{c}{\textbf{Frequency}} & \multicolumn{1}{c}{\textbf{Description}} \\
  \hline
  CLK20\_VCXO &  20~MHz & FPGA clock (from VCXO) \\
  FPGA\_CLK   & 125~MHz & FPGA clock (from PLL IC) \\
  SFP\_CLK    & 125~MHz & Dedicated SFP clock \\
  FPGA\_MGT\_CLK & 125~MHz & Dedicated clock for FPGA transceiver \\
  \hline
  \end{tabular}
}
\end{table}

Both VCXOs can be tuned by means of two Analog Devices DACs (IC17 and IC18), that
can be controlled by the FPGA via a 3-wire SPI interface.

The 3.3~V power supply used by ICs on the clock generation part is a cleaner version
of the board-wide 3.3~V supply. The cleaning is done by a four-pole LC filter.

The design of the clock circuits is based on the SPEC board design \cite{spec}.

%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
%------------------------------------------------------------------------------
\subsection{FPGA}
\label{sec:fpga}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 4 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent A Xilinx XC6SLX45T Spartan-6 FPGA is present on the CONV-TTL-BLO board. It is the
core part of the blocking conversion system, since it is the device controlling
all the components on the board.

The intended functionality of the FPGA is:

\begin{itemize}
  \item generating output pulses as response to input pulse
  \item pulse logging
  \item clock conditioning
  \item remote reprogramming
  \item controlling the various panel LEDs to inform the user either of pulse
  arrival, or the status of the system.
\end{itemize}

For more details on the FPGA firmware and functionality, refer to the CONV-TTL-BLO
HDL Guide~\cite{ctb-hdlguide}.

%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
%------------------------------------------------------------------------------
\subsection{TTL pulse repetition}
\label{sec:ttl}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 13 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent TTL and TTL-BAR pulses may arrive on front panels of CONV-TTL-BLO boards. The two
signal types are described in Sections~4.1~and~4.2 of~\cite{ctb-ug}. Signals
arriving on an input channel go through an input stage consisting of Schmitt
trigger circuits; they are then input to the FPGA, where the pulse gets regenerated
and passed to the output stage.

%------------------------------------------------------------------------------
\subsubsection{TTL input stage}

The input stage on a TTL pulse channel is shown in Figure~\ref{fig:ttl-inp}.
Pulses go through a Texas Instruments SN74LVC14AD Schmitt trigger inverter which
isolates the FPGA from the channel input. The inverter is 5~V tolerant at the
input, so TTL signals may be up to 5~V high. Anything above 5.6~V opens the BAR66
diode to the 5~V and protects the Schmitt trigger.

The input stage is 50~$\Omega$ terminated (the three 150~$\Omega$ resistors in parallel).
Note that when no wire is plugged into the LEMO connector, the termination pulls the line low
which becomes a continuous high-level when it comes out of the Schmitt trigger.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/ttl-inp}}
  \caption{TTL pulse input stage}
  \label{fig:ttl-inp}
\end{figure}

This input stage is repeated on each of the six TTL pulse replication channels of
the CONV-TTL-BLO, as well as the four inverter channels.

%------------------------------------------------------------------------------
\subsubsection{TTL output stage}

The output stage consists of Texas Instruments SN64BCT25244DW tri-state buffers
driven by the FPGA. These buffers assure a high-impedance output on startup and
assure the line can drive a 50~$\Omega$ load. Pull-down resistors at the output
of the tri-state buffers assure a continuous low level at the output when the
buffers are not enabled. Combined with the guaranteed tri-state output on startup,
these resistors assure a continuous low-level at the output on startup.

The buffers' enable signals are controlled by two signals from the FPGA.
These signals are NANDed together (IC10 NAND gate) and connected to the output
enable active-low signals. When the FPGA does not drive the output enable line,
it is pulled high by a pull-up resistor, to safeguard against spurious signals on the
output of the channel.

%------------------------------------------------------------------------------
% SUBSEC: Blocking pulse rep
%------------------------------------------------------------------------------
\subsection{Blocking pulse repetition}
\label{sec:blo}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9-12 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent Blocking pulses arrive through the LEMO connectors on the rear panel. Through the
RTM and the P2 connector, they arrive at the blocking input stage on the CONV-TTL-BLO,
where an optocoupler is used to isolate the input signal from the logic levels of
the FPGA. The input pulse then goes into the FPGA, where the pulse is regenerated
in the same manner as TTL pulses. The regenerated pulse signal goes through a flyback
converter output stage, where the logic levels of the FPGA are converted back into
blocking level.

%------------------------------------------------------------------------------
\subsubsection{Blocking input stage}
\label{sec:blo-inp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9, 10 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The blocking input stage (Figure~\ref{fig:blo-inp-nodots}) contains the 50~$\Omega$ termination,
a transient voltage suppressor diode to protect against high-voltage spikes from the RTM, a
high-pass RC filter which prevents DC signals from passing to the Avago optocoupler. The optocoupler
isolates the blocking-level stage from the logic stage on the FPGA side. Since the
optocoupler is powered from 5~V, a Schmitt trigger (not shown in Figure~\ref{fig:blo-inp-nodots})
adapts the 5~V level to the 3.3~V level needed by the FPGA.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-inp-nodots}}
  \caption{Blocking input stage}
  \label{fig:blo-inp-nodots}
\end{figure}

The minimum pulse level for this circuit is 3.8~V (see Appendix~\ref{app:blo-min-level}).

The maximum 24~V pulse duty cycle that can be safely sustained by the input stage is approximately 81\%
(see Appendix~\ref{app:blo-max-width}).

%------------------------------------------------------------------------------
\subsubsection{Blocking output stage}
\label{sec:blo-outp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 11, 12 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The blocking output stage is a flyback converter design with a 1:1 conversion
ratio, shown in Figure~\ref{fig:blo-outp-v4}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. This part of the board has been subject to a review and a redesign for v3 boards and later, this is discussed in detail in~\cite{blo-out-protect}.

In previous versions of the board (v2.1 and earlier) the transformer was driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
This however exposed the transformer and MOSFET to potential damage, due to uncontrolled current flow from the power supply.\\
 For this reason in boards v3 and later, a current limiting resistor is added between the transformer primary and the 24 V rail as shown in Fig.\ref{fig:blo-outp-v4}. The presence of the resistor between the decoupling capacitor 
and power supply, causes the capacitor to charge at power on. When a pulse comes through from the FPGA, the voltage across the inductor changes and current starts to flow from the capacitor and resistor through to the transformer.\\
The snubber circuit next to the transformer formed by the BAR66 diode and the Zener diode
provides a means to dissipate the energy stored in the leakage inductance of the transformer
when the MOSFET is on.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-outp-cap}}
  \caption{Blocking output stage- v2.1 and earlier.}
  \label{fig:blo-outp-cap-v2-1}
\end{figure}

\begin{figure}[h]
  \centerline{\includegraphics[width=1.1\textwidth]{fig/blo-outp-v4}}
  \caption{Blocking output stage- v3 and later.}
  \label{fig:blo-outp-v4}
\end{figure}


\begin{figure}[h]
  \centerline{\includegraphics[scale=0.5]{fig/blo-outp-tristate-v4}}
  \caption{Blocking output tri-state buffers}
  \label{fig:blo-outp-tristate}
\end{figure}

In order to further protect the blocking output stage MOSFET, a pulse width limitation circuit is added on v3 boards and later. This circuit can be seen in Fig. \ref{fig:blo-outp-v4} at the gate of the BSH103. It consists of a differentiator RC circuit, capable of detecting rising pulse edges. The $\tau=RC$ time constant will determine how long the MOSFET is left ON following the rising edge of a pulse. The gate voltage will reach the threshold gate trigger value after $\approx 8\mu s$ to make sure that the gate voltage remains well above threshold during the $1.2\mu s$ window, longest output pulse length (See~\cite{blo-out-protect} for more details).

In board versions 2.1 and earlier, the maximum pulse duty cycle that can be sustained without damaging the MOSFET
considering nominal blocking pulse widths~\cite{blo-std} of 1.2~$\mu$s, is approximately 4160~Hz
(see Appendix~\ref{app:blo-max-freq}). However, by implementing the blocking output stage protection techniques mentioned earlier and outlined in~\cite{blo-out-protect}, these duty cycles can be significantly improved upon.\\
In fact, to achieve very high repetition frequencies, the  gateware for CONV-TTL-BLO board for v4 and later, offers a pulse-width selection feature, that allows for frequencies of up to 2MHz to be reached, when using narrow pulses ($250ns$). These high repetition frequencies are possible as part of a burst mode functionality, which allows the board to operate at higher frequencies but for a limited amount of time (see~\cite{blo-out-protect} and~\cite{ctb-ug} for more details on operation in this mode).

Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
inputs are pulled-down on startup, thus avoiding spurious signals on blocking outputs. Though these were left in tri-state at startup in v2.1 boards, it was seen that this can cause irreversible damage to the board in some circumstances such as hot-swaps \cite{hotswap-issue}.
The extra pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid on startup.

The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
signal common with the TTL output enable, and a separate, blocking output enable signal.
These two signals go through the IC10 NAND gate to enable the buffers. When the FPGA does
not drive either of these signals, the output enable input of the buffers is kept high via
the pull-up resistor.

The blocking output stage is susceptible to common-impedance coupling, due to the high inter-winding
capacitance of the selected transformer. The solution to this problem is provided in the form of the
100~nF capacitor placed between pin 4 of the transformer and the common reference (GND) network. Note
that this capacitor is either straddled on top of the RTM TVS diodes, or placed directly on the RTMP in
newer board versions. This is shown in Figure~\ref{fig:blo-outp-cap-v2-1} and in Section~\ref{sec:rtm}.
For more details about this common-impedance coupling event, see~\cite{crosstalk}.

\vspace{11pt}

%------------------------------------------------------------------------------
% SEC: Blocking pulse rep
%------------------------------------------------------------------------------
\pagebreak
\subsection{SFP connector}
\label{sec:sfp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 6 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The small form-factor pluggable (SFP) connector on the CONV-TTL-BLO front panel
can be used to input an optic fiber cable that may be used for pulse time-tagging
using White Rabbit.

%------------------------------------------------------------------------------
% SEC: Thermo, flash
%------------------------------------------------------------------------------
\subsection{Thermometer and flash chip}
\label{sec:thermo-flash}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 7 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent A DS18B20U+ thermometer chip is provided on board. This chip can be used to provide
a unique ID for the board and measure on-board temperature. It communicates to the
FPGA via a Dallas one-wire interface and is powered from 3.3~V.

The Flash chip on-board is used to store FPGA configuration data. It is a Micron
M25P32 SPI Flash memory chip with 32~Mbits storage capability.

%------------------------------------------------------------------------------
% SEC: RTM det
%------------------------------------------------------------------------------
\subsection{RTM detection}
\label{sec:rmtdet}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent 

The RTM detection circuitry is shown in Figure~\ref{fig:rtmdet}. It works by
connecting the RTM motherboard or piggyback detection lines to ground, based
on the motherboard or piggyback used. Lines not connected to ground are pulled
up to V$_{CC}$ by the pull-up resistor, which yields a low value after
the Schmitt triggers. The outputs of the Schmitt triggers are connected directly
to the FPGA inputs.

An up-to-date list of boards and their RTM detection line connections can be found
at \cite{rtmdet}.

\begin{figure}[h]
  \centerline{\includegraphics[scale=1]{fig/rtmdet}}
  \caption{RTM detection circuit}
  \label{fig:rtmdet}
\end{figure}

%------------------------------------------------------------------------------
% SEC: LEDs, status and pulse
%------------------------------------------------------------------------------
\subsection{Status and pulse LEDs}
\label{sec:leds}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 14 \\
\hline
\end{tabular}

\vspace*{11pt}

The circuit for driving the bicolor status LEDs is based on the SVEC design \cite{svec}.
It consists of the same Texas Instruments SN74VMEH22501DGGR bus buffer chip used
for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of~\cite{ctb-hdlguide}.

TTL (front panel), INV channels (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
the Schmitt trigger is connected directly to the VME P2 connector and through
the RTM to the piggyback, where the current-limiting resistor and the LEDare located.


%------------------------------------------------------------------------------
% SEC: PCB version
%------------------------------------------------------------------------------

\subsection{PCB version}
\label{sec:diag-pcbvers}
The PCB version is necessary to the operation of the burst mode. Indeed the FPGA reads out the hardware version,
and depending on whether the board is v4 and later or v3 earlier, will enable or disable this functionality accordingly.
The PCB version is provided to the FPGA via a resistor network offering 4 bits for the version number
 and 2 bits for potential revisions. The circuit is shown in Fig.~\ref{fig:pcb-version}.
\begin{figure}[h]
	\centering
		\includegraphics[scale=0.5]{fig/pcb-version.png}
		\caption{Hard-wired PCB versioning}
	\label{fig:pcb-version}
\end{figure}

Board version can be read as 4 bits, 1s when the resistors are pulled up, 0s when they are pulled down. Board revision is available in 2-bits, read-out in the same way. For example, Fig.~\ref{fig:pcb-version} shows a v4.0 board.
Note that PCB identification is not available in boards v3 and earlier, and therefore will be read as all zeroes in the FPGA.

%==============================================================================
% SEC: RTM, RTMP
%==============================================================================
\section{Rear-Transition Module}
\label{sec:rtm}

Rear transition modules (RTMs) are located on the rear side of the VME crate.
An RTM in TTL to blocking converter systems is made up of two boards, the
motherboard and the piggyback, containing only passive components. The two boards
are detailed in the next subsections.

%------------------------------------------------------------------------------
% SUBSEC: RTMM
%------------------------------------------------------------------------------
\subsection{RTM Motherboard}

The CONV-TTL-RTM motherboard~\cite{rtmm-sch} is the interface between the VME P2
connector and the RTM piggyback board. It provides a female connector to the VME
backplane P2 connector and links the blocking and pulse LED signals from the
CONV-TTL-BLO to the piggyback via a 100-pin connector.

RTM motherboards are used in both CONV-TTL-BLO and CONV-TTL-RS485 systems, with
different piggybacks.

The motherboard also contains 47~V transient voltage suppressor (TVS) diodes that inhibit
high-voltage pulses arriving on piggyback LEMO connectors. The first two production
versions have the 100~nF capacitor that solves the common-impedance coupling
problem~\cite{crosstalk} soldered on top of these TVS diodes, as shown in Figure~\ref{fig:straddled}.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/straddled.jpg}}
  \caption{\label{fig:straddled} Capacitors straddled on the TVS diodes on some RTMM cards}
\end{figure}

%------------------------------------------------------------------------------
% SUBSEC: RTMP
%------------------------------------------------------------------------------
\pagebreak
\subsection{RTM Piggyback}

The CONV-TTL-RTM-BLO piggyback~\cite{rtmp-sch}, provides the
actual connectors on rear panels of TTL to blocking converter systems. On each of the
six blocking channels, there are four LEMO connectors (one input and three outputs)
and one LED together with its corresponding current-limiting resistor. The connections
for each of the LEMOs and LEDs are made via the 100-pin male connector, through the RTM
motherboard, to the CONV-TTL-BLO.

On newer piggyback boards, the 100~nF capacitor which solves the common-impedance coupling
issue~\cite{crosstalk} is placed close to the LEMO output connectors. Figure~\ref{fig:rtmm-new-sch}
shows this connection.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/rtmm-new-sch}}
  \caption{\label{fig:rtmm-new-sch} Schematics of newer-version piggyback cards}
\end{figure}


%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}

%==============================================================================
% APP: Block inp stage calc
%==============================================================================
\section{Blocking input stage calculations}
\label{app:blo-inp}

Figure~\ref{fig:blo-inp} shows the blocking input stage, as a reference for the
calculations below.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-inp}}
  \caption{Blocking input stage}
  \label{fig:blo-inp}
\end{figure}


%------------------------------------------------------------------------------
% SUBSEC: min pulse level
%------------------------------------------------------------------------------
\subsection{Minimum blocking pulse level}
\label{app:blo-min-level}

The optocoupler LED has a maximal forward voltage of 1.8~V and therefore when the LED is on,
the voltage in point 2 of Figure~\ref{fig:blo-inp} is

 \begin{equation}
  V_2 = 1.5V
\end{equation}

This means that for the LED to turn on, only

\begin{equation}
V_2 = \frac{R_{152}}{R_{152} + R_{147}}{V_1}
\end{equation}

\begin{equation}
V_1 = \frac{R_{152} + R_{147}}{R_{152}}{V_2}
\end{equation}

\begin{equation}
V_1 = \frac{5k7}{4k7} \times 1.5 = 1.82 V
\end{equation}

\noindent are needed at the blocking input. However, the LED needs to reach a certain
intensity level before it triggers the output of the optocoupler. This translates into
a threshold current for the LED, which is given in the optocoupler datasheet \cite{opto-ds}
to have a typical value of

\begin{equation}
I_{TH} = 2mA
\end{equation}

Inputting this into the circuit calculation above, and knowing that when the LED is on
a 0.31~mA current passes through $R_{152}$ (1.5~V / 4k7~$\Omega$), this yields a
current of 2.31~mA passing through $R_{147}$ ($I_{LED} + I_{R_{152}}$).
This results in a minimum pulse level of

\begin{equation}
V_1 - V_2 = 2.31mA \times 1k{\Omega}
\end{equation}

\begin{equation}
V_{1,min} = 3.8V
\end{equation}

This value has been verified in practice to be the minimum input pulse level for which
a pulse is generated at the output.

%------------------------------------------------------------------------------
% SUBSEC: max pulse width
%------------------------------------------------------------------------------
\subsection{Maximum blocking duty cycle}
\label{app:blo-max-width}

Considering 24~V pulses at the blocking input (point 1 in Figure~\ref{fig:blo-inp})
and the fact that the forward voltage of the LED when conducting is 1.5~V ($V_2 =$ 1.5~V),
this yields a 22.5~mA current going through $R_{147}$

\begin{equation}
I_{R_{147}} = \frac{24-1.5}{1k} = 22.5mA
\end{equation}

Since this current is divided among $R_{152}$ and the optocoupler LED and the current
through $R_{152}$ is

\begin{equation}
I_{R_{152}} = \frac{V_2}{R_{152}} = \frac{1.5}{4k7} = 0.31mA
\end{equation}

\noindent the current through the LED is

\begin{equation}
I_{LED} = I_{R_{147}} - I_{R_{152}} \cong 22.2mA
\end{equation}

Now, by considering the maximum input RMS current of 20~mA obtained from the
optocoupler's datasheet \cite{opto-ds}, and given that the RMS current for the pulse wave is

\begin{equation}
I_{LED,RMS} = I_{LED} \sqrt{\delta}
\end{equation}

\noindent this gives a maximum duty cycle of

\begin{equation}
\delta \cong 0.81
\end{equation}

%==============================================================================
% APP: Block outp stage calc
%==============================================================================
\pagebreak
\section{Blocking output stage calculations}
\label{app:blo-outp}

\textbf{\textit{ Since the following calculations were originally intended to document design 
decisions 
related with v2.1 boards and implemented in release 3.0 of the gateware, they are no longer 
applicable for v4 boards.\\
 Indeed, the blocking output protection discussed in Sec.\ref{sec:blo-outp} and in 
\cite{blo-out-protect}, means that frequency of repetition can be considerably 
increased, by relying on adequate protection in hardware (current and pulse width limitation) and 
in the gateware (Implementation of an thermal model of the 
blocking output circuit inside the FPGA, effectively resulting in dynamic regulation of output 
frequency).\\ Nonetheless these calculations are still relevant to v2
.1 boards and earlier, and the final recommended duty cycle will still be applicable in these 
boards, 
even with future releases of the gateware. Moreover, the calculations presented here remain of 
great value and demonstrate the procedure to follow to translate MOSFET datasheet thermal 
characteristics, into switching frequency limits similar to the calculations in \ref{sec:blo-outp} and \cite{an10273}.\\}}


\vspace*{11pt}
Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for the
calculations below.

\begin{figure}[h]
  \centerline{\includegraphics[width=.98\textwidth]{fig/blo-outp}}
  \caption{Blocking output stage}
  \label{fig:blo-outp}
\end{figure}

%------------------------------------------------------------------------------
% SUBSEC: max. pulse freq
%------------------------------------------------------------------------------
\subsection{Maximum blocking pulse duty cycle}
\label{app:blo-max-freq}

The maximum blocking pulse duty cycle is dictated by the output stage, which contains
a BSH103 transistor~\cite{bsh103} that has been found to be the failing component when the pulse frequency becomes too high.
The maximum duty cycle will be calculated in this section, considering the nominal (1.2~$\mu$s)
blocking pulse widths \cite{blo-std}. All calculations presented here are for operation starting at
25~$^\circ$C.

Due to the presence of the transformer in the blocking output stage, the MOSFET will enter
into avalanche mode at the falling edge of the pulse, since the current which was increasing
through the transformer primary during the pulse will still be present at the end of the pulse.
Since at the falling edge of the pulse the transistor is turned off and there is still a current
at its gate, the voltage at the transistor drain will rise sharply and the transistor will go
into avalanche mode.

NXP application note AN10273~\cite{an10273} details MOSFET avalanche rugedness and a method to
calculate whether a MOSFET will be capable to withstand repeated avalanche events at specific
frequencies. In summary, due to the fact current is still present in the circuit after transistor
turn-off, the power dissipated on the transistor leads to a rise in the transistor's temperature.
To make sure that the transistor withstands the avalanche event, one must make sure its temperature
does not rise above a threshold of 170$^\circ$C~\cite{an10273}.

The calculation presented here will follow the example in section 6 of NXP AN10273~\cite{an10273}
on the blocking output stage in Figure~\ref{fig:blo-outp}, in some way abstracting the effects the secondary
has on the primary.

To start, the avalanche current, which is the current at the end of the 1.2~$\mu$s pulse~\cite{blo-std},
can be calculated from the current rise through the RL circuit formed by the 100~$\mu$H transformer primary
and the 0.5~$\Omega$ $R_{ds(ON)}$ of the BSH103 MOSFET~\cite{bsh103},

\begin{align}
I_{AS} & = \frac{V_{BLO\_24V}}{R_{ds(ON)}}\left(1 - e^{-\frac{R_{ds(ON)}}{L}}t\right) \nonumber\\
       & = \frac{27}{0.5} \left( 1 - e^{-1.2{\mu} \frac{0.5}{100{\mu}}} \right) \nonumber \\
       & = 323 mA
\end{align}

To account for possible effects that the secondary might have on the primary, the value
of the avalanche current will be rounded off to,

\begin{equation}
I_{AS} = 400 mA
\end{equation}

At the end of the pulse, the voltage across the inductor will be

\begin{equation}
V_{BR} - V_{BLO\_24V} = L\frac{dI_{AS}}{dt}
\end{equation}

\noindent where $V_{BR}$ is the breakdown voltage of the MOSFET~\cite{an10273},

\begin{equation}
V_{BR} = 1.3 \times V_{DS(max.)} \nonumber \\
\end{equation}

In the case of the BSH103~\cite{bsh103},

\begin{equation}
V_{BR} = 39V \\
\end{equation}

The time in which the avalanche current decays to zero is the avalanche time, due to the
fact that this is the time for which the voltage at the drain of the transistor will be
$V_{BR}$, and can be calculated based on the voltage across the inductor as,

\begin{equation}
dt_{AV} = \frac{L}{V_{BR} - V_{BLO\_24V}}dI_{AS}
\end{equation}

Integrating this equation yields

\begin{align}
t_{AV} & = \frac{L}{V_{BR} - V_{BLO\_24V}}I_{AS} \nonumber \\
       & = \frac{100{\mu}H}{39V - 27V} \times 400 \times 10^{-3} \nonumber \\
       & = 3.33{\mu}s \label{av-time}
\end{align}

With this, the single-shot avalanche energy can be calculated based on the peak power avalanche dissipation,
which occurs at the start of the avalanche period, and the avalanche time~\cite{an10273},

\begin{align}
E_{AS} & = \frac{P_{AV(pk)} \times t_{AV}}{2} = \frac{I_{AV} \times V_{BR} \times t_{AV}}{2} \nonumber \\
       & = \frac{400mA \times 39V \times 3.33{\mu}s}{2} \nonumber \\
       & = 25.97{\mu}J
\end{align}

Once the single-shot avalanche energy is known, the repetitive avalanche power dissipation
can be calculated taking into account the pulse frequency~\cite{an10273},

\begin{equation}
P_{AV(R)} = E_{AS} \times f
\end{equation}

Knowing the repetitive avalanche event power dissipation helps in finding the
temperature rise~\cite{an10273},

\begin{equation}
{\Delta}T_j = P_{AV(R)} \times R_{th(j-amb)}
\end{equation}

\noindent where $R_{th(j-amb)}$ is the junction-to-ambient thermal resistance of the package,
140~K/W in the case of the BSH103~\cite{bsh103}.

In the case at hand, knowing that the temperature starts at 25~$^{\circ}$C and has to rise
to no more than 170~$^{\circ}$C, the temperature rise is

\begin{center}
${\Delta}T_j = 145^{\circ}C$, or ${\Delta}T_j = 145K$
\end{center}

Using these three previous equations, the maximum pulse frequency can be calculated from

\begin{align}
f_{max} & = \frac{{\Delta}T_j}{E_{AS} \times R_{th(j-amb)}} \nonumber \\
        & = \frac{145K}{25.97{\mu}J \times 140K/W} \nonumber \\
        & = 39.88 kHz
\end{align}

The minimum pulse period can be calculated from this to be

\begin{equation}
T_{p(min)} = \frac{1}{f_{max}} \cong 25{\mu}s
\end{equation}

and the maximum duty cycle

\begin{equation}
{\delta}_{max} = \frac{T_{pulse}}{T_{p(min)}} = \frac{1.2{\mu}s}{25{\mu}s} = 0.048
\end{equation}

To reach the final maximum duty cycle for the blocking pulses, the possibility
of other channels operating at high frequencies around a particular transistor
has been taken into account. Other channels operating around the transistor would
mean the board temperature would increase the starting operating temperature for
the transistor. This in turn means that the power dissipation needs to be derated.
To account for this power derating, the final maximum duty cycle is obtained as the maximum
duty cycle divided by 10,

\begin{equation}
{\delta}_{max, final} = \frac{{\delta}_{max}}{10} \cong 0.005
\end{equation}

This yields to a minimum period of,

\begin{equation}
T_{min} = \frac{T_{pulse}}{{\delta}_{max, final}} = \frac{1.2{\mu}s}{0.005} = 240{\mu}s
\end{equation}

The value stated in the CONV-TTL-BLO User Guide~\cite{ctb-ug} is 1~$\mu$s more than
this value, due to the fact that the FPGA logic~\cite{ctb-hdlguide} contains a pulse
repeater module which enters in a rejection period after a pulse arrives at the input.
Since this logic is sampled, if there is jitter on input pulses arriving at a frequency
of 4166 Hz, which corresponds to the 1/200 duty cycle of the pulses, the logic may still
be in the rejection state counting the rejection period. This in turn may lead to a pulse
being missed and not replicated at the output. To avoid any pulses being missed, the
minimum period stated in the CONV-TTL-BLO User Guide~\cite{ctb-ug} is,

\begin{equation}
T_{min, final} = 241 {\mu}s
\end{equation}

\noindent and respectively, the maximum pulse frequency,

\begin{equation}
f_{max, final} = \frac{1}{T_{min, final}} = 4150 Hz
\end{equation}


%==============================================================================
% APP: Block outp stage calc in the burst mode
%==============================================================================
\pagebreak
\section{Frequency limits implemented in Version 4 boards}
\label{app:freq-limits}

From experimental measurements and functional specifications, a 2MHz maximum frequency limit is 
implemented in gateware for $250ns$-wide pulses and 104kHz for $1.2\mu s$~\cite{ctb-ug}. After 
tests on the v3.0 prototypes it was found that jitter in the pulses at the blocking input of the 
FPGA, mean that pulse repetition at maximal frequency (2MHz) corresponding to periods of $500ns$,
 is difficult to achieve with any consistency. In effect it means that some pulses, may be missed if 
jitter causes them to be shorter than the required $500ns$. As a result, internal to the 
FPGA, a lower pulse limit is implemented, exactly one clock cycle shorter (One system clock cycle 
corresponds to $50ns$), to allow for errors caused through jitter.\\
The gateware limits therefore set maximum repetition frequency for $250ns$-wide pulses at ~2.22
MHz, corresponding to $450ns$. The limit is~$\approx104.7kHz$, i.e. $9550ns$ instead of the 
required $9600ns$ for wide $1.2\mu$s pulses.\\

The guaranteed, error-free, repetition times are therefore as advertised in the user guide \cite{
ctb-ug}, $500ns$ and $9600ns$ for the short and wide modes of operation.\\
\textbf{\textit{Repetition at rates below these values is possible, but is not 
guaranteed to be error-free, and therefore not advertised in the user manual, nor is it recommended.
}}
%==============================================================================
\end{appendices}
%==============================================================================


%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hwg-conv-ttl-blo}
\addcontentsline{toc}{section}{References}

\end{document}