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Conv TTL Blocking - Hardware
Commit 00f551e6 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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New version of the hw guide for v4 boards

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doc/hwg/cern-title.tex
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......@@ -25,7 +25,7 @@
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\\textit{Last edited by {\textbf{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}}
\textit{Last edited by {\textbf{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}}
\noindent \rule{\textwidth}{.05cm}
......
doc/hwg/hwg-conv-ttl-blo.bib
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......@@ -88,7 +88,7 @@ Date = {July 2015}
author = {{NXP Semiconductor}},
title = {{Power MOSFET single-shot/repetitive avalanche ruggedness rating}},
day = 27,
month = March,
month = 03,
year = 2009,
note = {\url{http://www.nxp.com/documents/application_note/AN10273.pdf}}
}
......@@ -108,7 +108,7 @@ Date = {July 2015}
author = {{Philips Semiconductor}},
title = {{BSH103 N-channel enhancement mode MOS transistor}},
day = 11,
month = February,
month = 02,
year = 1998,
note = {\url{http://www.nxp.com/documents/data_sheet/BSH103.pdf}}
}
doc/hwg/hwg-conv-ttl-blo.tex
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......@@ -467,10 +467,12 @@ The maximum 24~V pulse duty cycle that can be safely sustained by the input stag
\vspace*{11pt}
\noindent The blocking output stage is a flyback converter design with a 1:1 conversion
ratio, shown in Figure~\ref{fig:blo-outp-cap}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. This part of the board has been subject to a review a redesign for v3 boards and later, this is desicussed in detail in~\cite{bib:blo-out-protect}.
ratio, shown in Figure~\ref{fig:blo-outp-v4}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. This part of the board has been subject to a review and a redesign for v3 boards and later, this is discussed in detail in~\cite{blo-out-protect}.
In previous versions of the board (v2.1 and earlier) the transformer was driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
This however exposed the transformer and MOSFET to potential damage, due to uncontrolled current flow from the power supply. For this reason in boards v3 and later, a current limiting resistor is added between the transformer primary and the 24 V rail as shown in fig.\ref{fig:blo-outp-v4}. The presence of the resistor between the decoupling capacitor
This however exposed the transformer and MOSFET to potential damage, due to uncontrolled current flow from the power supply.\\
For this reason in boards v3 and later, a current limiting resistor is added between the transformer primary and the 24 V rail as shown in Fig.\ref{fig:blo-outp-v4}. The presence of the resistor between the decoupling capacitor
and power supply, causes the capacitor to charge at power on. When a pulse comes through from the FPGA, the voltage across the inductor changes and current starts to flow from the capacitor and resistor through to the transformer.\\
The snubber circuit next to the transformer formed by the BAR66 diode and the Zener diode
provides a means to dissipate the energy stored in the leakage inductance of the transformer
......@@ -483,34 +485,35 @@ when the MOSFET is on.
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp-v4}}
\centerline{\includegraphics[width=1.1\textwidth]{fig/blo-outp-v4}}
\caption{Blocking output stage- v3 and later.}
\label{fig:blo-outp-v4}
\end{figure}
Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
inputs are pulled-down on startup, thus avoiding spurious signals on blocking outputs. Though these were left in tri-state at startup in v2.1 boards, it was seen that this can cause irreversible damage to the board in some circumstances such as hot-swaps \cite{bib:hotswap-issue}.
The extra pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid
on startup.
The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
signal common with the TTL output enable, and a separate, blocking output enable signal.
These two signals go through the IC10 NAND gate to enable the buffers. When the FPGA does
not drive either of these signals, the output enable input of the buffers is kept high via
the pull-up resistor.
\begin{figure}[h]
\centerline{\includegraphics[scale=1]{fig/blo-outp-tristate-v4}}
\centerline{\includegraphics[scale=0.5]{fig/blo-outp-tristate-v4}}
\caption{Blocking output tri-state buffers}
\label{fig:blo-outp-tristate}
\end{figure}
In order to further protect the blocking output stage MOSFET, a pulse width limitation circuit is added on v3 board and later. This circuit can be seen in Fig. \ref{fig:blo-outp-v4} at the gate of the BSH103. It consists of a differentiator RC circuit}, capable of detecting rising pulse edges. The $\tau=RC$ time constant will determine how long the MOSFET is left ON following the rising edge of a pulse. The gate voltage will reach the threshold gate trigger value after $\approx 8\mu s$ to make sure that the gate voltage remains well above threshold during the $1.2\mu s$ window (longest output pulse length) (See~\cite{bib:blo-out-protect} for more details).
In order to further protect the blocking output stage MOSFET, a pulse width limitation circuit is added on v3 boards and later. This circuit can be seen in Fig. \ref{fig:blo-outp-v4} at the gate of the BSH103. It consists of a differentiator RC circuit, capable of detecting rising pulse edges. The $\tau=RC$ time constant will determine how long the MOSFET is left ON following the rising edge of a pulse. The gate voltage will reach the threshold gate trigger value after $\approx 8\mu s$ to make sure that the gate voltage remains well above threshold during the $1.2\mu s$ window, longest output pulse length (See~\cite{blo-out-protect} for more details).
In board versions 2.1 and earlier, the maximum pulse duty cycle that can be sustained without damaging the MOSFET
considering nominal blocking pulse widths~\cite{blo-std} of 1.2~$\mu$s, is approximately 4160~Hz
(see Appendix~\ref{app:blo-max-freq}). However, by implementing the blocking output stage protection techniques mentioned earlier and outlined in~\cite{bib:blo-out-protect}, these duty cycles can be significantly improved upon. In fact, to achieve very high repetition frequencies, the CONv-TTL-BLO board now offers a pulse-width selection feature, that allows for frequencies of up to 2MHz to be reached, when using narrow pulses ($250ns$). These high repetition frequencies are possible as part of a burst mode functionality, which allows the board to operate at higher frequencies but for a limited amount of time (see~\cite{bib:blo-out-protect} and~\cite{bib:ctb-ug} for more details on operation in this mode).
(see Appendix~\ref{app:blo-max-freq}). However, by implementing the blocking output stage protection techniques mentioned earlier and outlined in~\cite{blo-out-protect}, these duty cycles can be significantly improved upon.\\
In fact, to achieve very high repetition frequencies, the gateware for CONV-TTL-BLO board for v4 and later, offers a pulse-width selection feature, that allows for frequencies of up to 2MHz to be reached, when using narrow pulses ($250ns$). These high repetition frequencies are possible as part of a burst mode functionality, which allows the board to operate at higher frequencies but for a limited amount of time (see~\cite{blo-out-protect} and~\cite{ctb-ug} for more details on operation in this mode).
Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
inputs are pulled-down on startup, thus avoiding spurious signals on blocking outputs. Though these were left in tri-state at startup in v2.1 boards, it was seen that this can cause irreversible damage to the board in some circumstances such as hot-swaps \cite{hotswap-issue}.
The extra pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid on startup.
The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
signal common with the TTL output enable, and a separate, blocking output enable signal.
These two signals go through the IC10 NAND gate to enable the buffers. When the FPGA does
not drive either of these signals, the output enable input of the buffers is kept high via
the pull-up resistor.
The blocking output stage is susceptible to common-impedance coupling, due to the high inter-winding
capacitance of the selected transformer. The solution to this problem is provided in the form of the
......@@ -638,7 +641,8 @@ The PCB version is provided to the FPGA via a resistor network offering 4 bits f
and 2 bits for potential revisions. The circuit is shown in Fig.~\ref{fig:pcb-version}.
\begin{figure}[h]
\centering
\includegraphics\includegraphics[scale=0.5]{fig/pcb-version.png}
\includegraphics[scale=0.5]{fig/pcb-version.png}
\caption{Hard-wired PCB versioning}
\label{fig:pcb-version}
\end{figure}
......
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