Commit 91a25598 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Doc: updated guide with limit on number of blocking channels per crate.

parent 00f551e6
......@@ -42,7 +42,7 @@ Date = {July 2015}
@misc{sch,
title = {{CONV-TTL-BLO Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V4_sch.pdf}}
}
@misc{rtmm-sch,
......
......@@ -524,13 +524,6 @@ For more details about this common-impedance coupling event, see~\cite{crosstalk
\vspace{11pt}
\noindent \textbf{\textit{Note that if the FPGA is improperly configured, a DC high-level signal
on the power MOSFET's grid pin will yield a too high current passing through the MOSFET,
which will lead to its failure. Make sure the FPGA pins driving the blocking output stage
are properly configured to drive time-limited pulses or a DC low-level at the power
MOSFET's grid, or that the blocking output enable signal from the FPGA is low, so as to
keep the outputs of the tri-state buffers in high-impedance.}}
%------------------------------------------------------------------------------
% SEC: Blocking pulse rep
%------------------------------------------------------------------------------
......@@ -623,7 +616,7 @@ for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of~\cite{ctb-hdlguide}.
TTL (front panel), INV channels and blocking (rear panel) pulse LEDs are driven by the FPGA
TTL (front panel), INV channels (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
the Schmitt trigger is connected directly to the VME P2 connector and through
the RTM to the piggyback, where the current-limiting resistor and the LEDare located.
......@@ -734,7 +727,7 @@ calculations below.
\subsection{Minimum blocking pulse level}
\label{app:blo-min-level}
The optocoupler LED has a forward voltage of 1.5~V and therefore when the LED is on,
The optocoupler LED has a maximal forward voltage of 1.8~V and therefore when the LED is on,
the voltage in point 2 of Figure~\ref{fig:blo-inp} is
\begin{equation}
......@@ -827,6 +820,24 @@ I_{LED,RMS} = I_{LED} \sqrt{\delta}
\section{Blocking output stage calculations}
\label{app:blo-outp}
\textbf{\textit{ Since the following calculations were originally intended to document design
decisions
related with v2.1 boards and implemented in release 3.0 of the gateware, they are no longer
applicable for v4 boards.\\
Indeed, the blocking output protection discussed in Sec.\ref{sec:blo-outp} and in
\cite{blo-out-protect}, means that frequency of repetition can be considerably
increased, by relying on adequate protection in hardware (current and pulse width limitation) and
in the gateware (Implementation of an thermal model of the
blocking output circuit inside the FPGA, effectively resulting in dynamic regulation of output
frequency).\\ Nonetheless these calculations are still relevant to v2
.1 boards and earlier, and the final recommended duty cycle will still be applicable in these
boards,
even with future releases of the gateware. Moreover, the calculations presented here remain of
great value and demonstrate the procedure to follow to translate MOSFET datasheet thermal
characteristics, into switching frequency limits similar to the calculations in \ref{sec:blo-outp} and \cite{an10273}.\\}}
\vspace*{11pt}
Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for the
calculations below.
......@@ -1007,6 +1018,31 @@ T_{min, final} = 241 {\mu}s
f_{max, final} = \frac{1}{T_{min, final}} = 4150 Hz
\end{equation}
%==============================================================================
% APP: Block outp stage calc in the burst mode
%==============================================================================
\pagebreak
\section{Frequency limits implemented in Version 4 boards}
\label{app:freq-limits}
From experimental measurements and functional specifications, a 2MHz maximum frequency limit is
implemented in gateware for $250ns$-wide pulses and 104kHz for $1.2\mu s$~\cite{ctb-ug}. After
tests on the v3.0 prototypes it was found that jitter in the pulses at the blocking input of the
FPGA, mean that pulse repetition at maximal frequency (2MHz) corresponding to periods of $500ns$,
is difficult to achieve with any consistency. In effect it means that some pulses, may be missed if
jitter causes them to be shorter than the required $500ns$. As a result, internal to the
FPGA, a lower pulse limit is implemented, exactly one clock cycle shorter (One system clock cycle
corresponds to $50ns$), to allow for errors caused through jitter.\\
The gateware limits therefore set maximum repetition frequency for $250ns$-wide pulses at ~2.22
MHz, corresponding to $450ns$. The limit is~$\approx104.7kHz$, i.e. $9550ns$ instead of the
required $9600ns$ for wide $1.2\mu$s pulses.\\
The guaranteed, error-free, repetition times are therefore as advertised in the user guide \cite{
ctb-ug}, $500ns$ and $9600ns$ for the short and wide modes of operation.\\
\textbf{\textit{Repetition at rates below these values is possible, but is not
guaranteed to be error-free, and therefore not advertised in the user manual, nor is it recommended.
}}
%==============================================================================
\end{appendices}
%==============================================================================
......
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