Commit f8c8511c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Added RTM Interface Tester files

This tester card tests that the RTM interface on CONV-TTL-BLO front module cards
works as intended.
parent f341b181
......@@ -4,6 +4,9 @@ CONV-TTL-BLO hardware project
This project contains source files for boards which do not go into EDMS, as well
as possible documentation for the cards.
The following folders contain the files for tester cards:
- RTM_Interface_Tester -- tester card for the FM PTS
The latest source files for boards that go into EDMS can be found at the
following links:
......
Field=Description~String~Description~100|Field=Comment~String~Comment~100|Field=Designator~String~Designator~416|Field=Quantity~Integer~Quantity~100|ReportField=Currency~<none>|ReportField=ProductionQuantity~1|ReportField=ProjectFileName~RTM_Interface_Tester.PrjPCB|ReportField=ProjectFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB|ReportField=Title~Bill of Materials For Project [RTM_Interface_Tester.PrjPCB] (No PCB Document Selected)|ReportField=TotalQuantity~25|ReportField=ReportTime~10:21:21 AM|ReportField=ReportDate~7/1/2013|ReportField=ReportDateTime~7/1/2013 10:21:21 AM|ReportField=OutputName~Bill of Materials|ReportField=OutputType~BOM_PartType|ReportField=GeneratorName~BOM|ReportField=GeneratorDescription~Bill of Materials|ReportField=VariantName~None|ReportField=Address1~|ReportField=Address2~|ReportField=Address3~|ReportField=Address4~|ReportField=ApprovedBy~|ReportField=Author~|ReportField=CheckedBy~|ReportField=CheckedDate~-|ReportField=CompanyName~|ReportField=CreateDate~4/24/2013|ReportField=CurrentDate~7/1/2013|ReportField=CurrentTime~10:21:13 AM|ReportField=Date~|ReportField=Designer~Theodor-Adrian Stana|ReportField=DivGrp~BE/CO|ReportField=DocumentFullPathAndName~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.SchDoc|ReportField=DocumentName~RTM_Interface_Tester.SchDoc|ReportField=DocumentNumber~|ReportField=DrawnBy~Theodor-Adrian Stana|ReportField=EDA_Number~|ReportField=Engineer~Theodor-Adrian Stana|ReportField=ImagePath~|ReportField=ModifiedBy~-|ReportField=ModifiedDate~7/1/2013|ReportField=Organization~|ReportField=ProjectName~RTM_Interface_Tester.PrjPCB|ReportField=Projet~Blocking Pulse Repeater PTS|ReportField=Revision~|ReportField=Rule~|ReportField=SheetNumber~|ReportField=SheetTotal~|ReportField=Time~|ReportField=Title~PTS|ReportField=Title2~RTM Interface Tester|ReportField=DataSourceFileName~RTM_Interface_Tester.PrjPCB|ReportField=DataSourceFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB
Resistor - 0.1%|51|R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18|18
Connector 160zabcd Female (5x32)|HAR-BUS 64|P2|1
Transient Voltage Suppressor Diode (Bi-Directional)|SMBJ30CA|D1, D2, D3, D4, D5, D6|6
This diff is collapsed.
Record=TopLevelDocument|FileName=RTM_Interface_Tester.SchDoc
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