Blocking output stage
This can be caused by incorrect gateware loaded on the FPGA, which may cause longer, or even continuous, pulses on the MOSFET gate. Higher pulse repetition rates may also cause this problem.
LT Spice Simulation of the Blocking output stage
Below, in fig.1, is the circuit simulated in LTSpice. Of course specific components are modeled by their respective SPICE modeles, as provided by the manufacturer.
Figure 1: Blocking output stage circuit as modeled on LT
SPICE
Figure 2: Blocking pulse output Vs +5V FPGA input pulse
Current flow during and after a pulse:
When the MOSFET is turned off at the end of a pulse, the current through L1 continues to flow and so the voltage across the MOSFET sees a sudden sharp rise. This event is known as the single-shot avalanche breakdown event. It causes large junction temperatures at the drain of the MOSFET, which in turn leads to irreversible damage of the component. In the case of repetitive pulses, even if each pulse is within Safe Operating ARea (SOAR) ratings, repeated stress can cumulatively cause damage to the device.
After the MOSFET is turned off,drain voltage will remain at breakdown level for avalanche time ta, until current decays to zero. This time directly depends on the inductance, breakdown voltage and the peak drain current reached.
Transistor datasheet should normally include a SOAR curve to determine whether the peak current combined with the avalanche time, are within acceptable limits, for a given junction temperature.
The Repetitive avalanche breakdown SOAR is more difficult to characterise, and is therefore a derated version of the single-shot avalanche event SOAR.
In the CONV-TTL-BLO board, the BSH103 MOSFET datasheet unfortunately lacks some of the information required to characterise avalanche operation, namely, the Id Vs ta SOAR curves. However, in order to mitigate the effects of such events, two views of the problem must be taken:
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At the pulse level: pulse width should be such that the peak
drain current reached at the end of it remains within recommended
values. Moreover, since the value of the peak current will affect
the avalanche time proportionally, it should be limited.
The blocking standard requires blocking pulses of 1.2us width. Therefore the peak drain current expected will be dictated by the inductance and simple calculation will give it at approximately 324mA.
The LT spice simulation predicts peak current of 870mA, which constitutes a large difference from the calculated value. This is due to ~550mA offset the simulation adds to the current during pulse rise time (which is also being removed during fall time). Whether this offset exists on the board also remains to be verified (through measurements). Nonetheless, it would therefore be sensible to assume a worst case peak current value of 1A.
This peak current will result in an avalanche time ta=