Commit 1dee9525 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Added field to control and status register for reading the pcb version number

parent e9236008
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-- Title : Wishbone slave core for PTS control and status registers
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-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Dec 4 13:46:54 2014
-- File : .\pts_regs.vhd
-- Author : auto-generated by wbgen2 from .\pts_regs.wb
-- Created : 06/19/17 17:23:25
-- Standard : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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......@@ -39,17 +39,19 @@ entity pts_regs is
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'Rear pulse enable' in reg: 'CSR'
pts_csr_rearpt_o : out std_logic;
-- Port for std_logic_vector field: 'PCB version number' in reg: 'CSR'
pts_csr_hwvers_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
-- Ports for BIT field: 'Reset bit -- active only if RST_UNLOCK is 1' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
-- Port for std_logic_vector field: 'RTM detection lines' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic;
......@@ -154,6 +156,7 @@ begin
rddata_reg(2) <= pts_csr_rledt_int;
rddata_reg(3) <= pts_csr_ttlpt_int;
rddata_reg(4) <= pts_csr_rearpt_int;
rddata_reg(13 downto 8) <= pts_csr_hwvers_i;
rddata_reg(14) <= pts_csr_rst_unlock_i;
rddata_reg(15) <= pts_csr_rst_i;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
......@@ -163,12 +166,6 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
......@@ -219,12 +216,13 @@ begin
pts_csr_ttlpt_o <= pts_csr_ttlpt_int;
-- Rear pulse enable
pts_csr_rearpt_o <= pts_csr_rearpt_int;
-- PCB version number
-- Reset unlock bit
pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit
-- Reset bit -- active only if RST_UNLOCK is 1
pts_csr_rst_o <= wrdata_reg(15);
-- switches
-- RTM
-- RTM detection lines
-- I2C communication error
pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error
......
......@@ -108,6 +108,20 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "PCB version number";
description = "6 bits representing HW/PCB version number \
4 MSB represent HW version number \
2 LSB represent number of execution \
Eg: value 010010 represents PCB version 4.2";
prefix = "hwvers";
type = SLV;
align = 8;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \
......
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