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Conv TTL Blocking - Testing
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Conv TTL Blocking - Testing
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3e6eea7b
Commit
3e6eea7b
authored
Oct 26, 2017
by
Maciej Lipinski
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[DOC] added the hwvertest test to the documentation
parent
a5f734f7
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-1
cern-title.tex
fm/doc/hdlg/cern-title.tex
+1
-1
hdlg-pts-conv-ttl-blo.tex
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
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fm/doc/hdlg/cern-title.tex
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3e6eea7b
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@@ -9,7 +9,7 @@
\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
December 11, 2014
\hfill
October 26, 2017
\vspace*
{
3cm
}
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fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
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3e6eea7b
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@@ -73,6 +73,7 @@ work, see \\
11-12-2014
&
1.0
&
Updated document according to converter board documentation template, added licensing
information, updated information according to changes in HDL, added memory map
as appendix, removed redundant information
\\
26-10-2017
&
1.1
&
Added Test hwvertest and updated wishbone regsiter maps
\\
\hline
\end{tabular}
}
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@@ -183,6 +184,21 @@ for the gateware in Appendix~\ref{app:memmap}.
\section
{
Test logic
}
\label
{
sec:test-logic
}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
\subsection
{
Test hwvertest -- PCB version test
}
The PTS software verifies whether the version of the PCB is the one expected to
be tested with this PTS. Each PTS is prepared for a particular version of PCB
and it cannot be used to test other version of hardware.
The test reads the PCB version provided in an HWVERS register (see Annex~
\ref
{
app:pts-regs-csr
}
).
If the provided version is different than the expected version, no further tests is
run and PTS is stopped.
\textbf
{
This test is a prerequisite to run all the other tests.
}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
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