Commit 475b9acc authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Merge remote-tracking branch 'rw-origin/denia-dev' into HEAD

parents 153099b5 45ceab6b
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill December 11, 2014
\hfill October 26, 2017
\vspace*{3cm}
......@@ -24,7 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
......@@ -73,6 +73,7 @@ work, see \\
11-12-2014 & 1.0 & Updated document according to converter board documentation template, added licensing
information, updated information according to changes in HDL, added memory map
as appendix, removed redundant information \\
26-10-2017 & 1.1 & Added Test hwvertest and updated wishbone regsiter maps\\
\hline
\end{tabular}
}
......@@ -183,6 +184,21 @@ for the gateware in Appendix~\ref{app:memmap}.
\section{Test logic}
\label{sec:test-logic}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 00
%--------------------------------------------------------------------------------------
\subsection{Test 00 -- PCB version test}
The PTS software verifies whether the version of the PCB is the one expected to
be tested with this PTS. Each PTS is prepared for a particular version of PCB
and it cannot be used to test other version of hardware.
The test reads the PCB version provided in an HWVERS register (see Annex~\ref{app:pts-regs-csr}).
If the provided version is different than the expected version, no further tests is
run and PTS is stopped.
\textbf{This test is required to pass for the PTS to run the remaining tests.}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
......
\subsection{PTS control and status registers}
\label{app:pts-regs}
\label{app:pts-regs-csr}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{gray}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & BIDR & pts\_bidr & BIDR\\
0x4& REG & CSR & pts\_csr & CSR\\
0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & CSR & Control and Status Register\\
0x8 & (2) & LSR & Line Status Register\\
\end{longtable}
\end{tabular}
}
\noindent Note (1): The reset value of the status bits in the CSR cannot be specified, since it is based on the
the state of the on-board switches and whether an RTM is plugged in or not. Control bits in the CSR default to 0.
\subsubsection{Register description}
\paragraph*{BIDR}\vspace{12pt}
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\subsubsection{BIDR -- Board ID Register}
\label{app:pts-regs-bidr}
\vspace{12pt}
Board ID Register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -58,18 +57,22 @@ is plugged into the channel or not.
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\paragraph*{CSR}\vspace{12pt}
\subsubsection{CSR -- Control and Status Register}
\label{app:pts-regs-csr}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -83,7 +86,7 @@ Reset value: 0x54424c4f
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{gray!25}HWVERS[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
......@@ -130,6 +133,13 @@ REARPT
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
......@@ -170,15 +180,21 @@ I2C\_WDTO
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\label{app:pts-regs-lsr}
\paragraph*{LSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -223,9 +239,6 @@ REAR
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
......
This diff is collapsed.
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 15, 2015
\hfill July 13, 2018
\vspace*{3cm}
......@@ -24,7 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
......@@ -119,7 +119,7 @@ focuses on installing the test system (scripts, preparing shortcuts, etc.) on th
\label{sec:rack}
To setup the rack for the PTS system, we will need to insert an RTM Interface Tester
card to the back side of the ELMA crate placed inside the 19'' rack. You will need
card into the back of the ELMA crate placed inside the 19'' rack. You will need
an RTM Interface Tester card to set up the system, so this would be a good time to
obtain one.
......@@ -151,6 +151,9 @@ system to gain remote access to the laptop, the installation of the system can a
on the laptop directly. However, the steps related to network drivers and configuration
should be followed in order to have a properly working PTS system.
Also note that the admin account should be named \verb=pts-administrator=. This account
name is important as it is embedded in the PTS scripts (Password \verb=pts-admin=).
The guide should be followed until \textbf{step 17} of section \textbf{Set up the PTS user account}.
After this step, the guide is SVEC-related and need not be followed. We will continue with
the details in the next section to test our system and network was properly installed.
......@@ -171,7 +174,8 @@ the details in the next section to test our system and network was properly inst
Escape character is '^]'.
login:admin
password: ADMIN
%>
%>
$
\end{verbatim}
\vspace{11pt}
\item Make sure the ELMA crate has gateware version 2.31 or higher on it. In the SysMon Telnet prompt:
......@@ -220,12 +224,12 @@ We will detail here the simplest of the two, downloading the ready-made archive.
See Appendix~\ref{app:build} for details on the second.
\begin{enumerate}
\item Log in to the \verb=pts= user on the laptop
\item Log in to the \verb=pts-administrator= user on the laptop
\item Open up a terminal window, download the PTS folder structure tarball from OHWR
to the home folder of the \verb=pts= user and extract the archive:
\begin{verbatim}
cd ~
wget http://www.ohwr.org/attachments/download/3777/ubuntu.tar.gz
wget https://www.ohwr.org/attachments/5822/ubuntu.tar.gz
tar xzvf ubuntu.tar.gz
\end{verbatim}
Note that you can also copy the archive from a USB stick instead of downloading it from OHWR.
......@@ -259,7 +263,7 @@ See Appendix~\ref{app:build} for details on the second.
\begin{verbatim}
chmod a+w *
\end{verbatim}
\item Now we that have the test scripts on the system we can create a dedicated
\item Now that we have the test scripts on the system we can create a dedicated
user that will be used to run the PTS for the CONV-TTL-BLO. Open up Ubuntu's
\textbf{User Accounts} window (click the \verb=pts= user account name at the top-right
side of the screen), unlock this window by providing the \verb=pts= user account's
......@@ -286,9 +290,9 @@ See Appendix~\ref{app:build} for details on the second.
\begin{verbatim}
cd ~
cp .bashrc .bashrc.old
cp /home/pts/ubuntu/ttlbl/config/bashrc.pts .bashrc
cp /home/pts-administrator/ubuntu/ttlbl/config/bashrc.pts .bashrc
cd ~/Desktop/
cp /home/pts/ubuntu/ttlbl/config/*.desktop .
cp /home/pts-administrator/ubuntu/ttlbl/config/*.desktop .
\end{verbatim}
\item Right-click on the terminal icon in the launcher bar at the left and click \textbf{Lock to Launcher}
\item Close the terminal window
......@@ -298,7 +302,7 @@ See Appendix~\ref{app:build} for details on the second.
\begin{itemize}
\item on the Desktop, right-click and select \textbf{Change Desktop Background}
\item hit the \textbf{+} under Wallpapers
\item navigate to \verb=/home/pts/ubuntu/ttlbl/config/=
\item navigate to \verb=/home/pts-administrator/ubuntu/ttlbl/config/=
\item select \verb=ttlbl-background.png= as the background image
\item make sure the scaling of the image is set to \textbf{Zoom}
\end{itemize}
......@@ -355,12 +359,16 @@ In order to build a test system from scratch, follow these steps:
git clone git://ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-tst.git
\end{verbatim}
\end{small}
\item Run \verb=make= in the \verb=pts-fm/= folder, setting the options as appropriate
\item Run \verb=make= in the \verb=fm/pts/= folder, setting the options as appropriate
in your case:
\begin{verbatim}
cd conv-ttl-blo-tst/fm/
cd conv-ttl-blo-tst/fm/pts
make # ... set options here ...
\end{verbatim}
\item Copy the entire \verb=./ubuntu= folder to the \verb=pts-administrator= home directory. Type:
\begin{verbatim}
cp -r ./ubuntu /home/pts-administrator/
\end{verbatim}
\end{enumerate}
This will generate an archive similar to that downloaded in Section~\ref{sec:environment},
......
This diff is collapsed.
This diff is collapsed.
\subsection{PTS control and status registers}
\label{subsec:wbgen:pts}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & BIDR & pts\_bidr & BIDR\\
0x4& REG & CSR & pts\_csr & CSR\\
0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{BIDR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
Board ID Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\end{small}
\end{itemize}
\paragraph*{CSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCH[7:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CHLEDT}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHLEDT
} [\emph{read/write}]: Channel pulse LED enable
\\
1 -- Enable channel LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
STLEDT
} [\emph{read/write}]: Status LED enable
\\
1 -- Enable front panel bicolor LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
RLEDT
} [\emph{read/write}]: Rear pulse LED line
\\
1 -- Set LED lines high \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TTLPT
} [\emph{read/write}]: TTL test enable
\\
1 -- Enable pulse generation from CH1 \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
REARPT
} [\emph{read/write}]: Rear pulse enable
\\
1 -- Enable rear panel pulse generation \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit -- active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
SWITCH
} [\emph{read-only}]: switches
\\
1 - switch is ON \\ 0 - switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines
\\
1 - line active \\ 0 - line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\paragraph*{LSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\end{itemize}
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS control and status registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Dec 4 13:46:54 2014
-- File : .\pts_regs.vhd
-- Author : auto-generated by wbgen2 from .\pts_regs.wb
-- Created : 10/27/17 10:49:32
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -39,17 +39,19 @@ entity pts_regs is
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'Rear pulse enable' in reg: 'CSR'
pts_csr_rearpt_o : out std_logic;
-- Port for std_logic_vector field: 'PCB version number' in reg: 'CSR'
pts_csr_hwvers_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
-- Ports for BIT field: 'Reset bit -- active only if RST_UNLOCK is 1' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
-- Port for std_logic_vector field: 'RTM detection lines' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic;
......@@ -154,6 +156,7 @@ begin
rddata_reg(2) <= pts_csr_rledt_int;
rddata_reg(3) <= pts_csr_ttlpt_int;
rddata_reg(4) <= pts_csr_rearpt_int;
rddata_reg(13 downto 8) <= pts_csr_hwvers_i;
rddata_reg(14) <= pts_csr_rst_unlock_i;
rddata_reg(15) <= pts_csr_rst_i;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
......@@ -163,12 +166,6 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
......@@ -219,12 +216,13 @@ begin
pts_csr_ttlpt_o <= pts_csr_ttlpt_int;
-- Rear pulse enable
pts_csr_rearpt_o <= pts_csr_rearpt_int;
-- PCB version number
-- Reset unlock bit
pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit
-- Reset bit -- active only if RST_UNLOCK is 1
pts_csr_rst_o <= wrdata_reg(15);
-- switches
-- RTM
-- RTM detection lines
-- I2C communication error
pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error
......
......@@ -108,6 +108,20 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "PCB version number";
description = "6 bits representing HW/PCB version number \
4 MSB represent HW version number \
2 LSB represent number of execution \
Eg: value 010010 represents PCB version 4.2";
prefix = "hwvers";
type = SLV;
align = 8;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \
......
......@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -59,7 +59,7 @@
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......
......@@ -182,6 +182,24 @@ NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# PCB version pins
#------------------------------------------------------------------------------
NET "pcbrev_i[0]" LOC = A3;
NET "pcbrev_i[0]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[1]" LOC = A4;
NET "pcbrev_i[1]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[2]" LOC = R4;
NET "pcbrev_i[2]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[3]" LOC = P4;
NET "pcbrev_i[3]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[4]" LOC = V3;
NET "pcbrev_i[4]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[5]" LOC = Y3;
NET "pcbrev_i[5]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
#=============================================================================
......
......@@ -155,6 +155,9 @@ entity pts is
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
......@@ -312,6 +315,8 @@ architecture arch of pts is
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'Blocking test enable' in reg: 'CSR'
pts_csr_rearpt_o : out std_logic;
-- Port for std_logic_vector field: 'PCB version number' in reg: 'CSR'
pts_csr_hwvers_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
......@@ -627,6 +632,7 @@ architecture arch of pts is