Commit 70cebc0f authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Added pcb version input pins to top entity. Link pcb version number to status…

Added pcb version input pins to top entity. Link pcb version number to status and control register. updated component and port map of pts_regs for pcb version
parent 1dee9525
......@@ -154,6 +154,10 @@ entity pts is
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
......@@ -312,6 +316,8 @@ architecture arch of pts is
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'Blocking test enable' in reg: 'CSR'
pts_csr_rearpt_o : out std_logic;
-- Port for std_logic_vector field: 'PCB version number' in reg: 'CSR'
pts_csr_hwvers_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
......@@ -655,6 +661,7 @@ architecture arch of pts is
signal i2c_err_bit_rst_ld : std_logic;
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches : std_logic_vector(7 downto 0);
signal pcb_version : std_logic_vector(5 downto 0);
signal line_front : std_logic_vector(5 downto 0);
signal line_inv : std_logic_vector(3 downto 0);
signal line_rear : std_logic_vector(5 downto 0);
......@@ -916,6 +923,9 @@ begin
-- RTM lines combo
rtm_lines <= rtmp_i & rtmm_i;
switches <= not sw_gp_n_i;
-- PCB version
pcb_version <= pcbrev_i;
-- LSR signals
line_front <= not (ttl_n_i);
......@@ -946,7 +956,8 @@ begin
pts_csr_stledt_o => stat_led_en,
pts_csr_rledt_o => rear_led_en,
pts_csr_ttlpt_o => front_pulse_en,
pts_csr_rearpt_o => rear_pulse_en,
pts_csr_rearpt_o => rear_pulse_en,
pts_csr_hwvers_i => pcb_version,
pts_csr_rst_unlock_o => rst_unlock_ldval,
pts_csr_rst_unlock_i => rst_unlock,
pts_csr_rst_unlock_load_o => rst_unlock_ld,
......
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